CN107046003A - 低温多晶硅tft基板及其制作方法 - Google Patents

低温多晶硅tft基板及其制作方法 Download PDF

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Publication number
CN107046003A
CN107046003A CN201710412498.6A CN201710412498A CN107046003A CN 107046003 A CN107046003 A CN 107046003A CN 201710412498 A CN201710412498 A CN 201710412498A CN 107046003 A CN107046003 A CN 107046003A
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Prior art keywords
grid
doped region
layer
polysilicon portion
substrate
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CN201710412498.6A
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CN107046003B (zh
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王涛
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to CN201710412498.6A priority Critical patent/CN107046003B/zh
Priority to PCT/CN2017/089620 priority patent/WO2018218712A1/zh
Priority to US15/735,614 priority patent/US10355138B2/en
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Abstract

本发明提供一种低温多晶硅TFT基板及其制作方法。该制作方法包括：在基板上依次形成遮光部、缓冲层及岛状多晶硅部，对岛状多晶硅部两侧进行离子轻掺杂，形成掺杂区和沟道区；依次形成栅极绝缘层和栅极，栅极覆盖沟道区且其两端均超出沟道区的两端一段距离并覆盖部分掺杂区；对未被栅极覆盖的掺杂区进行离子重掺杂，形成N型重掺杂区和N型轻掺杂区；在栅极上形成层间绝缘层，及与N型重掺杂区电连接的源漏极。该方案可通过栅极电压控制轻掺杂区的阻抗变化，以有效抑制N‑TFT产生翘曲效应，提升器件的工作特性。

Description

低温多晶硅TFT基板及其制作方法
技术领域
本发明涉及液晶显示面板制作领域，特别是涉及一种低温多晶硅TFT基板及其制作方法。
背景技术
在信息社会的当代，作为可视信息传输媒介的显示器的重要性在进一步加强，为了在未来占据主导地位，显示器正朝着更轻、更薄、更低能耗、更低成本以及更好图像质量的趋势发展。
低温多晶硅(Low Temperature Poly-silicon，LTPS)技术是新一代TFT(ThinFilm Transistor，薄膜晶体管)基板的制造技术，与传统非晶硅(a-Si)技术的最大差异在于，低温多晶硅显示器反应速度较快，且有高亮度、高解析度与低耗电量等优点。
一般地，N型低温多晶硅TFT(Thin Film Transistor，薄膜晶体管)基板，通常为自准直的N-TFT结构，其栅极覆盖位于其下方的多晶硅未掺杂区(即沟道区)，而与掺杂区不重叠。然而，这种低温多晶硅TFT基板的设计中，由于其轻掺杂区的阻抗是恒定不变无法调节的，在较高的漏极电压下，将使得漏极区域存在严重的碰撞电离，从而产生翘曲效应(kinkeffect)，导致对器件的长期稳定工作造成不利影响。
因此，现有技术存在缺陷，急需改进。
发明内容
本发明的目的在于提供一种改进的低温多晶硅TFT基板及其制作方法。
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种低温多晶硅TFT基板的制作方法，包括：
提供一基板；
在基板上设置遮光部，以及形成缓冲层；
在缓冲层上沉积低温多晶硅层，对低温多晶硅层进行图形化处理，以在每一遮光部对应上方形成一岛状多晶硅部，并对岛状多晶硅部进行无差别的整面离子掺杂；
在岛状多晶硅部上涂布光阻，对该光阻进行图形化处理形成光阻部，以该光阻部为掩膜对岛状多晶硅部两侧进行离子轻掺杂，形成位于岛状多晶硅部两侧的掺杂区以及位于两侧掺杂区之间的沟道区；
去除光阻部，在岛状多晶硅部上依次形成栅极绝缘层和第一金属层，并对第一金属层进行图形化处理，以在岛状多晶硅部对应上方形成栅极，其中，所述栅极的宽度小于所述岛状多晶硅部的宽度，所述栅极覆盖所述岛状多晶硅部的沟道区，且所述栅极的两端均超出所述沟道区的两端一段距离并覆盖部分掺杂区；
以栅极为掩膜对未被栅极覆盖的掺杂区进行离子重掺杂，形成位于岛状多晶硅部两侧的N型重掺杂区，并将位于N型重掺杂区与沟道区之间的掺杂区作为N型轻掺杂区；
在栅极上形成层间绝缘层，及与N型重掺杂区电连接的源极和漏极。
在一些实施例中，以光阻部为掩膜对岛状多晶硅部两侧进行离子轻掺杂的离子为P离子。
在一些实施例中，以栅极为掩膜对未被栅极覆盖的掺杂区进行离子重掺杂的离子为P离子。
在一些实施例中，对岛状多晶硅部进行无差别的整面离子掺杂的离子为B离子。
在一些实施例中，在基板上设置遮光部的步骤包括：
利用物理气相沉积技术在基板上沉积第二金属层并涂布光阻；
通过黄光工艺和刻蚀工艺，对第二金属层进行刻蚀，形成相互间隔的多个遮光部。
在一些实施例中，在栅极上形成层间绝缘层，及与N型重掺杂区电连接的源极和漏极的步骤包括：
通过化学气相沉积技术整面沉积层间绝缘层；
通过黄光制程在该层间绝缘层、栅极绝缘层上对应在N型重掺杂区的上方形成第一过孔，以使N型重掺杂区露出；
在基板上沉积第三金属层，对第三金属层进行图案化处理形成源极和漏极，该源极和漏极分别经由第一过孔与N型重掺杂区电连接。
在一些实施例中，在基板上依次形成栅极绝缘层和第一金属层，并对第一金属层进行图形化处理，以在岛状多晶硅部对应上方形成栅极的步骤包括：
通过化学气相沉积技术在基板上沉积绝缘层；
通过物理气相沉积技术在基板上沉积第一金属层并涂布光阻；
通过黄光工艺和刻蚀工艺，对第一金属层进行刻蚀，形成相互间隔的多个栅极。
在一些实施例中，在栅极上形成层间绝缘层，及与N型重掺杂区电连接的源极和漏极之后，该方法还包括：
在层间绝缘层、源极和漏极上一次沉积平坦层和公共电极材料层；
通过黄光工艺和刻蚀工艺去除位于漏极上方的公共电极材料层，以在平坦层上形成公共电极；
在平坦层和公共电极上形成钝化层；
通过黄光制程在平坦层、钝化层上对应在漏极的上方形成第二过孔，以使漏极露出；
整面沉积像素电极材料层，对像素电极材料层图形化处理，以在平坦层上形成多个像素电极，每一像素电极通过第二过孔与漏极电连接。
在一些实施例中，像素电极的制备材料为氧化铟锡。
相应地，本发明提供一种低温多晶硅TFT基板，包括：
基板；
基板；
遮光部，其设置在基板上；
缓冲层，其设置在基板和遮光部上；
多晶硅部，其设置在缓冲层上，每一多晶硅部包括：位于多晶硅部中间的沟道区、位于多晶硅部两端的N型重掺杂区、及位于沟道区与相邻的N型重掺杂区之间的N型轻掺杂区；
栅极绝缘层，其设置在多晶硅部和缓冲层上；
栅极，其设置在栅极绝缘层上，所述栅极的宽度小于所述多晶硅部的宽度，且所述栅极覆盖所述多晶硅部的沟道区及N型轻掺杂区；
层间绝缘层，其设置在栅极和栅极绝缘层上；
源极，其设置在层间绝缘层上，并与所述多晶硅部一端的N型重掺杂区电连接；
漏极，其设置在层间绝缘层上，并与所述多晶硅部另一端的N型重掺杂区电连接。
本发明提供的低温多晶硅TFT的制作方法包括：在基板上依次形成遮光部、缓冲层及岛状多晶硅部，对岛状多晶硅部两侧进行离子轻掺杂，形成掺杂区和沟道区；依次形成栅极绝缘层和栅极，栅极覆盖沟道区且其两端均超出沟道区的两端一段距离并覆盖部分掺杂区；对未被栅极覆盖的掺杂区进行离子重掺杂，形成N型重掺杂区和N型轻掺杂区；在栅极上形成层间绝缘层，及与N型重掺杂区电连接的源漏极。该方案将低温多晶硅TFT基板中的N-TFT结构更改为栅极和轻掺杂区有重叠的N-TFT结构，从而可通过栅极电压控制轻掺杂区的阻抗变化，以有效抑制N型TFT产生翘曲效应，提升器件的工作特性。
附图说明
图1为本发明优选实施例中低温多晶硅TFT基板的制作方法的流程示意图。
图2A-图2C为本发明优选实施例中低温多晶硅TFT基板的制程示意图。
图3为本发明优选实施例中低温多晶硅TFT基板的一种结构示意图。
图4为本发明优选实施例中低温多晶硅TFT器件的一种结构示意图。
图5为本发明优选实施例中低温多晶硅TFT器件的另一种结构示意图。
具体实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在附图中，组件相似的模块是以相同标号表示。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
参阅图1，图1为本发明优选实施例中低温多晶硅TFT基板的制作方法的流程示意图。如图1所示，本优选实施例的低温多晶硅TFT基板的制作方法，包括：
S101、提供一基板，在基板上设置遮光部，以及形成缓冲层；
S102、在缓冲层上沉积低温多晶硅层，对低温多晶硅层进行图形化处理，以在遮光部对应上方形成岛状多晶硅部，并对岛状多晶硅部进行无差别的整面离子掺杂；
S103、在岛状多晶硅部上涂布光阻，对该光阻进行图形化处理形成光阻部，以该光阻部为掩膜对岛状多晶硅部两侧进行离子轻掺杂，形成位于岛状多晶硅部两侧的掺杂区以及位于两侧掺杂区之间的沟道区；
S104、去除光阻部，在岛状多晶硅部上依次形成栅极绝缘层和第一金属层，并对第一金属层进行图形化处理，以在岛状多晶硅部对应上方形成栅极，其中，所述栅极的宽度小于岛状多晶硅部的宽度，栅极覆盖岛状多晶硅部的沟道区，且栅极的两端均超出沟道区的两端一段距离并覆盖部分掺杂区；
S105、以栅极为掩膜对未被栅极覆盖的掺杂区进行离子重掺杂，形成位于岛状多晶硅部两侧的N型重掺杂区，并将位于N型重掺杂区与沟道区之间的掺杂区作为N型轻掺杂区；
S106、在栅极上形成层间绝缘层，及与N型重掺杂区电连接的源极和漏极。
以下将结合图2A-图2C对以上低温多晶硅TFT基板的制作方法的步骤进行详细描述。
步骤S101中，该基板可为玻璃基板。遮光部的制备材料可以为不透明的金属材料，以防止背光源光线直接照射到TFT对基板的逻辑电路造成影响，可由不透明的金属(如Al、Ag、Cu、Mo、Au等)或叠层设置，还可由各金属的合金制成。在一些实施方式中，参考图2A，可利用PVD(Physical Vapor Deposition，物理气相沉积)技术在基板100上沉积第二金属层11，然后涂布光阻，通过黄光工艺和刻蚀工艺，对第二金属层11进行刻蚀，形成相互间隔的多个遮光部111。
然后，可采用CVD(Chemical Vapor Deposition，化学气相沉积)技术整面沉积绝缘材料，以在遮光部111和基板100上形成缓冲层12。其中，缓冲层12为氮化硅层与氧化硅层的复合层。在一些实施方式中，氮化硅层的厚度为40～100nm，氧化硅层的厚度可100～200nm。
在步骤S102中，参考图2A，整面沉积低温多晶硅层13。在一些实施方式中，可采用黄光工艺和刻蚀工艺对低温多晶硅层13进行图形化处理，以在遮光部111对应上方形成岛状多晶硅部131。然后对岛状多晶硅部131进行无差别的整面离子掺杂(离子注入)，以调整N-TFT的阈值电压(Vth)。其中，对岛状多晶硅部131进行整面离子掺杂的离子为B离子。
在步骤S103中，继续参考图2A，可采用涂布的方式在缓冲层12上涂布光阻，然后通过全曝光工艺对该光阻进行图形化处理形成光阻部14。其中，该光阻部14形成于岛状多晶硅部131的上方，且位于该岛状多晶硅部131的中间部分，该光阻部14宽度约为岛状多晶硅部131宽度的1/3～1/2之间。
以该光阻部14为掩膜对岛状多晶硅部131的两侧进行离子轻掺杂，形成位于岛状多晶硅部131两侧的掺杂区1311以及位于两侧掺杂1311区之间的沟道区(即未掺杂区)1312。其中，以光阻部14为掩膜对岛状多晶硅部131两侧进行离子轻掺杂的离子为P离子。
参考图2A，在步骤S104中，可采用光阻剥离工艺或光阻灰化去除光阻部14。然后，可采用CVD技术在基板100上沉积栅极绝缘层15，再采用PVD技术在栅极绝缘层15上形成第一金属层16。其中，栅极绝缘层15的制备材料可为氮化硅或氧化硅；第一金属层的材料可以为钼。
然后，在第一金属层16涂布一层厚度均匀的光阻，通过黄光工艺和刻蚀工艺对第一金属层16进行刻蚀，以在岛状多晶硅部131对应上方形成相互间隔的多个栅极161。其中，栅极161的宽度小于岛状多晶硅部131的宽度，栅极161覆盖岛状多晶硅部的沟道区1312，且栅极161的两端均超出沟道区1312的两端一段距离，从而覆盖部分掺杂区1311。其中，栅极161的两端均超出沟道区1312的两端的一段距离可约为1～2μm。
在步骤S105中，参考图2A和图2B，以栅极161为掩膜对未被栅极覆盖的掺杂区1311进行离子重掺杂，形成位于岛状多晶硅部131两侧的N型重掺杂区1311A，并将位于N型重掺杂区1311A与沟道区1312之间的掺杂区1311作为N型轻掺杂区1311B，其宽度可为1.5μm左右。其中，以栅极161为掩膜对未被栅极161覆盖的掺杂区1311进行离子重掺杂的离子为P离子。
在步骤S106中，可采用CVD技术整面沉积绝缘材料，以在栅极绝缘层15和栅极161上形成层间绝缘层17。其中，层间绝缘层17可为氮化硅层、氧化硅层、或二者的组合。
随后，通过黄光制程在该层间绝缘层17、栅极绝缘层15上对应在N型重掺杂区1311A的上方形成第一过孔，以使两个N型重掺杂区1311A露出。其中，第一过孔包括位于栅极161一侧的过孔P1和位于另一侧形成的过孔P2，该N型重掺杂区1311A可以全部露出，也可以部分露出。
然后，可采用PVD技术整面沉积第三金属层18。在通过黄光工艺、刻蚀工艺对第三金属层18进行图案化处理，以在层间绝缘层17上形成源极181和漏极182，使得源极181经由过孔P1与岛状多晶硅部131一侧的N型重掺杂区1311A电连接，漏极182经由过孔P2与岛状多晶硅部131另一侧的N型重掺杂区1311A电连接。其中，源极181和漏极182可为钼/铝/钼复合层。
参考图2B和图2C，在一些实施例中，在步骤S106之后，还可以在上述形成的TFT基板上依次形成平坦层19、公共电极101、钝化层102，以及在钝化层102上设置像素电极1031。
具体地，可通过CVD技术先在层间绝缘层17、源极181及漏极182上整面沉积平坦层19，然后在平坦层19上沉积公共电极材料层101。随后，可在公共电极材料层101上涂布光阻，通过黄光工艺和刻蚀工艺去除对应于漏极182上方的公共电极材料层101，以在平坦层19上形成公共电极1011。其中，平坦层19为绝缘材料层，公共电极1011可由透明导电金属氧化物或者透明导电金属薄膜制成。
然后，可通过CVD技术在平坦层19和公共电极1011上形成钝化层102。该钝化层102的制备材料可以为氮化硅、氧化硅等。再采用黄光制程在平坦层19、钝化层102上对应在漏极182的上方形成第二过孔Q，以使漏极182露出。其中，漏极182可部分露出。
在一些实施例中，可采用PVD技术整面沉积像素电极材料层103，然后，通过黄光工艺和刻蚀工艺对像素电极材料层103图形化处理，以在钝化层102上形成像素电极1031，使得该像素电极1031通过第二过孔Q与漏极182电连接。从而完成低温多晶硅TFT基板的制作。
实际应用中，像素电极1031的制备材料可为氧化铟锡(即ITO)，以增强像素电极的导电性。
由上可知，本发明实施例提供的低温多晶硅TFT基板的制作方法，将低温多晶硅TFT基板中的N-TFT结构更改为栅极和轻掺杂区有重叠的N-TFT结构，从而可通过栅极电压控制轻掺杂区的阻抗变化，以有效抑制N型TFT产生翘曲效应，提升器件的工作特性。
本发明实施例还提供一种低温多晶硅TFT基板。其中，低温多晶硅TFT基板包括有多个TFT，每个TFT对应一遮光部、一低温多晶硅部、一栅极、一源极、以及一漏极。
参考图3，该低温多晶硅TFT基板包括：
基板200；
遮光部21，其设置在基板200上；
缓冲层22，其设置在基板20和遮光部21上；
多晶硅部23，其设置在缓冲层22上，包括位于多晶硅部23中间的沟道区232、位于多晶硅部23两端的两个N型重掺杂区231A、及位于沟道区与相邻的N型重掺杂区231A之间的N型轻掺杂区231B；
栅极绝缘层24，其设置在多晶硅部23和缓冲层22上；
栅极25，其设置在栅极绝缘层24上，栅极25的宽度小于多晶硅部23的宽度，且栅极25覆盖多晶硅部23的沟道区232及N型轻掺杂区231B；
层间绝缘层26，其设置在栅极25和栅极绝缘层24上；
源极271，其设置在层间绝缘层26上，并与多晶硅部23一端的N型重掺杂区231A电连接；
漏极272，其设置在层间绝缘层26上，并与多晶硅部23另一端的N型重掺杂区231A电连接。
继续参考图3，在一些实施例中，该低温多晶硅TFT基板还可以包括：
平坦层28，其设置在源极271、漏极272和层间绝缘层26上；
公共电极29，其设置在平坦层28上；
钝化层201，其设置在公共电极29和平坦层28上；
像素电极202，其设置在钝化层201上。
其中，参考图4，栅极绝缘24、及层间绝缘层26上对应N型重掺杂区231A的上方设有第一过孔(P1和P2)，源极271与漏极272分别经由第一过孔(P1和P2)与N型重掺杂区231A电连接。
在一些实施例中，参考图5，平坦层28、钝化层201上对应漏极272的上方设有第二过孔Q，像素电极202经由第二过孔Q与漏极272电连接。
在一些实施例中，基板200可为玻璃基板。遮光部21可由不透明的金属(如Al、Ag、Cu、Mo、Au等)或叠层设置，还可由各金属的合金制成，以防止背光源光线直接照射到TFT对基板的逻辑电路造成影响。
在一些实施例中，缓冲层22可为氮化硅层与氧化硅层的复合层。在一些实施方式中，氮化硅层的厚度为40～100nm，氧化硅层的厚度可100～200nm。
在本发明实施例中，多晶硅部23整体可掺杂有B离子，以调整N-TFT的阈值电压(Vth)。其N型轻掺杂区231B可掺杂有少量P离子，其N型重掺杂区231B掺杂有较多的P离子。在一些实施方式中，N型轻掺杂区231B的宽度可设计为约为1.5μm左右。
在一些实施例中，栅极绝缘层24的制备材料可为氮化硅或氧化硅。而栅极25的制备材料可为钼。
在一些实施方式中，层间绝缘层26可为氮化硅层、氧化硅层、或二者的组合。
在一些实施例中，源极271和漏极272可为钼/铝/钼复合层。
本发明实施例中，平坦层28为绝缘材料层，如氮化硅层、氧化硅层等。而公共电极29则可由透明导电金属氧化物或者透明导电金属薄膜制成。
在一些实施例中，钝化层201的制备材料可以为氮化硅、氧化硅等。而像素电极202的制备材料可为氧化铟锡(即ITO)，以增强像素电极的导电性。
由上可知，本发明实施例提供的低温多晶硅的TFT基板，将低温多晶硅TFT基板中的N-TFT结构更改为栅极和轻掺杂区有重叠的N-TFT结构，由于栅极电压会在N型轻掺杂区感应出电荷，该N型轻掺杂区的阻抗会随栅极电压而变化，从而能有效抑制N-TFT漏极输出的扭结效应，提升器件的工作特性。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (10)

1.一种低温多晶硅TFT基板的制作方法，其特征在于，包括：
提供一基板；
在基板上设置多个遮光部、以及形成缓冲层；
在缓冲层上沉积低温多晶硅层，对低温多晶硅层进行图形化处理，以在每一遮光部对应上方形成一岛状多晶硅部，并对岛状多晶硅部进行无差别的整面离子掺杂；
在多晶硅层上涂布光阻，对该光阻进行图形化处理形成光阻部，以该光阻部为掩膜对岛状多晶硅部两侧进行离子轻掺杂，形成位于岛状多晶硅部两侧的掺杂区以及位于两侧掺杂区之间的沟道区；
去除光阻部，在岛状多晶硅部上依次形成栅极绝缘层和第一金属层，并对第一金属层进行图形化处理，以在岛状多晶硅部对应上方形成栅极，其中，所述栅极的宽度小于所述岛状多晶硅部的宽度，所述栅极覆盖所述岛状多晶硅部的沟道区，且所述栅极的两端均超出所述沟道区的两端一段距离并覆盖部分掺杂区；
以栅极为掩膜对未被栅极覆盖的掺杂区进行离子重掺杂，形成位于岛状多晶硅部两侧的N型重掺杂区，并将位于N型重掺杂区与沟道区之间的掺杂区作为N型轻掺杂区；
在栅极上形成层间绝缘层、及与N型重掺杂区电连接的源极和漏极。
2.如权利要求1所述的低温多晶硅TFT基板的制作方法，其特征在于，以光阻部为掩膜对岛状多晶硅部两侧进行离子轻掺杂的离子为P离子。
3.如权利要求2所述的低温多晶硅TFT基板的制作方法，其特征在于，以栅极为掩膜对未被栅极覆盖的掺杂区进行离子重掺杂的离子为P离子。
4.如权利要求1所述的低温多晶硅TFT基板的制作方法，其特征在于，对岛状多晶硅部进行无差别的整面离子掺杂的离子为B离子。
5.如权利要求1所述的低温多晶硅TFT基板的制作方法，其特征在于，在基板上设置遮光部的步骤包括：
利用物理气相沉积技术在基板上沉积第二金属层并涂布光阻；
通过黄光工艺和刻蚀工艺，对第二金属层进行刻蚀，形成相互间隔的多个遮光部。
6.如权利要求1所述的低温多晶硅TFT基板的制作方法，其特征在于，在栅极上形成层间绝缘层，及与N型重掺杂区电连接的源极和漏极的步骤包括：
通过化学气相沉积技术整面沉积层间绝缘层；
通过黄光制程在该层间绝缘层、栅极绝缘层上对应在N型重掺杂区的上方形成第一过孔，以使N型重掺杂区露出；
整面沉积第三金属层，对第三金属层进行图案化处理形成多个源极和多个漏极，每一源极和每一漏极分别经由第一过孔与N型重掺杂区电连接。
7.如权利要求1所述的低温多晶硅TFT基板的制作方法，其特征在于，在基板上依次形成栅极绝缘层和第一金属层，并对第一金属层进行图形化处理，以在岛状多晶硅部对应上方形成栅极的步骤包括：
通过化学气相沉积技术在基板上沉积绝缘层；
通过物理气相沉积技术在基板上沉积第一金属层并涂布光阻；
通过黄光工艺和刻蚀工艺，对第一金属层进行刻蚀，形成相互间隔的多个栅极。
8.如权利要求1所述的低温多晶硅TFT基板的制作方法，其特征在于，在栅极上形成层间绝缘层，及与N型重掺杂区电连接的源极和漏极之后，所述方法还包括：
在层间绝缘层、源极及漏极上依次沉积平坦层和公共电极材料层；
通过黄光工艺和刻蚀工艺去除位于漏极上方的公共电极材料层，以在平坦层上形成公共电极；
在平坦层和公共电极上形成钝化层；
通过黄光制程在平坦层、钝化层上对应在漏极的上方形成第二过孔，以使漏极露出；
整面沉积像素电极材料层，对像素电极材料层图形化处理，以在钝化层上形成多个像素电极，每一像素电极通过第二过孔与漏极电连接。
9.如权利要求1所述的低温多晶硅TFT基板的制作方法，其特征在于，像素电极的制备材料为氧化铟锡。
10.一种低温多晶硅TFT基板，其特征在于，包括：
基板；
遮光部，其设置在基板上；
缓冲层，其设置在基板和遮光部上；
多晶硅部，其设置在缓冲层上，每一多晶硅部包括：位于多晶硅部中间的沟道区、位于多晶硅部两端的N型重掺杂区、及位于沟道区与相邻的N型重掺杂区之间的N型轻掺杂区；
栅极绝缘层，其设置在多晶硅部和缓冲层上；
栅极，其设置在栅极绝缘层上，所述栅极的宽度小于所述多晶硅部的宽度，且所述栅极覆盖所述多晶硅部的沟道区及N型轻掺杂区；
层间绝缘层，其设置在栅极和栅极绝缘层上；
源极，其设置在层间绝缘层上，并与所述多晶硅部一端的N型重掺杂区电连接；
漏极，其设置在层间绝缘层上，并与所述多晶硅部另一端的N型重掺杂区电连接。
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