CN107039390A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN107039390A
CN107039390A CN201611032531.4A CN201611032531A CN107039390A CN 107039390 A CN107039390 A CN 107039390A CN 201611032531 A CN201611032531 A CN 201611032531A CN 107039390 A CN107039390 A CN 107039390A
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circuit board
hole
semiconductor chip
semiconductor packages
semiconductor
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蔡宪聪
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MediaTek Inc
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MediaTek Inc
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Abstract

本发明实施例提供了一种半导体封装。其包括：电路板，其包括：相对的第一和第二表面以及多个通孔；半导体芯片，形成于该电路板的该第一表面上，并且该半导体芯片的有源面朝向该电路板的该第一表面；以及多个导电连接，穿过该多个通孔并且将该半导体芯片与该电路板电性连接。本发明实施例，有助于降低电压降效应。

Description

半导体封装
技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体封装。
背景技术
一般的BGA(Ball Grid Array，球栅阵列)半导体封装包括：半导体芯片，安装在绝缘PCB(Printed Circuit Board，印刷电路板)基底的上表面。该基底可以由玻璃纤维填充的有机层压板制成，诸如FR4板、FR5板或者BT(bismaleimide triazine，双马来酰亚胺三嗪)板，并且该基底在其上下表面上具有互连的导电电路图案。***的包封(encapsulating)材料覆盖该芯片、该基底的上表面以及电导体(诸如接合线)，该电导体在该芯片和该基底的上表面上的电路图案之间延伸。导电球或者其他输入/输出(Input/output，I/O)端形成于该基底的下表面的电路图案上。
然而，虽然现有的BGA半导体封装已经足够用于其预期目的，但是现有的BGA半导体封装并非在各个方面完全令人满意。
发明内容
有鉴于此，本发明实施例提供了一种半导体封装，能够降低电压降效应。
本发明实施例提供了一种半导体封装，包括：电路板，其包括：相对的第一和第二表面以及多个通孔；半导体芯片，形成于该电路板的该第一表面上，并且该半导体芯片的有源面朝向该电路板的该第一表面；以及多个导电连接，穿过该多个通孔并且将该半导体芯片与该电路板电性连接。
其中，进一步包括：附着层，形成于该电路板的该第一表面与该半导体芯片的该有源面之间；其中，该多个通孔穿透该附着层以露出该有源面的部分。
其中，进一步包括：第一包封层，填充该多个通孔并且覆盖该多个导电连接。
其中，该多个通孔包括：第一通孔，露出该半导体芯片的该有源面的中央部分；以及第二通孔，露出该半导体芯片的该有源面的周边部分。
其中，该电路板包括：梯状部分，具有多个次层，并且该多个次层形成于该电路板的该第一表面和该第二表面之间，并且该多个通孔将该多个次层露出。
其中，该梯状部分设置于该电路板的位置邻近该半导体芯片的该有源面的周边部分。
其中，于该电路板的该第二表面上，该第一通孔形成第一沟道，并且该第二通孔形成多个彼此隔开的第二沟道，并且该多个第二沟道分别位于该第一沟道的两侧。
其中，于该电路板的该第二表面上，该第一和第二通孔形成为十字交叉结构。
其中，于该电路板的该第二表面上，该第一通孔包括：矩形通孔，并且该第二通孔形成连续的矩形沟道，其中，该连续的矩形沟道围绕该第一通孔。
其中，该梯状部分的该多个次层与该电路板的该第一表面和该第二表面均不共平面。
其中，该多个导电连接之一还电性连接设置于该多个次层之一上的接合垫。
其中，该半导体芯片的该有源面上的中央部分和周边部分均设置有多个接合垫，并且该多个通孔露出该多个接合垫，并且该多个导电连接分别电性连接至该多个接合垫。
其中，该多个导电连接为接合线。
其中，进一步包括：散热层，形成于该半导体芯片的上方，并且于该散热层与该半导体芯片之间没有设置任何衬垫；以及第二包封层，形成于该电路板上，并且覆盖该散热层、该半导体芯片和该电路板。
其中，该第二包封层不物理接触该半导体芯片的该有源面。
本发明实施例的有益效果是：
上述的半导体封装，在电路板上设置通孔，并且导电连接穿过该通孔来将半导体芯片与该电路板电性连接，因此能够优化半导体芯片与电路板之间的电性连接路径，从而降低半导体芯片的电压降效应。
附图说明
通过阅读接下来的详细描述和参考附图所做的示例，能够更加全面地理解本发明，其中：
图1为根据本发明实施例的半导体封装的横截面示意图；
图2为图1所示的半导体封装的俯视图；
图3为根据本发明另一实施例的半导体封装的横截面示意图；
图4为图3所示的半导体芯片的平面示意图；
图5～7为图3所示的电路板的仰视图。
具体实施方式
为了使本发明所解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
本发明涉及集成电路(Integrated Circuit，IC)装置，特别涉及一种半导体封装，具有降低的电压降(IR drop)效应和更加灵活的接合垫(bond-pad)设计。
图1示出了示范性的半导体封装10的横截面示意图，其包括：电路板12、半导体芯片20、衬垫(spacer)28、包封层30、散热(heat spreading)层32以及多个导电元件36。
如图1所示，该半导体芯片20例如为功能性芯片，诸如微处理器芯片、存储器芯片、逻辑芯片或者其他的功能性芯片，并且该半导体芯片20具有有源的(active)第一表面22和钝性的(inactive)第二表面24。该半导体芯片20的第一表面22包括：多个I/O垫A(或者接合垫)，位于邻近第一表面22的周边边缘的位置。通过磨光(polishing)第二表面24来使该半导体芯片20变薄。在一个实施例中，半导体芯片20可以具有大约4～8mil(密耳)的厚度。
半导体芯片20通过第一附着层(adhesive layer)18安置在电路板12上，例如电路板12的中央部分上。电路板12具有相对的第一和第二表面14和16，并且第一附着层18和半导体芯片20顺序地形成于电路板12的第一表面14上，例如其中央部分上。电路板12主要由树脂层(未示出)构成，该树脂层形成于BT板、FR4板、FR5板或者一些其他类的用来制作半导体封装的PCB基底的填充有玻璃纤维的有机(环氧树脂)层压板。另外，导电线路(conductive trace)及导电互连(均未示出)也形成于电路板12中，从而在半导体芯片20与导电元件36之间提供合适的电连接。第一附着层18可以包括：环氧树脂或类似物。
如图1所示，多个接合垫B及电性的导电电路图案(未示出)形成于电路板12的第一表面14上，并且导电元件36形成于电路板12的第二表面16上。半导体芯片20的每个I/O垫A通过导电连接34电性连接至接合垫B之一，其中该导电连接34跨越在半导体芯片20和接合垫B之间。如图1所示，导电连接34可以为由金或者铝形成的接合线。
另外，衬垫28通过第二附着层26安置在半导体芯片20的第一表面22上，例如其中央部分上。衬垫28例如为矩形的由空白的半导体晶圆制成的非功能性(non-functional)芯片，并且衬垫28可以包括：半导体材料，与半导体芯片20的半导体层(未示出)的材料相同。形成的衬垫28的横截面尺寸(例如宽度W1)小于半导体芯片20的横截面尺寸(例如宽度W2)。在一个实施例中，衬垫28的厚度大约4～10mil。
包封层30覆盖半导体芯片20的第一表面22、电路板12的第一表面14的一部分、以及散热层32的一部分，从而露出散热层32的顶面中位于衬垫28和半导体芯片20上方的部分。包封层30也填充散热层32与衬垫28之间的空间。通过使树脂材料(如环氧树脂)成型和固化或者通过浇注和固化液体树脂材料(如环氧树脂)来形成包封层30。散热层32例如可以形成为图1所示的像Ω一样的形状，该散热层32具有接触电路板12的部分并且可以由铜、铝或者另一金属合金形成。
导电元件36例如可以由铅锡焊料(lead tin solder)或者一些其他的金属来形成，并且作为半导体封装10的输入/输出(Input/output，I/O)端。每个导电元件36通过导电连接34、接合垫B、导电线路与导电互连(均未示出)而分别电性连接至半导体芯片20的I/O垫A，其中接合垫B形成于电路板12上，导电线路与导电互连(均未示出)形成于电路板12中。导电元件36允许半导体封装10安置在母板(未示出)上。其他配置的I/O端也是可能的。
图2示出了图1所示的半导体封装10的俯视图，并且图1示意了沿图2中的线1-1的横截面示意图。出于简化目的，在图2中，没有示出散热层32和包封层30，而示意了电路板12、半导体芯片20、衬垫28和导电连接34。
如图1及图2所示，于半导体芯片20的第一表面22上提供导电连接34以电性连接I/O垫A和接合垫B，其中I/O垫A形成于半导体芯片20的周边边缘附近，接合垫B形成于封装基底12的第一表面12上。
在图1～2所示的示范性的半导体封装10中，由于I/O垫全部位于半导体芯片20的第一表面22的周边边缘的附近，使得在半导体芯片20的I/O垫A和封装基底12上形成的接合垫B之间提供的导电连接34是密集配置的。因此，随着增加半导体芯片20中的有源或无源元件数量的趋势，半导体芯片20将具有更大的尺寸来容纳半导体芯片20的更多的I/O垫A和避免相邻的导电连接34之间的短路。
另外，由于全部的I/O垫位于半导体芯片20的第一表面22的周边边缘的附近，因此半导体芯片20需要形成更加复杂的互连结构，以连接有源或无源元件(例如位于半导体芯片20的中央部分)与I/O垫A，这意味着半导体芯片20的制造将变得更加复杂并且有源或无源元件同I/O垫A之间的路径的长度将会太长，其中有源或无源元件形成于半导体芯片20中，I/O垫A位于半导体芯片20的第一表面22的周边边缘附近。因此，例如位于半导体封装10的半导体芯片20的中央部分处的有源或无源元件将会出现非期望的电压(IR)降效应，如此，将影响半导体封装10的性能。
如此，需要一种改善的能够降低电压降效应的半导体封装。
图3示出了一种示范性的能够降低电压降效应的半导体封装100，其包括：电路板112、半导体芯片120、包封层130、散热层132以及多个导电元件136。
如图3所示，该半导体芯片120例如为功能性芯片，诸如微处理器芯片、存储器芯片、逻辑芯片或者其他的功能性芯片，并且该半导体芯片120具有有源的第一表面122和钝性的第二表面124。可以通过磨光该第二表面124来使该半导体芯片120变薄。在一个实施例中，该半导体芯片120可以具有大约4～18mil的厚度。
电路板112具有相对的第一和第二表面114和116，并且附着层118和半导体芯片120顺序地形成于电路板112的第一表面114的中央部分上。电路板112主要由树脂层(未示出)构成，该树脂层由BT(bismaleimide triazine，双马来酰亚胺三嗪)板、FR4板、FR5板或者一些其他类的用来制作用于半导体封装的PCB基底的填充有玻璃纤维的有机(如环氧树脂)层压板形成。另外，多层导电线路(conductive trace)及导电互连(均未示出)也形成于电路板112中，从而在半导体芯片120与导电元件136之间提供合适的电连接。附着层118可以包括：环氧树脂或类似物。
如图3所示，半导体芯片120通过附着层118安置于电路板112的中央部分上，并且半导体芯片120的第一表面122面向电路板112。半导体芯片120的第一表面122包括：多个I/O垫A′，其不仅位于第一表面的周边边缘处，而且也位于第一表面122的中央部分处。
另外，于电路板112中设置多个通孔(through hole)150以穿过电路板112的中央和周边部分。另外，通孔150也穿过附着层118的一部分以露出形成于半导体芯片120的第一表面122上的I/O垫A′。如图3所示，将电路板112的周边部分(接近半导体芯片120的第一表面122的周边边缘)设计为包括：梯状(stair-like)部分112a。该梯状部分112a具有多个次层160，垂直地形成于第一表面114和第二表面116之间并且由通孔150露出。另外，梯状部分112的次层160与电路板112的第一表面114和第二表面116不共平面。通孔150也露出电路板120的多个次层160中形成的导电线路和导电互连(均未示出)，并且多个接合垫B′形成于该导电线路和导电互连(均未示出)上，其中该导电线路和导电互连(均未示出)形成于电路板120的由通孔150露出的多个次层160中的每一个中。导电元件136形成于电路板112的第二表面116上。
另外，在通孔150中设置一条或者多条导电连接134，并且该一条或者多条导电连接134跨越在I/O垫A′和接合垫B′之间，以电性连接半导体芯片120与电路板112。如图3所示，导电连接134可以为由金或者铝形成的接合线。
另外，包封层130覆盖半导体芯片120的第二表面124及散热层132的部分，从而露出半导体芯片20的散热层132的顶面的位于半导体芯片120上方的部分。包封层130也填充散热层132与半导体芯片20之间的空间。另外，包封层130也填充通孔150并且覆盖通孔150露出的导电连接134、接合垫B′以及I/O垫A′。通过使树脂材料(如环氧树脂)成型和固化，或者通过浇注并固化液体树脂材料(如环氧树脂)来形成包封层130。散热层132例如可以形成图3所示的像Ω一样的形状，该散热层32具有接触电路板12的部分并且可以由铜、铝或者另一金属合金形成。需要说明的是，在一些实施例中，散热层32可以省略或者采用其他的形状或设置方式等。
如图3所示，由于半导体芯片120通过将有源的第一表面122(也可称为有源面)面向电路板112的方式安装于电路板112上，使得散热层132可以直接设置在半导体芯片132的钝性的第二表面124的上方，而无需在散热层132和第二表面124之间形成额外的热传导(thermal conductive)衬垫。相应地，可以降低半导体封装100的厚度。另外，导电元件136例如可以由铅锡焊料或者一些其他的金属制成，并且作为半导体封装110的I/O端。每个导电元件136通过导电连接134和接合垫B′而分别电性连接至半导体芯片120的I/O垫A′及接合垫B′，其中接合垫B′形成于导电线路与导电互连(均未示出)上，而该导电线路与导电互连(均未示出)形成于电路板112的梯状部分112a的次层160，并且该次层160由通孔150露出。导电元件136允许半导体封装110安置在母板(未示出)上。其他配置的I/O端也是可能的。
在图3所示的示范性的半导体封装100中，由于至少在第一表面122的中央部分提供了额外的I/O垫A，因此可以降低半导体芯片120中的电压降效应，并且使得在I/O垫A′与电路板112的梯状部分112a的次层160之间可以提供诸如接合线等导电连接134，其中I/O垫A′位于半导体芯片120的第一表面122的中央和周边部分上，并且通孔150露出次层160。
另外，由于I/O垫A′位于半导体芯片120的第一表面122的中央并周边部分，使得可以使用相对简单的布线结构来设计半导体芯片120中提供的互连结构，以连接有源或无源元件(位于半导体芯片120的中央部分)与I/O垫A′。因此，当趋势是形成更有影响的半导体芯片120时，可以简化半导体芯片120的制造，以及减少半导体芯片120的第一表面122的周边边缘附近的I/O垫A′的数量。
图4示出了图3所示的半导体芯片120的第一表面122的平面示意图。如图4所示，出于简化目的，仅示意了半导体芯片120的第一表面122上形成的I/O垫A′。
如图4所示，可以在半导体芯片120的第一表面122的周边边缘附近提供宽松的导电连接134(见图3)，以连接半导体芯片120的I/O垫A′和封装基底112上形成的接合垫B′。另外，由于在半导体芯片120的第一表面122的中央部分提供额外的I/O垫A′，因此可以降低半导体封装100的尺寸以在I/O垫A′和接合垫B′之间容纳更多的连接，由于收缩半导体封装100的尺寸的趋势，因此这是受欢迎的。
另外，在半导体封装100中，如图3～4中所示的I/O垫A′的配置允许更短的线回路(wire loop)和降低电压降效应，因此可以得到I/O垫的更灵活的IC设计。
图5～7为电路板112中形成的通孔的布局的各种实施例的示意图，其中示意了电路板112的第二表面116，其上具有凸块(如前述的导电元件136)。
如图5所示，提供一个具有矩形形状的通孔150来作为电路板112的中心，并且其他的通孔150形成连续的矩形沟道来围绕该具有矩形形状的通孔150，并且与该具有矩形形状的通孔150脱离开。
另外，如图6所示，在电路板112的第二表面116上设置了十字交叉状的通孔150。
另外，如图7所示，通孔150设置为通过电路板112彼此隔离的多个沟道。如图7所示，通孔150之一可以形成为第一沟道，而其他的通孔可以在第一沟道的相对侧上形成为第二沟道。
在其他的实施例中，根据半导体芯片120的I/O垫A′的各种设计，可以进一步调整通孔150的配置并且通孔150可以为其他形状，而不限制于图5～7所示的配置和形状。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (15)

1.一种半导体封装，其特征在于，包括：
电路板，其包括：相对的第一和第二表面以及多个通孔；
半导体芯片，形成于该电路板的该第一表面上，并且该半导体芯片的有源面朝向该电路板的该第一表面；以及
多个导电连接，穿过该多个通孔并且将该半导体芯片与该电路板电性连接。
2.如权利要求1所述的半导体封装，其特征在于，进一步包括：附着层，形成于该电路板的该第一表面与该半导体芯片的该有源面之间；其中，该多个通孔穿透该附着层以露出该有源面的部分。
3.如权利要求1所述的半导体封装，其特征在于，进一步包括：第一包封层，填充该多个通孔并且覆盖该多个导电连接。
4.如权利要求1所述的半导体封装，其特征在于，该多个通孔包括：第一通孔，露出该半导体芯片的该有源面的中央部分；以及第二通孔，露出该半导体芯片的该有源面的周边部分。
5.如权利要求1所述的半导体封装，其特征在于，该电路板包括：梯状部分，具有多个次层，并且该多个次层形成于该电路板的该第一表面和该第二表面之间，并且该多个通孔将该多个次层露出。
6.如权利要求5所述的半导体封装，其特征在于，该梯状部分设置于该电路板的位置邻近该半导体芯片的该有源面的周边部分。
7.如权利要求4所述的半导体封装，其特征在于，于该电路板的该第二表面上，该第一通孔形成第一沟道，并且该第二通孔形成多个彼此隔开的第二沟道，并且该多个第二沟道分别位于该第一沟道的两侧。
8.如权利要求4所述的半导体封装，其特征在于，于该电路板的该第二表面上，该第一和第二通孔形成为十字交叉结构。
9.如权利要求4所述的半导体封装，其特征在于，于该电路板的该第二表面上，该第一通孔包括：矩形通孔，并且该第二通孔形成连续的矩形沟道，其中，该连续的矩形沟道围绕该第一通孔。
10.如权利要求5所述的半导体封装，其特征在于，该梯状部分的该多个次层与该电路板的该第一表面和该第二表面均不共平面。
11.如权利要求5所述的半导体封装，其特征在于，该多个导电连接之一还电性连接设置于该多个次层之一上的接合垫。
12.如权利要求1所述的半导体封装，其特征在于，该半导体芯片的该有源面上的中央部分和周边部分均设置有多个接合垫，并且该多个通孔露出该多个接合垫，并且该多个导电连接分别电性连接至该多个接合垫。
13.如权利要求1所述的半导体封装，其特征在于，该多个导电连接为接合线。
14.如权利要求1所述的半导体封装，其特征在于，进一步包括：散热层，形成于该半导体芯片的上方，并且于该散热层与该半导体芯片之间没有设置任何衬垫；以及第二包封层，形成于该电路板上，并且覆盖该散热层、该半导体芯片和该电路板。
15.如权利要求14所述的半导体封装，其特征在于，该第二包封层不物理接触该半导体芯片的该有源面。
CN201611032531.4A 2015-12-17 2016-11-15 半导体封装 Pending CN107039390A (zh)

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