CN107026196B - 具有外质装置区无沟槽隔离的双极性接面晶体管 - Google Patents

具有外质装置区无沟槽隔离的双极性接面晶体管 Download PDF

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CN107026196B
CN107026196B CN201710061621.4A CN201710061621A CN107026196B CN 107026196 B CN107026196 B CN 107026196B CN 201710061621 A CN201710061621 A CN 201710061621A CN 107026196 B CN107026196 B CN 107026196B
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CN107026196A (zh
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R·玛拉迪
R·卡米洛-卡斯蒂洛
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Abstract

本发明涉及具有外质装置区无沟槽隔离的双极性接面晶体管，其揭示装置结构及用于装置结构的制造方法。在衬底中形成一或多个沟槽隔离区以围绕装置区。在该装置区上形成基极层。在该基极层上形成第一与第二发射极指。该装置区自该第一发射极指延展至该第二发射极指的第一部分无介电材料。

Description

具有外质装置区无沟槽隔离的双极性接面晶体管
技术领域
本发明大体关于半导体装置及积体电路制造，而且，尤其是有关于用于双极性接面晶体管及异质接面双极晶体管的制造方法及装置结构。
背景技术
就其它终端用途而言，可在射频收发器、数十亿位元模拟数字转换器、光学网路、汽车雷达及高速电路中可发现双极性接面晶体管。双极性接面晶体管可与互补式金属氧化物半导体(CMOS)场效晶体管在双极性互补式金属氧化物半导体(BiCMOS)积体电路中组合，其利用两种晶体管类型的有利特性。
双极性接面晶体管为三端点电子装置，其包括发射极、基极及集电极，配置成使得该基极置于该发射极与集电极之间。NPN双极性接面晶体管可包括构成该等发射极与集电极的n型半导体材料区、以及构成该基极的p型半导体材料区。PNP双极性接面晶体管包括构成该等发射极与集电极的p型半导体材料区、以及构成该基极的n型半导体材料区。在操作时，该基极发射极接面为正偏而该基极集电极接面为反偏。该集电极发射极电流可由该基极发射极电压所控制。
异质接面双极晶体管(HBT)是一种双极性接面晶体管，其中该发射极、本质基极、及/或集电极的二或更多者是由具有不均等能隙的半导体材料所组成，其建立异质接面。举例而言，异质接面双极晶体管的集电极及/或发射极可由硅所组成，而异质接面双极晶体管的基极可由硅锗所组成，其特征在于比硅更窄的能隙。在无线设计中，介于电子电路之间的介面是由低杂讯放大器(LNA)及功率放大器(PA)所提供，其各可包括具有SiGe基极的异质接面双极晶体管。
双极性接面晶体管及异质接面双极晶体管需要改良型制造方法及装置结构。
发明内容
在本发明的一具体实施例中，提供一种用于制造装置结构的方法。在衬底中形成一或多个沟槽隔离区以围绕装置区。在该装置区上形成基极层。在该基极层上形成呈相隔关系的第一与第二发射极指。该装置区自该第一发射极指延展至该第二发射极指的第一部分无介电材料。
在本发明的一具体实施例中，装置结构包括位在衬底中的一或多个沟槽隔离区。该一或多个沟槽隔离结构围绕装置区。该装置结构更包括位在该装置区上的基极层、以及位在该基极层上布置成相隔关系的第一与第二发射极指。该装置区自该第一发射极指延展至该第二发射极指的第一部分无介电材料。
附图说明
附图合并于本说明书的一部分并构成该部分，绘示本发明的各项具体实施例，并且连同上述对本发明的一般性说明、及下文对具体实施例提供的详细说明，目的是为了阐释本发明的具体实施例。
图1根据本发明的一具体实施例，用于制造装置结构的处理方法在初始制造阶段时，衬底的一部分的俯视图。
图1A基本上沿着图1所示线条1A-1A取看的截面图。
图2就根据本发明的一具体实施例制造的装置结构、及根据先前技术制造的装置结构，绘出截止频率的曲线图。
图3就根据本发明的一具体实施例制造的装置结构、及根据先前技术制造的装置结构，以集电极电流为函数绘出最大振荡频率的曲线图。
图4就根据本发明的一具体实施例制造的装置结构、及根据先前技术制造的装置结构，以基极集电极接面偏压为函数绘出基极集电极间电容的曲线图。
图5就根据本发明的一具体实施例制造的装置结构、及根据先前技术制造的装置结构，以两种不同基极发射极偏压的基极集电极接面偏压为函数绘出崩溃电压的曲线图。
图6就根据本发明的一具体实施例制造的装置结构、及根据先前技术制造的装置结构，以该集电极电流为函数绘出杂讯指数最小值的曲线图。
符号说明:
10 衬底
10a 顶端表面
11 部分
12 沟槽隔离区
13 部分
14 装置区
15 非导电性间隔物
16 集电极
17 集电极接触区
18 集电极接触区
20 基极层
20a 顶端表面
22 接垫
26 发射极指
27 发射极指
28 发射极指
29 发射极指
34 外质基极
36 本质基极
40 装置结构
41 基极接触部
50 本质装置区
60 外质装置区
102 曲线
103 曲线
104 曲线
105a 曲线
105b 曲线
106 曲线
112 曲线
113 曲线
114 曲线
115a 曲线
115b 曲线
116 曲线。
具体实施方式
请参阅图1、图1A，并且根据本发明的一具体实施例，衬底10包含可用于形成积体电路的装置的单晶半导体材料。构成衬底10的半导体材料可包括位于其顶端表面10a的外延层，其可含有一定量的电活性掺质，相对于衬底10的剩余部分增强其电气特性。举例而言，衬底10可包括单晶硅的外延层，该外延层就NPN晶体管在构造中掺有一浓度的n型掺质，该n型掺质出自周期表第五族(例如：磷(P)、砷(As)或锑(Sb))，所用的浓度对付与n型导电性有效。
沟槽隔离区12位于衬底10的半导体材料中。制造装置结构时使用的装置区14遭由沟槽隔离区12约束。装置区14由衬底10的半导体材料的一部分所构成。沟槽隔离区12从衬底10的顶端表面10a延展至顶端表面10a下方的浅深处。
沟槽隔离区12可通过沉积硬罩、利用微影与蚀刻程序界定沟槽以图型化此硬罩与衬底10、沉积电绝缘体以填充此等沟槽、使用化学机械研磨(CMP)程序相对于此硬罩平坦化此电绝缘体、以及移除此硬罩来形成。在一项具体实施例中，沟槽隔离区12可由二氧化硅(SiO2)所构成，其通过化学气相沉积(CVD)来沉积。沟槽隔离区12可包含浅沟槽隔离区及/或深沟槽隔离区。
集电极16可由装置区14的材料的一区段或全部所构成，位于诸沟槽隔离区12间。集电极16可含有浓度达到得以对其半导体材料有效付与n型导电性的n型掺质。集电极接触区17、18通过衬底10的半导体材料在沟槽隔离区12下方延展的部分与集电极16耦合。集电极接触区17、18相邻于集电极16而置，并且通过沟槽隔离区12与集电极16横向分开。
给定厚度的基极层20位于装置区14中衬底10的顶端表面上。基极层20与装置区14垂直对准而置，并且直接接触装置区14的单晶半导体材料。基极层20界定本质基极，其参与形成装置结构的发射极基极接面。
基极层20可由与装置区14不同的半导体材料所构成，并且可与集电极16具有相反的导电性类型。举例而言，基极层20可由半导体材料所构成，诸如呈合金的硅锗(SiGe)，其具有范围自95原子百分比至50原子百分比的硅(Si)含量、以及范围自5原子百分比至50原子百分比的锗(Ge)含量。基极层20的锗含量可跨布基极层20的厚度呈现均匀、或可跨布基极层20的厚度呈现阶化及/或步进。基极层20的半导体材料可包含掺质，诸如选自于浓度得有效付与p型导电性的周期表第三族p型掺质(例如：硼(B))、以及供选择地，用以抑制此p型掺质扩散的碳(C)。
基极层20可在装置区14的顶端表面上形成，并且可由单晶半导体材料(例如：单晶硅锗)所构成。包含基极层20的半导体材料可使用诸如气相外延术(VPE)的低温外延(LTE)生长程序来外延生长(epitaxially grown)。在沉积期间，装置区14的单晶半导体材料的晶体结构作用为外延生长用的模板。基极层20的生长在相邻发射极间外质装置区60中未遭受阻滞，因为半导体材料直接在装置区14上外延生长，而不是在装置区14的外边界或周界内部沟槽隔离区上生长。结果是外质装置区60中的单晶生长增厚，如此可降低外质基极电阻。
基极层20在包括内部沟槽隔离区的装置结构中正常观测的形貌方面没有变异，此等沟槽隔离区用于将相邻发射极隔离，并且将装置区14区分成各于此等发射极其中一者上专用的不同区段。本质装置区50中及外质装置区60中的基极层由单晶半导体材料所构成。外质装置区中因没有沟槽隔离区而导致单晶半导体材料生长，而不是导致经观测在沟槽隔离区的介电材料上所形成厚度更小的多结晶半导体材料生长。无沟槽隔离区所带来的另一效益在于，基极层20在自单晶半导体材料过渡至装置区14的外边界内侧的多结晶半导体材料的过程没有小面特性。装置结构的可靠度可通过将装置区14的外边界内的这些小面消除来改良。
沉积并图型化介电层以在基极层20的顶端表面20a上形成接垫22。接垫22可由二氧化硅所构成，是在后续形成发射极窗时使用。一或多个介电层沉积于基极层20的顶端表面20a及接垫22上，并且经图型化以形成发射极开口，此等发射极开口穿过介电层与接垫22而伸抵包含基极层20的单晶半导体材料的顶端表面20a。这一或多个介电层可由一或多个电绝缘体所构成，诸如氮化硅(Si3N4)、二氧化硅、及/或其它使用化学气相沉积沉积的材料。此等发射极开口可通过利用光微影及蚀刻程序将这一或多个介电层图型化来形成。
由发射极指26至29所构成的发射极于各别发射极开口中形成，并且经布置而成为有相隔关系的平行结构元件。基极层20的单晶半导体材料垂直位于发射极指26至29与集电极16之间。
发射极指26至29可由一层重度掺杂的半导体材料所形成，其经沉积而使得部分填充此等发射极开口，然后使用微影与蚀刻程序来图型化。举例而言，发射极指26至29可由以化学气相沉积法沉积并以一定浓度的掺质重度掺杂的多晶硅或多结晶硅锗所构成，此掺质例如为出自周期表第五族对付与n型导电性有效的杂质种类，诸如磷(P)或砷(As)。非导电性间隔物15将发射极指26至29包覆，并且可在形成发射极的程序期间予以形成。
外质基极34的区段可通过以受到控制的方式引进掺质而在基极层20的区段中形成，此掺质进行操作以提升其与基极层20的剩余部分相对的导电性。在一具体实施例中，外质基极34的区段在形成方面可通过离子布植来达成，而且具体而言，可通过以一浓度布植选自于周期表第三族的p型掺质(例如：硼)的离子来达成，此浓度得相对于基极层20的剩余部分有效提升p型导电性的程度。可选择离子种类、及离子的剂量与动能以提供所欲浓度。发射极指26至29提供掺质引进的自对准，以使得形成外质基极34的区段的基极层20的区段位于相邻发射极指26至29之间、及基极层20的周缘。可于这些位置接触外质基极34的此等区段。基极层20位处发射极指26至29下方的区段未接收一定浓度的掺质，此等区段界定本质基极36的区段。
外质基极34的此等区段、及本质基极36的此等区段于基极层20内以交替方式横向并列。装置区14的一部分11及/或集电极16与形成外质基极34的一区段的基极层20的各区段对准。装置区14的这些部分11及/或集电极16无介电材料，例如半导体材料中无嵌埋介电材料，此将会是沟槽隔离区的特性。装置区14的一部分13及/或集电极16与形成本质基极36的一区段的基极层20的各区段对准。装置区14的这些部分13及/或集电极16亦无介电材料，例如半导体材料中无嵌埋介电材料，此将会是沟槽隔离区的特性。部分11与部分13于基极层20内以交替方式横向并列。
装置结构40具有集电极16、本质基极36的区段的单晶半导体材料、及发射极指26至29垂直配置于其中的垂直架构。构成基极层22、及本质基极36的此等区段的半导体材料与构成发射极指26至29及集电极16的半导体材料有相反的导电性类型。若集电极16、本质基极36的此等区段、及发射极指26至29其中两者或全部三者由不同半导体材料所构成，则可将装置结构40特征化为异质接面双极晶体管。发射极基极介面界定于发射极指26至29的各者与本质基极36的相应区段间的介面处，以使得装置结构有效包括促成发射极基极接面的多个接面。基极集电极接面界定在介于集电极16与基极层20间的介面处，以使得装置结构40仅包括完全由单晶半导体材料所构成的单一基极集电极接面。此单一基极集电极接面与装置构造形成对比，此等装置构造包括具有由共集电极所连接的多个基极集电极接面的沟槽隔离区，而且其中外质基极与沟槽隔离区的介电材料具有介面。
接着是中段(MOL)处理及后段制程(BEOL)处理，其包括硅化、形成介电层、贯孔插塞、及通过局部互连结构与双极性接面晶体管耦合的互连结构用的配线、以及与衬底10上制造的其它电路***中包括的装置结构40与CMOS晶体管相似的附加装置结构用的其它类似接触部。至少一列基极接触部41位于各对发射极指26至29之间，并且位于各该胞元的周缘侧边。基极接触部41着落于外质基极34的区段上，其可在其顶端表面处硅化。形成接触发射极指26至29与集电极接触区17、18的附加接触部(图未示)。在一具体实施例中，发射极指26至29的一或多者可以是中段处理期间未接触的虚设发射极。
由于没有沟槽隔离区，装置结构40缺乏与各该发射极指26至29相关联的装置区，使得装置区的数目等于发射极指26至29的数目。反而，装置结构40包括与所有发射极指26至29相关联的单一装置区14。
可将装置结构40区分成本质装置区50，其与部分集电极16、基极层20的本质基极36、及发射极指26至29重合，此等发射极指参与本质装置区50外侧的接面及外质装置区60。外质装置区60其中一者位于各相邻对的本质装置区50之间，因此也介于最接近邻接体的各相邻对的发射极指26至29之间。装置区14的部分11及/或集电极16基本上与外质装置区60对准，而装置区14的部分13及/或集电极16基本上与本质装置区50对准。将外质装置区60中的沟槽隔离区消除，多半会将可归因于外质基极-隔离介电质-集电极的电容成份消除，此通过消除沟槽隔离的介电材料来达成，其按照习知会位在介于外质基极34与集电极16间的装置区14中。
外质装置区中外质基极的厚度增加可能造成集电极外周界处的外质基极掺质分布以更快速度减小。植入的掺质其浓度分布的尾部可与集电极以更大距离相隔，同时仍将充分掺质浓度引入基极层，以因应需要提升将外质基极特征化的导电性。这可减少周界集电极与本质基极间的电容，进行可改善高频效能及过渡时间。基极电阻也可随着外质装置区中基极层厚度增加而降低。
装置结构40因消除外质装置区中的沟槽隔离区而改善的效能可通过改善优值而得以证实，诸如增大峰值截止频率fT及峰值最大振荡频率fmax。外质装置区中消除沟槽隔离区亦可加宽截止频率fT及最大振荡频率fmax曲线，亦即，截止频率fT及最大振荡频率fmax可随着电流增加而更高。不用提高集电极掺杂也可改善截止频率fT及最大振荡频率fmax曲线。消除外质装置区中的沟槽隔离区可增大截止频率fT而不影响崩溃电压。
得以消除基于装置区内侧存在沟槽隔离区对发射极指间隔的任何限制，这可允许缩减装置结构的占位面积。消除沟槽隔离区可降低热量约束并提高出自装置结构的热量散逸，这是因为低热传导率的介电材料也跟着消除。改善热量散逸可降低因发射极指焦耳加热所致热失控问题的机率，并且可允许使用更小的镇流电阻器。由于没有与沟槽隔离区正常相关联的应力，消除沟槽隔离区可改善装置结构的几何扩缩。不用在程序流程里新增任何遮罩也可消除此等沟槽隔离区。
制造并测试装置结构，其中基线装置结构具有4个发射极指的SiGe异质接面双极晶体管，并且在设计方面旨在操作于作为标称优值的25GHZ峰值截止频率及100GHz最大频率。此装置构造类似于本文中所示及所述装置结构的构造，其中装置区的外周界内侧消除沟槽隔离区。为求比较，制造标称等同的装置结构，其在集电极接触区的装置区内部的半导体材料中、及相邻对的发射极指之间包括沟槽隔离区。此装置交流效能在提取方面，使用的是具有标准负载-反射-反射-匹配(LRRM)校准、及开路与短路去嵌埋的双埠S参数测量，用以移除与测量缆线、探针、配线及接垫相关联的寄生阻抗。
图2就根据本发明的一具体实施例缺乏沟槽隔离区的装置结构(曲线102)、及根据先前技术包括沟槽隔离区的装置结构(曲线112)，绘出截止频率以集电极电流为函数的曲线图。观测到曲线102呈现比曲线112中的峰值截止频率更大的峰值截止频率。另外，曲线102在峰值截止频率附近的宽度比曲线112在峰值截止频率附近的宽度更广(即更宽)。具体而言，就观测到的峰值截止频率而言，曲线103比曲线112高约10％，而且观测到的峰值集电极电流(与增加的幅度有关)增加22％。
图3就根据本发明的一具体实施例缺乏沟槽隔离区的装置结构(曲线103)、及根据先前技术包括沟槽隔离区的装置结构(曲线113)，绘出最大振荡频率以集电极电流为函数的曲线图。观测到曲线103呈现比曲线113中的峰值最大振荡频率更大的峰值最大振荡频率。另外，曲线103在峰值最大振荡频率附近的宽度比曲线113在峰值最大振荡频率附近的宽度更广(即更宽)。在没有沟槽隔离区的装置结构中，相较于曲线113，曲线103中的截止频率fT随着电流增大而可察觉地更高。具体而言，就观测到的峰值最大振荡频率而言，曲线103比曲线112高约10％，而且观测到的峰值集电极电流(与增加的幅度有关)增加22％。
就相邻发射极指之间外质装置区中缺乏沟槽隔离区的装置结构在图2及图3中呈现的效能度量改善状况可源自于外质基极电阻及外质基极集电极间电容的降低。相较于先前技术的装置结构，图2、图3所特征化的装置结构呈现外质基极电阻降低10％且外质基极集电极间电容降低有10％之多。具如此效能度量改善的装置结构可呈现更快的操作。
图4就根据本发明的一具体实施例缺乏沟槽隔离区的装置结构(曲线104)、及根据先前技术包括沟槽隔离区的装置结构(曲线114)，绘出基极集电极间电容以基极集电极接面偏压为函数的曲线图。曲线104的基极集电极间电容在基极集电极接面偏压所有值都小于曲线114的基极集电极间电容。此观测可归因于外质基极与集电极间消除了沟槽隔离的介电材料特性。
图5就根据本发明的一具体实施例缺乏沟槽隔离区的装置结构(曲线105a、105b)、及根据先前技术包括沟槽隔离区的装置结构(曲线115a、115b)，绘出两种不同基极发射极偏压下崩溃电压以基极集电极接面偏压为函数的曲线图。基极发射极偏压为0.76V的曲线105a、115a以标称有感差异在图中重叠。同样地，基极发射极偏压为0.66V的曲线105b、115b以标称有感差异在图中重叠。高度重叠表示沟槽隔离区的消除不影响崩溃电压。
图6以集电极电流为函数，就根据本发明的一具体实施例缺乏沟槽隔离区的装置结构(曲线106)、及根据先前技术包括沟槽隔离区的装置结构(曲线116)，绘出杂讯指数最小值(Nfmin)以集电极电流为函数的曲线图。基本上装置杂讯随着集电极电流升高而增加。曲线106中观测到的装置杂讯小于曲线116中的装置杂讯，原因据信是外质基极电阻减小。
本方法如以上所述，用于制造积体电路芯片。产生的积体电路芯片可由制造商以空白晶圆形式(例如：作为具有多个未封装芯片的单一晶圆)、当作裸晶粒、或以封装形式来配送。在后例中，芯片嵌装于单芯片封装(例如：塑胶载体，有导线黏贴至主机板或其它更高层次载体)中、或多芯片封装(例如：具有表面互连或埋置型互连任一者或两者的陶瓷载体)中。无论如何，芯片可与其它芯片、离散电路元件、及/或其它信号处理装置整合，作为中间产品或或最终产品的部分。
本文中对“垂直”、“水平”等用语的参照属于举例，并非限制，用来建立参考架构。“水平”一词于本文中使用时，定义为与半导体衬底的***面平行的平面，与其实际三维空间方位无关。“垂直”与“正交”等词指垂直于水平的方向，如刚才的定义。“横向”一词指水平平面内的维度。诸如“上面”及“下面”等词用于指出元件或结构彼此的相对位置，与相对高度截然不同。
一特征可连至或与另一元件进行“连接”或“耦合”，其可直接连接或耦合至其它元件，或取而代的，可存在一或多个中介元件。如无中介元件，一特征可“直接连接”或“直接耦合”至另一元件。如有至少一个中介元件，一特征可“间接连接”或“间接耦合”至另一元件。
本发明的各项具体实施例的描述已为了说明目的而介绍，但用意不在于穷举或受限于所揭示的具体实施例。许多修改及变例对于本领域技术人员将会显而易知，但不会脱离所述具体实施例的范畴及精神。本文中使用的术语是为了最佳阐释具体实施例的原理、对市场出现的技术所作的实务应用或技术改良、或让本领域技术人员能够理解本文中所揭示的具体实施例而选择。

Claims (16)

1.一种使用衬底形成的装置结构，该装置结构包含：
位在该衬底中的一或多个沟槽隔离区，该一或多个沟槽隔离区围绕装置区，该装置区具有一部分；
位在该装置区上的基极层，该基极层包含本质基极及在该装置区的该部分上的外质基极，并且该外质基极相较于该本质基极具有较高的导电性；
延展至在该装置区的该部分上的该外质基极的一区段的多个接触部；以及
位在该基极层上呈相隔关系的第一发射极指及第二发射极指，
其中，该本质基极具有该第一发射极指下方的第一区段及该第二发射极指下方的第二区段，该外质基极的该区段横向位于该本质基极的该第一区段与该本质基极的该第二区段之间的该基极层中，该装置区的该部分及该外质基极的该区段位于该第一发射极指及该第二发射极指之间，且该装置区的该部分无介电材料。
2.如权利要求1所述的装置结构，其中，该外质基极直接位于该装置区的该部分上。
3.如权利要求1所述的装置结构，其中，该装置区的该部分无包含该介电材料的沟槽隔离区。
4.如权利要求1所述的装置结构，其中，该基极层具有均匀厚度。
5.如权利要求1所述的装置结构，其中，该第一发射极指是中段处理期间未接触的虚设发射极。
6.如权利要求1所述的装置结构，其中，该装置区的该部分位在介于该第一发射极指与该第二发射极指间的外质装置区中。
7.如权利要求1所述的装置结构，其中，位在该装置区的该部分上的该基极层完全由单晶半导体材料所构成。
8.如权利要求1所述的装置结构，其中，位在该装置区的该部分上的该基极层无小面也无多结晶半导体材料。
9.一种制造装置结构的方法，该方法包含：
形成位在衬底中的一或多个沟槽隔离区以围绕装置区；
形成位在该装置区上的基极层；
形成位在该基极层上呈相隔关系的第一发射极指及第二发射极指，
用电活性掺质布植该基极层自该第一发射极指延展至该第二发射极指的区段以界定外质基极的一区段；以及
形成延展至在该装置区的一部分上的该外质基极的该区段的多个接触部；
其中，该基极层进一步包括本质基极以及相较于该本质基极具有较高的导电性的该外质基极，该本质基极具有该第一发射极指下方的第一区段及该第二发射极指下方的第二区段，该外质基极的该区段横向位于该本质基极的该第一区段与该本质基极的该第二区段之间的该基极层中，该装置区的该部分及该外质基极的该区段位于该第一发射极指及该第二发射极指之间，且该装置区的该部分无介电材料。
10.如权利要求9所述的方法，其中，该外质基极直接形成在该装置区的该部分上。
11.如权利要求9所述的方法，其中，该装置区的该部分无包含该介电材料的沟槽隔离区。
12.如权利要求9所述的方法，其中，该基极层具有均匀厚度。
13.如权利要求9所述的方法，其中，该第一发射极指是中段处理期间未接触的虚设发射极。
14.如权利要求9所述的方法，其中，该装置区的该部分介于该第一发射极指与该第二发射极指间的外质装置区。
15.如权利要求9所述的方法，其中，位在该装置区的该部分上的该基极层完全由单晶半导体材料所构成。
16.如权利要求9所述的方法，其中，位在该装置区的该部分上的该基极层无小面也无多结晶半导体材料。
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