CN106990936B - Plus-minus method universal circuit with symbol control end - Google Patents
Plus-minus method universal circuit with symbol control end Download PDFInfo
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- CN106990936B CN106990936B CN201710171105.7A CN201710171105A CN106990936B CN 106990936 B CN106990936 B CN 106990936B CN 201710171105 A CN201710171105 A CN 201710171105A CN 106990936 B CN106990936 B CN 106990936B
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Abstract
An addition and subtraction universal circuit with a sign control end comprises m cascaded full subtracter units FM, wherein input signals of each full subtracter unit FM comprise a signal A serving as a subtrahend or an addend and a signal B serving as a subtrahend or an addend, and the signal B and a sign bit control signal Cr are subjected to XOR operation and are connected to the subtraction or addend input end of the full subtracter unit FM; the output signal of each full-subtractor unit FM comprises an operation result signal S, a sign bit control signal Cr is connected to the low borrowing input end of the first-stage full-subtractor unit FM, and the borrowing output signal of the highest stage is a signal Cout; when the sign bit control signal Cr takes 0, the whole circuit performs subtraction operation; when the sign bit control signal Cr takes 1, the whole circuit carries out addition operation. And m is a positive integer. The invention can simultaneously control and realize the addition and subtraction operation of m bits, thereby reducing the number of logic gates and reducing the circuit area.
Description
Technical Field
The invention belongs to the field of circuit design, and particularly relates to an addition and subtraction universal circuit with a symbolic control end.
Background
At present, the adder and the subtracter both have own specific arithmetic circuits, and the adder circuit and the subtracter circuit usually exist at the same time in actual circuit design. Therefore, it is necessary to design a general add-subtract circuit, which can complete two kinds of operations with one circuit structure, thereby reducing the number of logic gates required for a certain operation and reducing the circuit area.
Disclosure of Invention
The present invention is directed to solve the above problems in the prior art, and an object of the present invention is to provide a general addition/subtraction circuit with a sign control terminal, which simplifies a circuit structure by adding a sign control terminal and an xor logic to implement addition/subtraction in the same circuit.
In order to achieve the purpose, the invention adopts the technical scheme that: the device comprises m cascaded full-subtracter units FM, wherein input signals of each full-subtracter unit FM comprise a signal A which is a subtrahend or an addend and a signal B which is a subtrahend or an addend, and the signal B and a sign bit control signal Cr are subjected to XOR operation and are connected to the input end of the full-subtracter unit FM; the output signal of each full-subtractor unit FM comprises an operation result signal S, the sign bit control signal Cr is connected to the low borrowing input end of the first-stage full-subtractor unit FM, and the highest borrowing output signal is a signal Cout; when the sign bit control signal Cr takes 0, the whole circuit performs subtraction operation; when the sign bit control signal Cr takes 1, the whole circuit carries out addition operation. And m is a positive integer.
In m cascaded full reducer units FM, a low-order borrow signal Cin of a first-order full reducer unit FM is connected with a sign bit control signal Cr to be used as the lowest-order borrow input, the first-order full reducer unit FM outputs a first-order operation result signal S0 and a first-order borrow output signal Cout0 to the high-order, the first-order borrow output signal Cout0 to the high-order is connected to the low-order borrow input end of a second-order full reducer unit FM, and by analogy, the second-order to m-1 th full reducer units FM are cascaded, and the borrow output of the lower-order full reducer unit FM is directly connected to the borrow input end of the high-order unit FM between all levels.
A signal B and a low-order borrow signal Cin of the full-subtractor unit FM are respectively connected with the input end of a first NOR gate, the output signal and the signal B of the first NOR gate are connected with the input end of a second NOR gate, and the output signal and the low-order borrow signal Cin of the first NOR gate are connected with the input end of a third NOR gate; the output ends of the second NOR gate and the third NOR gate are connected with two input ends of the fourth NOR gate; the output signal of the fourth NOR gate and the signal A are connected with two input ends of the fifth NOR gate; the output signal of the fifth NOR gate and the output signal of the fourth NOR gate are connected to two input ends of the seventh NOR gate, and the output signal of the fifth NOR gate and the signal A are connected to two input ends of the sixth NOR gate; the output signal of the sixth nor gate and the output signal of the seventh nor gate are connected to two input ends of the eighth nor gate, and the output signal of the eighth nor gate is an operation result signal S; the output signal of the seventh nor gate and the output signal of the first nor gate are connected to the input of a ninth nor gate, the output of which is the signal Cout.
The signal A and the signal B are respectively provided with m bits, and the sign bit control signal Cr is provided with 1 bit and is respectively connected to different full-subtracting units FM.
When the sign bit control signal Cr takes 0, the whole circuit performs m-bit subtraction operation to output m +1 bits, the operation results Sm-1 to S0 represent differences, and the borrow output signal Cout of the circuit represents the sign bit of the difference; when the sign bit control signal Cr takes 1, the whole circuit carries out m-bit addition operation to output m +1 bits in total, the borrow output signal Cout of the circuit represents the highest bit of the sum, and the operation results Sm-1 to S0 represent other bits of the sum.
The XOR operation enables the signal B and the sign bit control signal Cr to carry out NOR operation through the first-stage NOR gate, the output signal of the first NOR gate is respectively subjected to NOR operation with the signal B and the sign bit control signal Cr through the second-stage NOR gate, and the obtained two NOR operation results are output after the NOR operation is carried out through the OR gate.
Compared with the prior art, the invention has the following beneficial effects: based on the full subtracter unit, the m-bit full subtracter unit is cascaded to form an m-bit subtracter, and the addition and subtraction operation of m bits can be simultaneously controlled and realized by adding a sign bit control signal and an exclusive OR operation logic. The invention can be simultaneously suitable for addition and subtraction, thereby reducing the number of logic gates and reducing the circuit area.
Drawings
The exclusive or circuit represented by the nor gate of fig. 1;
FIG. 2 is a schematic diagram of a circuit configuration of a full subtractor unit;
FIG. 3 is a schematic diagram of the overall structure of the circuit of the present invention;
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
Referring to fig. 1-3, the boolean expression for the full subtractor unit of the present invention is as follows:
the exclusive or operation in the boolean expression can be implemented with two levels of three nor gates and one or gate.
The one-bit full-subtractor unit serving as a cascade basic unit of the subtractor is composed of six stages of NOR gates, the six stages of NOR gates are symmetrical in structure and are sequentially connected in series from input to output, the input ends of a first NOR gate, a second NOR gate, a third NOR gate, a fifth NOR gate and a sixth NOR gate in the six stages of NOR gates are connected with an input signal, and the output ends of an eighth NOR gate and a ninth NOR gate are connected with an output signal. The input signals include a signal a as a subtrahend, a signal B as a subtrahend, and a low borrow signal Cin, and the output signals include an operation result signal S and a signal Cout borrowed to a high. The signal a as a subtrahend is connected to one input of the fifth and sixth nor gates, and the signal B as a subtrahend and the low borrow signal Cin are connected to the inputs of the first and second nor gates, respectively. The output of the first nor gate is connected to the input of the second nor gate with signal B, and the output of the first nor gate is connected to the input of the third nor gate with the low borrow signal Cin. The output ends of the second NOR gate and the third NOR gate are connected with two input ends of a fourth NOR gate, and the output end and the signal A of the fourth NOR gate are connected with two input ends of a fifth NOR gate. The output of the fifth nor gate and the output of the fourth nor gate are connected to two inputs of the seventh nor gate, and the output of the fifth nor gate and the signal a are connected to two inputs of the sixth nor gate. The output of the sixth nor gate and the output of the seventh nor gate are connected to both inputs of the eighth nor gate, and the output of the eighth nor gate is the operation result signal S. The output of the seventh nor gate and the output of the first nor gate are connected to the input of a ninth nor gate, the output of which is Cout.
Referring to fig. 3, the full-subtracter units FM of the present invention are cascaded into an m-bit addition-subtraction circuit. The m stages of circuit structures are the same, and the first stage of circuit structure is used for illustrating the signal connection relationship of each stage. m is input signals A and B of the addition and subtraction circuit, and a sign bit control signal Cr. A and B are both m bits, and Cr is 1 bit. The input a is taken as a decremented or an incremented, and the least significant bit a0 of a is connected to the decremented input of the one-bit full-subtractor unit FM of the first stage. The input B is used as a decrement or an addition, and the lowest bit B0 of B is connected into an exclusive-OR circuit. Referring to fig. 1, the inputs of the xor circuit are B0 and a signal Cr, and are connected to two inputs of a first nor gate in the xor circuit, the output sum B0 of the first nor gate is connected to an input of a second nor gate, and the output sum Cr of the first nor gate is connected to an input of a third nor gate. The output of the second nor gate and the output of the third nor gate are connected to the input of a fourth or gate, the output of which is connected to the decrement input of a one-bit full subtractor unit FM.
The output of the first stage of the full subtractor FM is connected to the output signal S0, which connects the high borrow output signal to the low borrow input of the next stage of the full subtractor. The second to mth stages are connected in the same manner as the first stage, and the sign control signal Cr and the signals B1, B2.. Bm-1 are connected to the input terminal of the first nor gate of the xor circuit in each stage. The sign bit control signal Cr is connected to the low borrow input terminal of the first stage full subtractor circuit, and the borrow output of the highest stage is Cout.
When the sign bit control signal Cr is 0, the whole circuit performs m-bit subtraction operation and outputs m +1 bits in total. Sm-1 to S0 represent the difference and the borrow output Cout of the circuit represents the sign bit of the difference.
When the sign bit control signal Cr is 1, the whole circuit carries out m-bit addition operation and outputs m +1 bits in total. Cout represents the most significant bit of the sum, and Sm-1 through S0 represent the other bits of the sum.
The circuit in fig. 2 is represented by an abstract unit FM, and the m-bit addition and subtraction circuit structure of the present invention is shown in fig. 3.
The borrow input end of the first-stage full subtracter unit is connected with a sign bit control signal Cr and used as the borrow input of the lowest bit, and the output end of the first-stage full subtracter unit is S0 and outputs Cout0 to the high bit. The most significant borrow output Cout0 is directly connected to the low borrow input of the second stage full subtractor unit. According to the connection scheme, the second-level to the (m-1) -th-level full-reduction unit is cascaded, and the borrow output of the lower-level full-reduction unit is directly connected to the borrow input end of the higher-level unit between each level. And one end of the input end of the last stage, namely the m-1 th stage full subtractor unit, is connected with the highest bit Am-1 of the input signal A, the other end of the input end of the last stage, namely the m-1 th stage full subtractor unit, is connected with an exclusive or result of the sign bit control signal Cr and the highest bit Bm-1 of the input signal B, the output end of the last stage is Sm-1 and outputs Cout to a high borrow, and the borrow output Cout of the last stage is reserved as the borrow output of the whole subtraction circuit.
The m-bit addition and subtraction circuit of the invention has the following working principle:
when the sign bit control signal Cr takes 0, after each bit of the input signal B is subjected to exclusive OR with the sign bit control signal Cr, the value sent to the input end of the full subtracter unit FM is still the input signal B, the whole circuit performs subtraction, the difference value of the subtracted number A and the subtracted number B is calculated, and the m-bit difference S and the borrow output Cout are output, wherein m +1 bits are total. When the circuit performs subtraction, Cout is reserved as the most significant bit and is used for representing the sign bit of the result S. The boolean expression is:
S＝A-B
when the sign bit control signal Cr takes 1, after each bit of the input signal B is XOR-ed with the sign bit control signal Cr, the value B is fed into the input end of the full-subtracter unit FM and is inverted, the borrow signal Cin of the first-stage full-subtracter unit FM is input into the position 1, the whole circuit carries out addition operation, the sum of the added number A and the added number B is calculated, m-bit sum S and carry output Cout are output, m +1 bits are total, and when the addition operation is carried out, Cout is taken as the highest bit of the sum, and m +1 bits are total. The boolean expression is:
Claims (6)
1. an addition and subtraction universal circuit with a symbol control end is characterized in that: the device comprises m cascaded full-subtracter units FM, wherein input signals of each full-subtracter unit FM comprise a signal A which is a subtrahend or an addend and a signal B which is a subtrahend or an addend, and the signal B and a sign bit control signal Cr are subjected to XOR operation and are connected to the input end of the full-subtracter unit FM; the output signal of each full-subtractor unit FM comprises an operation result signal S, the sign bit control signal Cr is connected to the low borrowing input end of the first-stage full-subtractor unit FM, and the highest borrowing output signal is a signal Cout; when the sign bit control signal Cr takes 0, the whole circuit performs subtraction operation; when the sign bit control signal Cr takes 1, the whole circuit carries out addition operation; and m is a positive integer.
2. The sign-controlled add-subtract general circuit of claim 1, wherein: in m cascaded full reducer units FM, a low-order borrow signal Cin of a first-order full reducer unit FM is connected with a sign bit control signal Cr to be used as the lowest-order borrow input, the first-order full reducer unit FM outputs a first-order operation result signal S0 and a first-order borrow output signal Cout0 to the high-order, the first-order borrow output signal Cout0 to the high-order is connected to the low-order borrow input end of a second-order full reducer unit FM, and by analogy, the second-order to m-1 th full reducer units FM are cascaded, and the borrow output of the lower-order full reducer unit FM is directly connected to the borrow input end of the high-order unit FM between all levels.
3. The sign-controlled add-subtract general circuit of claim 1, wherein: a signal B and a low-order borrow signal Cin of the full-subtractor unit FM are respectively connected with the input end of a first NOR gate, the output signal and the signal B of the first NOR gate are connected with the input end of a second NOR gate, and the output signal and the low-order borrow signal Cin of the first NOR gate are connected with the input end of a third NOR gate; the output ends of the second NOR gate and the third NOR gate are connected with two input ends of the fourth NOR gate; the output signal of the fourth NOR gate and the signal A are connected with two input ends of the fifth NOR gate; the output signal of the fifth NOR gate and the output signal of the fourth NOR gate are connected to two input ends of the seventh NOR gate, and the output signal of the fifth NOR gate and the signal A are connected to two input ends of the sixth NOR gate; the output signal of the sixth nor gate and the output signal of the seventh nor gate are connected to two input ends of the eighth nor gate, and the output signal of the eighth nor gate is an operation result signal S; the output signal of the seventh nor gate and the output signal of the first nor gate are connected to the input of a ninth nor gate, the output of which is the signal Cout.
4. The sign-controlled add-subtract general circuit of claim 1, wherein: the signal A and the signal B are respectively provided with m bits, and the sign bit control signal Cr is provided with 1 bit and is respectively connected to different full-subtracting units FM.
5. The sign-controlled add-subtract general circuit of claim 1, wherein: when the sign bit control signal Cr takes 0, the whole circuit performs m-bit subtraction operation to output m +1 bits, the operation results Sm-1 to S0 represent differences, and the borrow output signal Cout of the circuit represents the sign bit of the difference; when the sign bit control signal Cr takes 1, the whole circuit carries out m-bit addition operation to output m +1 bits in total, the borrow output signal Cout of the circuit represents the highest bit of the sum, and the operation results Sm-1 to S0 represent other bits of the sum.
6. The sign-controlled add-subtract general circuit of claim 1, wherein: the XOR operation enables the signal B and the sign bit control signal Cr to carry out NOR operation through the first-stage NOR gate, the output signal of the first NOR gate is respectively subjected to NOR operation with the signal B and the sign bit control signal Cr through the second-stage NOR gate, and the obtained two NOR operation results are output after the NOR operation is carried out through the OR gate.
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| DE3844385A1 (en) * | 1988-12-30 | 1990-07-05 | Paul Merkle | Dual full adder-subtractor |
| CN103699353B (en) * | 2013-12-05 | 2016-06-08 | 西安交通大学 | An a kind of full subtracter circuit |
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