CN106961563B - Low-noise wide-dynamic-range image sensor related multi-sampling circuit - Google Patents
Low-noise wide-dynamic-range image sensor related multi-sampling circuit Download PDFInfo
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Abstract
The invention relates to a low-noise wide-dynamic-range image sensor correlation multi-sampling circuit, wherein an integrator integrates pixel signals output by a pixel output buffer; when the integration result is smaller than the set voltage threshold value, the integration control unit controls the integrator to perform integration of the next cycle, otherwise, the integration control unit controls the read control switch to be closed so that the final integration result is output to the analog-to-digital conversion unit, and the integration times are output to the data processing unit; the analog-to-digital conversion unit converts the final integral result into quantization result data and transmits the quantization result data to the data processing unit; and the data processing unit divides the quantized result data by the integration times to obtain the final sampling result data. The invention can carry out integration for different times aiming at different pixel outputs, achieves the purposes of integrating small signals for multiple times and integrating large signals appropriately, and can simultaneously realize low noise and wide dynamic range of the image sensor.
Description
Technical Field
The invention belongs to the technical field of semiconductor image sensing, and relates to a circuit for realizing a low-noise wide-dynamic-range image sensor by adopting a correlated multi-sampling technology.
Background
The noise of the sensor can be reduced by the related multiple sampling technology. A typical correlated multiple sampling circuit is shown in fig. 1a, and comprises an integrator and a readout control switch S5, wherein the integrator is composed of an amplifier AMP1, a sampling capacitor C1, a feedback capacitor C2, and four switches S0, S1, S2, S3, and S4; the circuit first resets the C2 and circuit by closing switch S0. Then switch S0 is opened and switches S1 and S3 are closed, as shown in fig. 1 b; after the signal at C1 stabilizes, switches S1 and S3 are opened to sample the pixel signal onto capacitor C1. The switches S2 and S4 are then closed, as shown in fig. 1C, transferring the signal charge to the capacitor C2. By repeating the loop of the phases described in fig. 1b and 1c, the noise on the pixel output buffer can be integrated, and since the uncorrelated noise is averaged after the integration, the equivalent input noise on Vpix (pixel signal) is reduced. The disadvantage is that the effective swing of Vpix decreases with increasing integration times, resulting in a decrease of the overall dynamic range of the sensor.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a low-noise wide-dynamic-range image sensor related multi-sampling circuit, which can keep the output of a pixel unchanged and reduce the equivalent input noise of the pixel, thereby realizing the low noise and wide dynamic range of the image sensor at the same time.
In order to solve the technical problem, the low-noise wide-dynamic-range image sensor correlation multi-sampling circuit comprises an integrator, an integration control unit, a reading control switch, an analog-to-digital conversion unit and a data processing unit; the integrator receives the pixel signal output by the pixel output buffer and integrates the pixel signal; the integration control unit acquires an integration result output by each cycle of integrator, outputs a signal to control the integrator to perform integration of the next cycle when the integration result is smaller than a set voltage threshold, outputs a signal to control the read control switch to be closed when the integration result is larger than or equal to the set voltage threshold so that a final integration result is output to the analog-digital conversion unit, and simultaneously outputs the integration times to the data processing unit; the analog-to-digital conversion unit converts the final integral result into quantization result data and transmits the quantization result data to the data processing unit; and the data processing unit divides the quantized result data by the integration times to obtain the final sampling result data.
The integration control unit comprises a logic circuit and an analog comparator; the analog comparator compares the integration result output by each cycle integrator with a set voltage threshold value and outputs the comparison result to the logic circuit, when the integration result is smaller than the set voltage threshold value, the logic circuit outputs a signal to control the integrator to perform integration of the next cycle, and when the integration result is larger than the set voltage threshold value, the logic circuit outputs a signal to control the read control switch to be closed so that the final integration result is output to the analog-to-digital conversion unit, and meanwhile, the integration times are output to the analog-to-digital conversion unit.
The integral control unit comprises a logic circuit, an analog-to-digital conversion circuit and a digital comparator; the analog-to-digital conversion circuit converts an integration result output by the integrator into a digital signal and outputs the digital signal to the digital comparator; the digital comparator compares the digital signal with a set voltage threshold value and outputs the comparison result to the logic circuit, when the digital signal is smaller than the set voltage threshold value, the logic circuit outputs a signal to control the integrator to perform integration of the next cycle, when the digital signal is larger than the set voltage threshold value, the logic circuit outputs a signal to control the read control switch to be closed so that the final integration result is output to the analog-to-digital conversion unit, and meanwhile, the integration times are output to the analog-to-digital conversion unit.
The invention is invented aiming at the special mechanism of the noise of the image sensor. The total noise of the image sensor has the following characteristics: when the number of photons input to the pixel is small, the total equivalent input noise of the sensor is determined by the readout circuit noise of the pixel, so that the circuit noise needs to be reduced by a noise reduction technology of multiple correlated sampling; when the number of photons input to the pixel is large, the total equivalent input noise of the sensor is determined by the number of photons (shot noise of photons), and the noise of the circuit can be ignored, so that the noise of the readout circuit is reduced without a related multi-sampling circuit. The present invention determines whether to continue executing the integration cycle by monitoring the results of the integrator. Therefore, integration of different times can be carried out aiming at different pixel outputs, and the purposes of integrating small signals for multiple times and integrating large signals appropriately are achieved. The invention can keep the output of the pixel unchanged and reduce the equivalent input noise of the pixel, thereby simultaneously realizing low noise and wide dynamic range of the image sensor.
Drawings
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
FIG. 1a is a schematic diagram of a related art multiple sampling circuit; fig. 1b and fig. 1c are schematic diagrams of two working phases of a related multiple sampling circuit in the prior art.
Fig. 2 is a schematic diagram of the structure of the low-noise wide-dynamic-range image sensor correlated multi-sampling circuit of the present invention.
Fig. 3 is a schematic structural view of embodiment 1 of the present invention.
Fig. 4 is a schematic structural diagram of embodiment 2 of the present invention.
Detailed Description
Example 1
As shown in fig. 2 and 3, the low-noise wide-dynamic-range image sensor correlation multi-sampling circuit of the present invention includes an integrator, an integration control unit, a readout control switch, an analog-to-digital conversion unit, and a data processing unit; the integral control unit comprises a logic circuit and an analog comparator.
The integrator receives and integrates the pixel signal Vpix output by the pixel output buffer; the analog comparator integrates the integration result V output by the integrator in each cycleiAnd a set voltage threshold value V0Making a comparison when ViLess than V0When the voltage is lower than the reference voltage, the logic circuit outputs a signal to control the integrator to perform integration in the next cycle when the voltage is lower than the reference voltageiGreater than or equal to V0When the current time is longer than the preset time, the logic circuit outputs a signal to control the read control switch S5 to be closed so that the final integration result is transmitted to the analog-digital conversion unit, i at the moment is equal to the integration frequency K, and the integration frequency K is transmitted to the data processing unit; the analog-to-digital conversion unit converts the final integral result into quantization result data A and then transmits the quantization result data A to the data processing unit; the data processing unit divides the quantization result data A by the number of integration times to obtain final sampling result data Y.
Example 2
As shown in fig. 2 and 4, the low-noise wide-dynamic-range image sensor correlation multi-sampling circuit of the present invention includes an integrator, an integration control unit, a readout control switch, an analog-to-digital conversion unit, and a data processing unit; the integration control unit comprises a logic circuit, an analog-to-digital conversion circuit and a digital comparator.
The integrator receives and integrates the pixel signal Vpix output by the pixel output buffer; the analog-to-digital conversion circuit converts the integration result output by the integrator into a digital signal Vi' then output to the digital comparator; a digital comparator compares Vi' with a set voltage threshold V0Making a comparison when Vi' less than or equal to V0Time, logic circuitThe output signal controls the integrator to integrate in the next cycle when ViGreater than or equal to V0When the current time is longer than the preset time, the logic circuit outputs a signal to control the read control switch S5 to be closed so that the final integration result is transmitted to the analog-digital conversion unit, i at the moment is equal to the integration frequency K, and the integration frequency K is transmitted to the data processing unit; the analog-to-digital conversion unit converts the final integral result into quantization result data A and then transmits the quantization result data A to the data processing unit; the data processing unit divides the quantization result data A by the number of integration times to obtain final sampling result data Y.
Setting the bit width of K as N-bit, and the bit width of the quantization result data A of the analog-to-digital conversion unit as M-bit ADC, after data processing, the quantization precision of the final result is 1L SB (the minimum quantization step of the M-bit ADC) divided by K (K is maximally equal to 2)N) Therefore, the minimum quantization step is 1L SB/(2)N) Therefore, the total bit width is (M + N) bit.
Claims (3)
1. A low-noise wide-dynamic-range image sensor correlation multi-sampling circuit comprises an integrator and a reading control switch; the pixel integration circuit is characterized by also comprising an integration control unit, an analog-to-digital conversion unit and a data processing unit, wherein the integrator receives and integrates pixel signals output by the pixel output buffer; the integration control unit acquires an integration result output by each cycle of integrator, outputs a signal to control the integrator to perform integration of the next cycle when the integration result is smaller than a set voltage threshold, outputs a signal to control the read control switch to be closed when the integration result is larger than or equal to the set voltage threshold so that a final integration result is output to the analog-digital conversion unit, and simultaneously outputs the integration times to the data processing unit; the analog-to-digital conversion unit converts the final integral result into quantization result data and transmits the quantization result data to the data processing unit; and the data processing unit divides the quantized result data by the integration times to obtain the final sampling result data.
2. The low noise wide dynamic range image sensor correlated multiple sampling circuit of claim 1, wherein said integral control unit comprises a logic circuit and an analog comparator; the analog comparator compares the integration result output by each cycle integrator with a set voltage threshold value and outputs the comparison result to the logic circuit, when the integration result is smaller than the set voltage threshold value, the logic circuit outputs a signal to control the integrator to perform integration of the next cycle, and when the integration result is larger than the set voltage threshold value, the logic circuit outputs a signal to control the read control switch to be closed so that the final integration result is output to the analog-to-digital conversion unit, and meanwhile, the integration times are output to the analog-to-digital conversion unit.
3. The low noise wide dynamic range image sensor correlated multiple sampling circuit of claim 1, wherein said integral control unit comprises a logic circuit, an analog-to-digital conversion circuit, a digital comparator; the analog-to-digital conversion circuit converts an integration result output by the integrator into a digital signal and outputs the digital signal to the digital comparator; the digital comparator compares the digital signal with a set voltage threshold value and outputs the comparison result to the logic circuit, when the digital signal is smaller than the set voltage threshold value, the logic circuit outputs a signal to control the integrator to perform integration of the next cycle, when the digital signal is larger than the set voltage threshold value, the logic circuit outputs a signal to control the read control switch to be closed so that the final integration result is output to the analog-to-digital conversion unit, and meanwhile, the integration times are output to the analog-to-digital conversion unit.
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| WO2019075749A1 (en) * | 2017-10-20 | 2019-04-25 | 深圳市汇顶科技股份有限公司 | Analog read circuit and image sensing module |
| CN209285376U (en) * | 2018-09-05 | 2019-08-23 | 江苏美的清洁电器股份有限公司 | A kind of signal processing circuit and device, dust catcher |
| CN111093043B (en) * | 2018-10-24 | 2021-10-22 | 宁波飞芯电子科技有限公司 | Radiation receiving system and method and sensing array |
| CN112449125B (en) * | 2019-08-29 | 2022-06-17 | 天津大学青岛海洋技术研究院 | Image sensor reading circuit based on self-adaptive threshold adjustment |
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Inventor after: Liu Yang Inventor after: Guo Yangyu Inventor after: Wang Xinyang Inventor after: Ma Cheng Inventor after: Li Yang Inventor before: Liu Yang Inventor before: Guo Yangyu Inventor before: Wang Xinyang Inventor before: Ma Cheng Inventor before: Li Yang |
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Address after: Office Buildings 1 and 5, Phase I, Optoelectronic Information Industry Park, No. 7691 Ziyou Road, Changchun Economic and Technological Development Zone, Jilin Province, 130000 Patentee after: Changchun Changguang Chenxin Microelectronics Co.,Ltd. Address before: No. 588, Yingkou Road, Jingkai District, Changchun City, Jilin Province, 130033 Patentee before: Changchun Changguangchenxin Optoelectronics Technology Co.,Ltd. |
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