CN106101585A - A kind of low noise CCD camera circuitry - Google Patents

A kind of low noise CCD camera circuitry Download PDF

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Publication number
CN106101585A
CN106101585A CN201610601095.1A CN201610601095A CN106101585A CN 106101585 A CN106101585 A CN 106101585A CN 201610601095 A CN201610601095 A CN 201610601095A CN 106101585 A CN106101585 A CN 106101585A
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ccd
resistance
ccd camera
amplifier
noise
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CN106101585B (en
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陈智
文延
姚大雷
王宏
单金玲
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XiAn Institute of Optics and Precision Mechanics of CAS
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XiAn Institute of Optics and Precision Mechanics of CAS
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

The present invention is a kind of low noise CCD camera circuitry, including the adjustable analog front circuit of bandwidth and CCD camera digital sampling circuitry based on CDS technology；Analog front circuit includes capacitance C, prime in-phase amplification circuit QF and bandwidth adjustable RC low-pass filtering switch KG；Preamplifying circuit QF includes amplifier U；The resistance R being connected with the in-phase input end of amplifier U；The resistance R1 being connected with amplifier U reverse input end and resistance R2；The Schottky diode D in parallel with resistance R2 and amplifier U reverse input end；Resistance RS1, resistance RS2 are connected with the outfan of amplifier U；Switch Ks and electric capacity Cs forms bandwidth rearrangeable switch KG；The invention provides a kind of volume low in energy consumption, capacity of resisting disturbance is strong, safety and reliability is high, flexible design extended capability is strong low noise CCD camera circuitry little, lightweight, can effectively reduce noise, improve the dynamic range of CCD camera.

Description

A kind of low noise CCD camera circuitry
Technical field
The invention belongs to photoelectric field, relate to a kind of low noise CCD camera circuitry realization method and system, particularly relate to one Plant the astronomical observation and the CCD remote sensing camera circuit of deep-space detection field required for low noise.
Background technology
There is due to CCD the characteristics such as high-quantum efficiency, the good linearity and low noise, be widely used to Aero-Space In field, especially in low-light (level), the field such as low light level target astronomical observation.But noise has had become as low light level observation mission Major obstacle, along with CCD device is to miniaturization, integrated development, the increase of CCD photosensitive unit quantity certainly will light be reduced The area of quick unit, thus reduce the output saturation signal of CCD.In order to expand the dynamic range of CCD, it is necessary for reducing CCD phase The noise of machine, otherwise cannot be applied to high accuracy, the astronomical observation task of low light level target.
The noise of CCD camera system sum up mainly include photon noise, reset noise, dark current noise, thermal noise, Off chip amplifier noise, 1/f noise and quantizing noise.Wherein photon noise is CCD intrinsic noise, and it characterizes CCD camera system The limit of highest signal to noise ratio.CCD thermal noise and dark current can effectively reduce its impact by freezing CCD.Remaining Reset noise, 1/f noise and AD quantizing noise all can be affected by Low noise circuit design to be preferably minimized.
Summary of the invention
In order to solve above-mentioned technical problem present in background technology, the invention provides a kind of volume merit little, lightweight Consume low noise CCD camera circuitry low, that capacity of resisting disturbance is strong, safety and reliability is high, flexible design extended capability is strong, permissible Effectively reduce noise, improve the dynamic range of CCD camera.
The technical solution of the present invention is: a kind of low noise CCD camera circuitry, it is characterised in that: described CCD camera electricity Road includes the adjustable analog front circuit of bandwidth and CCD camera digital sampling circuitry based on CDS technology；
Described analog front circuit includes capacitance C, prime in-phase amplification circuit QF and bandwidth adjustable RC low pass filtered Ripple switch KG；Preamplifying circuit QF includes amplifier U；The resistance R being connected with the in-phase input end of amplifier U；The most defeated with amplifier U Enter resistance R1 and resistance R2 that end connects；The Schottky diode D in parallel with resistance R2 and amplifier U reverse input end；Resistance RS1, resistance RS2 are connected with the outfan of amplifier U；Switch Ks and electric capacity Cs forms bandwidth rearrangeable switch KG；Ks analog switch Open and switch over according to the phase relation of current CCD video signal output voltage waveforms with closing, thus change AFE (analog front end) Bandwidth；
CCD camera digital sampling circuitry includes high-speed ADC and FPGA；High-speed ADC is to ccd signal datum and pixel electricity Putting down and carry out sampling and analog digital conversion, FPGA realizes the control to ADC high-speed sampling, digital low-pass filtering and numeral CDS.
Above-mentioned high-speed ADC is correlated-double-sampling, if the pixel clock frequency of CCD is fCcD, then sample frequency fSAMPLE= 2fCCD, it is i.e. 2 times of pixel clock frequency.
Also include wave digital lowpass filter LP, use multiple sampled point to be averaging, realize in FPGA, permit in sequential relationship Under conditions of Xuing, gathering 2n sampled point, be averaged, high-frequency noise and the reduction quantization of removing AFE (analog front end) introducing are made an uproar Sound.
Also including numeral CDS, be the difference of datum and pixel level sampled point, the reset of suppression CCD video signal is made an uproar Sound and low-frequency noise, it is achieved form is digital subtractor, digital subtractor is to ccd signal datum conversion value SrefAnd picture Element level conversion value SpixCarry out subtraction, obtain the digital picture needed.
The invention have the advantage that volume little, lightweight low in energy consumption, capacity of resisting disturbance is strong, safety and reliability is high, design Flexible expansion ability is strong；Can effectively reduce noise, improve the dynamic range of CCD camera.FPGA is used to realize high-speed sampling, number Word low-pass filtering and numeral CDS, be possible not only to remove further high-frequency noise that AFE (analog front end) introduces, reduce quantizing noise and Can effectively remove the correlated noise between pixel.Use FPGA to realize simultaneously, there is structure simpler, it is achieved the most excellent Point.
Accompanying drawing explanation
Fig. 1 is bandwidth of the present invention adjustable analog front circuit schematic diagram；
Fig. 2 is CCD video signal output voltage waveform of the present invention；
Fig. 3 is present invention low noise digital based on CDS technology sample circuit schematic diagram；
Fig. 4 is digital sample timing diagram of the present invention；
Detailed description of the invention
The invention provides a kind of low noise CCD camera circuitry implementation method and system thereof, before the adjustable simulation of bandwidth Terminal circuit and CCD camera digital sampling circuitry two parts based on CDS technology composition.
One, analog front circuit；As shown in Figure 1.It is by capacitance, preamplifying circuit QF and the adjustable RC of bandwidth Low-pass filtering switch KG tri-part composition.Owing to the output signal of CCD is floating (usual tens volts) negative in DC level The analogue signal of polarity spatial spreading.If this signal being directly used for rear class amplify and analog digital conversion, the most easily make amplifier Saturated with ADC, and it is unfavorable for the extraction of useful signal, it is therefore necessary to carry out this signal processing every primes such as straight, amplifications.This Patent proposes a kind of adjustable analog front circuit of bandwidth, and wherein C is that capacitance, U, R, R1, R2 and D constitute preposition amplification Circuit QF, its objective is to be adjusted in the input range of high-speed AD converter signal level；D: Schottky diode, is used for Filter a part of reset pulse spike.RS1, RS2, Ks and Cs form bandwidth rearrangeable switch KG.The opening and closing of Ks analog switch Close and switch over according to the phase relation of current CCD video signal output voltage waveforms, thus change the bandwidth of AFE (analog front end).RC The corner frequency of low pass filter is f0=1/2 π RC, and the position of corner frequency becomes with RC.If capacitance is constant, low pass Resistance is decreased to RS2 from RS1, and corner frequency translates to front end.
By ccd output signal feature: reset pulse A is mingled with some high fdrequency components (reset spike) as shown in Figure 2, and joins Examine level B relative with pixel level C stable.In order to reduce the noise of AFE (analog front end) further, according to the phase place of ccd output signal Relation switches band-width switch.When reset pulse comes then, and KS gets at RS1, and the corner frequency of RC low pass filter is low, permissible Effectively filter out reset pulse high frequency components；When datum and pixel level come then, and KS gets at RS2, RC low-pass filtering The corner frequency of device is high, makes the free of losses as much as possible of CCD datum and pixel level pass through.
Two, low noise digital sample circuit based on CDS technology:
As it is shown on figure 3, it is made up of high-speed ADC and FPGA.The purpose of CCD camera digital sampling circuitry is to adopt accurately Ccd signal, reduce the noise of CCD as much as possible.Owing to reset noise is main interference source in ccd output signal, and Peripheral sampling processing circuit can be applied to suppress, and Correlated Double Sampling can effectively filter reset noise, so CCD phase Machine sample circuit typically uses analog domain CDS circuit.
This circuit is made up of high-speed ADC and FPGA two parts.First this circuit carries out high speed analog-to-digital conversion, secondly in numeral Territory carries out the low-pass filtering (LP) of sampled signal, finally carries out digital subtracting at numeric field and realizes relevant double employing.In numeral It is that digital subtractor is more accurate that territory carries out the advantage of CDS process.This circuit selects components and parts kind few (2 kinds), substantially increases The reliability of circuit.The most alternative analog-digital converter kind is more, such that it is able to increase the motility of circuit design.
High-speed ADC its objective is to sample ccd signal datum and pixel level and analog digital conversion.Owing to being phase Close double sampled, if the pixel clock frequency of CCD is fCcD, then sample frequency fSAMPLE=2fCCD, it is i.e. the 2 of pixel clock frequency Times.Therefore the maximum operating frequency selecting analog-digital converter is at least 2 times of pixel clock frequency.The figure place of analog-digital converter is then Dynamic range and application demand according to ccd signal select.
Wave digital lowpass filter (LP): way of realization use multiple sampled points be averaging, due in FPGA realize, time Under conditions of order relation allows, 2n sampled point of general collection, as it is shown on figure 3, be averaged the most againPermissible Remove high-frequency noise and reduction quantizing noise that AFE (analog front end) introduces further；
Numeral CDS: actually datum and the difference of pixel level sampled point.Can effectively suppress CCD video signal Reset noise and low-frequency noise.Way of realization is digital subtractor.Digital subtractor is to ccd signal datum conversion value SrefWith pixel level conversion value SpixCarry out subtraction, obtain digital picture S neededimg=Spix Sref.Due to SrefWith SpixBeing successively to carry out analog digital conversion in chronological order, therefore current conversion value and eve only need to be changed by digital subtractor Value carries out subtraction process.

Claims (4)

1. a low noise CCD camera circuitry, it is characterised in that: described CCD camera circuit includes the adjustable AFE (analog front end) of bandwidth Circuit and CCD camera digital sampling circuitry based on CDS technology；
Described analog front circuit includes that capacitance C, prime in-phase amplification circuit QF and bandwidth adjustable RC low-pass filtering are opened Close KG；Preamplifying circuit QF includes amplifier U；The resistance R being connected with the in-phase input end of amplifier U；With amplifier U reverse input end The resistance R1 connected and resistance R2；The Schottky diode D in parallel with resistance R2 and amplifier U reverse input end；Resistance RS1, electricity Resistance RS2 is connected with the outfan of amplifier U；Switch Ks and electric capacity Cs forms bandwidth rearrangeable switch KG；Ks analog switch open with Guan Bi switches over according to the phase relation of current CCD video signal output voltage waveforms, changes the bandwidth of AFE (analog front end)；
CCD camera digital sampling circuitry includes high-speed ADC and FPGA；Ccd signal datum and pixel level are entered by high-speed ADC Row sampling and analog digital conversion, FPGA realizes the control to ADC high-speed sampling, digital low-pass filtering and numeral CDS.
Low noise CCD camera circuitry the most according to claim 1, it is characterised in that: described high-speed ADC is relevant pair and adopts Sample, if the pixel clock frequency of CCD is fCCD, then sample frequency fSAMPLE=2fCCD, it is i.e. 2 times of pixel clock frequency.
Low noise CCD camera circuitry the most according to claim 2, it is characterised in that: also include wave digital lowpass filter LP, Use multiple sampled point to be averaging, realize in FPGA, under conditions of sequential relationship allows, gather 2n sampled point, afterwards It is averaged again, removes high-frequency noise and reduction quantizing noise that AFE (analog front end) introduces.
Low noise CCD camera circuitry the most according to claim 3, it is characterised in that: also include numeral CDS, be with reference to electricity The flat difference with pixel level sampled point, the reset noise of suppression CCD video signal and low-frequency noise, it is achieved form is digital subtracting Device, digital subtractor is to ccd signal datum conversion value SrefWith pixel level conversion value spixCarry out subtraction, obtain The digital picture needed.
CN201610601095.1A 2016-07-27 2016-07-27 Low-noise CCD camera circuit Active CN106101585B (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106961563A (en) * 2017-03-24 2017-07-18 长春长光辰芯光电技术有限公司 Low noise wide dynamic range imaging sensor correlation multiple repairing weld circuit
CN111918006A (en) * 2020-07-08 2020-11-10 北京时代民芯科技有限公司 Direct current reconstruction circuit for CCD signal processing
CN112910436A (en) * 2019-12-03 2021-06-04 华润微集成电路(无锡)有限公司 Second-order low-pass active filter integrated circuit for realizing demodulation sampling
CN115150570A (en) * 2022-09-06 2022-10-04 武汉加特林光学仪器有限公司 Double-sampling signal processing circuit based on digital circuit and display panel detection equipment

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106961563A (en) * 2017-03-24 2017-07-18 长春长光辰芯光电技术有限公司 Low noise wide dynamic range imaging sensor correlation multiple repairing weld circuit
CN106961563B (en) * 2017-03-24 2020-07-28 长春长光辰芯光电技术有限公司 Low-noise wide-dynamic-range image sensor related multi-sampling circuit
CN112910436A (en) * 2019-12-03 2021-06-04 华润微集成电路(无锡)有限公司 Second-order low-pass active filter integrated circuit for realizing demodulation sampling
CN111918006A (en) * 2020-07-08 2020-11-10 北京时代民芯科技有限公司 Direct current reconstruction circuit for CCD signal processing
CN111918006B (en) * 2020-07-08 2023-03-24 北京时代民芯科技有限公司 Direct current reconstruction circuit for CCD signal processing
CN115150570A (en) * 2022-09-06 2022-10-04 武汉加特林光学仪器有限公司 Double-sampling signal processing circuit based on digital circuit and display panel detection equipment

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