CN106960881A - Thin film transistor (TFT) and preparation method thereof - Google Patents
Thin film transistor (TFT) and preparation method thereof Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- Thin Film Transistor (AREA)
Abstract
The invention provides a kind of thin film transistor (TFT) and preparation method thereof.Thin film transistor (TFT) includes the gate electrode being arranged in substrate and the gate insulation layer for covering the gate electrode, also including folding the first electrode, active layer and the second electrode that are located on surface of the gate electrode away from substrate successively.Preparation method includes：Gate electrode and gate insulation layer are formed in substrate；First electrode, active layer and the second electrode folded be located on surface of the gate electrode away from substrate successively are formed on gate insulation layer.The present invention is located on surface of the gate electrode away from substrate by the way that first electrode, active layer and second electrode are folded successively, and orthographic projection of the orthographic projection of first electrode, active layer and second electrode in substrate with gate electrode in substrate is at least partly overlapped, effectively reduce the size of thin film transistor (TFT), aperture opening ratio can not only be improved, realize that high-resolution is shown, and aligning accuracy and line width control can be ensured, improve yields.
Description
Technical field
The present invention relates to display technology field, and in particular to a kind of thin film transistor (TFT) and preparation method thereof.
Background technology
Thin Film Transistor-LCD (Thin Film Transistor LiquidCrystal Display, TFT-
LCD) as a kind of panel display apparatus, because it has the relatively low spy of small volume, low in energy consumption, radiationless and cost of manufacture
Point, is applied among high-performance display field more and more.TFT-LCD agent structure include to the array base palte of box and
Color membrane substrates, array base palte includes multiple pixel cells of matrix arrangement, and pixel cell is hung down by a plurality of grid line and a plurality of data lines
Orthogonal fork is limited, and thin film transistor (TFT) is provided with the crossover location of grid line and data wire.
Figure 1A is the structural representation of existing array base palte, Figure 1B be in Figure 1A A-A to sectional view.Such as Figure 1A, Tu1BSuo
Show, array base palte includes grid line 20, data wire 30, pixel electrode 17 and thin film transistor (TFT), wherein, thin film transistor (TFT) and pixel electricity
Pole 17 is located in the pixel cell that grid line 20 and the square crossing of data wire 30 are limited.Thin film transistor (TFT) includes：It is arranged on substrate
Gate electrode 11 on 10, the gate insulation layer 12 of covering grid electrode 11 is arranged on the active layer 13 on gate insulation layer 12, has been arranged on
Source electrode 14 and drain electrode 15 in active layer 13.Wherein, gate electrode 11 is connected with grid line 20, the weight of data wire 30 and gate electrode 11
Source electrode 14 of the part as thin film transistor (TFT) is folded, drain electrode 15 is oppositely arranged with source electrode 14, and region forms horizontal ditch therebetween
Road, drain electrode 15 is connected by the via on passivation layer 16 with pixel electrode 17.When gate electrode loads scanning gate signal, grid electricity
Active layer above pole can be changed into conductive state from semi-conductive state, by the display signal from data wire by source electrode, have
Active layer and drain electrode are loaded on pixel electrode.
In recent years, high-resolution display panel is increasingly becoming industry development trend.Generally, the resolution ratio of display panel
(Pixels per inch, PPI) is relevant with the pixel aperture ratio of array base palte, and the pixel aperture ratio of array base palte with it is each
The film crystal pipe size of pixel cell is relevant, and region is bigger shared by thin film transistor (TFT), and pixel aperture ratio is with regard to smaller, display panel
Resolution ratio it is lower, therefore reduce film crystal pipe size be to carry one of high-resolution important channel.But for such as Figure 1A, figure
The thin-film transistor structure that source-drain electrode shown in 1B be arranged in parallel, by aligning accuracy and line in data-line width and preparation technology
The influences such as width control, reduce the structure type film crystal pipe size by severely restricts, therefore the film of existing structure form
Transistor is difficult to improve resolution ratio by reducing size.
The content of the invention
Embodiment of the present invention technical problem to be solved is to provide a kind of thin film transistor (TFT) and preparation method thereof, with gram
Existing thin film transistor (TFT) is taken to be difficult to by reducing the problem of size is to improve resolution ratio.
In order to solve the above-mentioned technical problem, the embodiments of the invention provide a kind of thin film transistor (TFT), including it is arranged on substrate
On gate electrode and cover the gate insulation layer of the gate electrode, be also located at surface of the gate electrode away from substrate including folding successively
On first electrode, active layer and second electrode.
Alternatively, described fold successively is located at first electrode on surface of the gate electrode away from substrate, active layer and the
Two electrodes include：The first electrode is arranged on gate insulation layer and its orthographic projection in substrate and the gate electrode are in substrate
On orthographic projection at least partly overlap, the active layer is set on the first electrode and its orthographic projection in substrate and the grid
Orthographic projection of the electrode in substrate is at least partly overlapped, and the second electrode is arranged on active layer and its positive throwing in substrate
Orthographic projection of the shadow with the gate electrode in substrate is at least partly overlapped, and the first electrode set, active layer and the second electricity are folded successively
Pole forms vertical channel structure.
Alternatively, the orthographic projection of the first electrode, active layer or second electrode in substrate and the gate electrode are in base
Orthographic projection on bottom, which is at least partly overlapped, to be included：The orthographic projection scope of first electrode, active layer or second electrode in substrate with
Orthographic projection scope of the gate electrode in substrate is identical, or, first electrode, active layer or second electrode in substrate just
Drop shadow spread is located within the scope of orthographic projection of the gate electrode in substrate.
Alternatively, the material of the active layer includes polysilicon or metal oxide, and thickness is 2000~8000 angstroms.
Alternatively, gate electrode width of orthographic projection in substrate is that first electrode or second electrode are just thrown in substrate
1.2~1.3 times of the width of shadow.
In order to solve the above-mentioned technical problem, the embodiment of the present invention additionally provides a kind of manufacture method of thin film transistor (TFT), bag
Include：
Gate electrode and gate insulation layer are formed in substrate；
Formed on gate insulation layer and fold the first electrode being located on surface of the gate electrode away from substrate, active layer successively
And second electrode.
Alternatively, it is described that first for folding be located on surface of the gate electrode away from substrate successively is formed on gate insulation layer
Electrode, active layer and second electrode, including：
First electrode, orthographic projection and institute of the first electrode in substrate are formed on gate insulation layer by patterning processes
Orthographic projection of the gate electrode in substrate is stated at least partly to overlap；Active layer is formed on the first electrode by patterning processes, it is described
Orthographic projection of orthographic projection of the active layer in substrate with the gate electrode in substrate is at least partly overlapped；Existed by patterning processes
Second electrode, orthographic projection of the second electrode in substrate and orthographic projection of the gate electrode in substrate are formed on active layer
At least partly overlap.
Alternatively, it is described that first for folding be located on surface of the gate electrode away from substrate successively is formed on gate insulation layer
Electrode, active layer and second electrode, including：
Formed by the patterning processes of intermediate tone mask or gray tone mask on gate insulation layer the folded first electrode set and
Active layer, the orthographic projection of the first electrode and active layer in substrate and orthographic projection of the gate electrode in substrate at least portion
Divide and overlap；Second electrode, orthographic projection of the second electrode in substrate and grid electricity are formed on active layer by patterning processes
Orthographic projection of the pole in substrate is at least partly overlapped.
Alternatively, it is described that first for folding be located on surface of the gate electrode away from substrate successively is formed on gate insulation layer
Electrode, active layer and second electrode, including：
First electrode, orthographic projection and institute of the first electrode in substrate are formed on gate insulation layer by patterning processes
Orthographic projection of the gate electrode in substrate is stated at least partly to overlap；By the patterning processes of intermediate tone mask or gray tone mask
Form the folded active layer set and second electrode on one electrode, the orthographic projection of the active layer and second electrode in substrate with it is described
Orthographic projection of the gate electrode in substrate is at least partly overlapped.
Alternatively, the orthographic projection of the first electrode, active layer or second electrode in substrate and the gate electrode are in base
Orthographic projection on bottom, which is at least partly overlapped, to be included：The orthographic projection scope of first electrode, active layer or second electrode in substrate with
Orthographic projection scope of the gate electrode in substrate is identical, or, first electrode, active layer or second electrode in substrate just
Drop shadow spread is located within the scope of orthographic projection of the gate electrode in substrate.
Alternatively, gate electrode width of orthographic projection in substrate is that first electrode or second electrode are just thrown in substrate
1.2~1.3 times of the width of shadow.
The embodiment of the present invention additionally provides a kind of array base palte, including grid line, data wire, pixel electrode and above-mentioned film
Transistor, the grid line is connected with the gate electrode of the thin film transistor (TFT), and the of the pixel electrode and the thin film transistor (TFT)
Two electrodes are connected, and orthographic projection of the data wire in substrate has overlay region with orthographic projection of the gate electrode in substrate
Domain, the corresponding data wire part in the overlapping region is allocated as the first electrode for thin film transistor (TFT).
The embodiment of the present invention additionally provides a kind of display panel, including above-mentioned array base palte.
Thin film transistor (TFT) that the embodiment of the present invention is provided and preparation method thereof, by by first electrode, active layer and
Two electrodes are folded be located on surface of the gate electrode away from substrate successively, and first electrode, active layer and second electrode are in substrate
Orthographic projection of the orthographic projection with gate electrode in substrate is at least partly overlapped, and is effectively reduced the size of thin film transistor (TFT), not only may be used
To improve aperture opening ratio, realize that high-resolution is shown, and aligning accuracy and line width control can be ensured, improve yields.
Certainly, any product or method for implementing the present invention it is not absolutely required to while reaching all the above excellent
Point.Other features and advantages of the present invention will be illustrated in subsequent specification embodiment, also, partly be implemented from specification
Become apparent, or understood by implementing the present invention in example.The purpose of the embodiment of the present invention and other advantages can pass through
Specifically noted structure is realized and obtained in specification, claims and accompanying drawing.
Brief description of the drawings
Accompanying drawing is used for providing further understanding technical solution of the present invention, and constitutes a part for specification, with this
The embodiment of application is used to explain technical scheme together, does not constitute the limitation to technical solution of the present invention.Accompanying drawing
In the shapes and sizes of each part do not reflect actual proportions, purpose is schematically illustrate present invention.
Figure 1A is the structural representation of existing array base palte, Figure 1B be in Figure 1A A-A to sectional view；
Fig. 2 is the structural representation of embodiment of the present invention thin film transistor (TFT)；
Fig. 3 A are the schematic diagram after first embodiment of the invention formation gate electrode and grid line pattern, and Fig. 3 B are A-A in Fig. 3 A
To sectional view；
Fig. 4 A are the schematic diagram after first embodiment of the invention formation source electrode and data line pattern, and Fig. 4 B are A- in Fig. 4 A
A is to sectional view；
Fig. 5 A are the schematic diagram after first embodiment of the invention formation active layer pattern, Fig. 5 B be in Fig. 5 A A-A to section view
Figure；
Fig. 6 A are the schematic diagram after first embodiment of the invention formation drain electrode pattern, Fig. 6 B be in Fig. 6 A A-A to section view
Figure；
Fig. 7 is the schematic diagram after second embodiment of the invention formation source electrode, data wire and active layer pattern；
Fig. 8 second embodiment of the invention schematic diagram to be formed after drain electrode pattern；
Fig. 9 third embodiment of the invention schematic diagram to be formed after active layer and drain electrode pattern；
The structural representation of Figure 10 A array base paltes of the present invention, Figure 10 B be in Figure 10 A A-A to sectional view.
Description of reference numerals:
| 10-substrate； | 11-gate electrode； | 12-gate insulation layer； |
| 13-active layer； | 14-the first (source) electrode； | 15-the second (leakage) electrode； |
| 16-passivation layer； | 17-pixel electrode. |
Embodiment
The embodiment to the present invention is described in further detail with reference to the accompanying drawings and examples.Following examples
For illustrating the present invention, but it is not limited to the scope of the present invention.It should be noted that in the case where not conflicting, the application
In embodiment and the feature in embodiment can mutually be combined.
At present, the horizontal channel structure that existing thin film transistor (TFT) is generally be arranged in parallel using source-drain electrode, by data line width
Degree and preparation technology in aligning accuracy and line width control etc. influence so that using the structure type thin film transistor (TFT) size
It is difficult to have substantive reduction.In order to overcome existing thin film transistor (TFT) to be difficult to improve resolution ratio by reducing film crystal pipe size
The problem of, the embodiments of the invention provide a kind of thin film transistor (TFT), array base palte and display panel.
Fig. 2 is the structural representation of embodiment of the present invention thin film transistor (TFT).As shown in Fig. 2 thin film transistor (TFT) includes grid electricity
Pole and gate insulation layer, and first electrode, active layer and the second electrode being located on surface of the gate electrode away from substrate are folded successively.
Specifically, thin film transistor (TFT) includes：
Gate electrode 11, is set on the substrate 10；
Gate insulation layer 12, covering grid electrode 11；
First electrode 14, is arranged on gate insulation layer 12, and its orthographic projection in substrate and gate electrode 11 are in substrate
Orthographic projection at least partly overlap；
Active layer 13, is arranged in first electrode 14, and its orthographic projection in substrate and gate electrode 11 are in substrate
Orthographic projection is at least partly overlapped；
Second electrode 15, is arranged on active layer 13, and its orthographic projection in substrate and gate electrode 11 are in substrate
Orthographic projection is at least partly overlapped.
Wherein, the first electrode 14 set, active layer 13 and the formation vertical channel structure of second electrode 15 are folded successively.First electricity
Extremely source electrode, second electrode is drain electrode；Or, first electrode is drain electrode, and second electrode is source electrode.The thickness of active layer
Spend for 2000~8000 angstroms, active layer material both can be polysilicon, form low temperature polycrystalline silicon (Low Temperature
Poly-Silicon, LTPS) thin film transistor (TFT) or metal oxide, form oxide (Oxide) thin film transistor (TFT).
The width of first electrode and the second electrode orthographic projection in substrate is 3~5 microns, and gate electrode width of orthographic projection in substrate is
4~6 microns, the width of gate electrode is 1.0~2.0 times of the width of first electrode or second electrode, it is preferable that the width of gate electrode
Degree is 1.2~1.3 times of the width of first electrode or second electrode.
A kind of thin film transistor (TFT) of vertical channel structure is present embodiments provided, due to by first electrode, active layer and
Two electrodes are folded be located on the surface of remote substrate of gate electrode successively, and first electrode, active layer and second electrode are in substrate
The orthographic projection in substrate of orthographic projection and gate electrode at least partly overlap, effectively reduce the size of thin film transistor (TFT), not only
Aperture opening ratio can be improved, realizes that high-resolution is shown, and aligning accuracy and line width control can be ensured, yields is improved.
The technical scheme of the embodiment of the present invention is further illustrated below by preparation process.
First embodiment
Fig. 3 A~6B prepares the schematic diagram of thin film transistor (TFT) first embodiment for the present invention.Wherein, it is described in the present embodiment
" patterning processes " include depositional coating, coating photoresist, mask exposure, development, etching, the processing such as stripping photoresist, be existing
There is the preparation technology of maturation.Deposition be able to can use known using the already known processes such as sputtering, evaporation, chemical vapor deposition, coating
Coating processes, etching can not do specific restriction herein using known method.
In first time patterning processes, pass through patterning processes formation gate electrode and grid line pattern in substrate.Form gate electrode
Include with grid line pattern：One first metallic film is deposited on the substrate 10, and one layer of photoresist is coated on the first metallic film, is adopted
Photoresist is exposed and developed with monotone mask plate, in gate electrode and grid line pattern position formation unexposed area, is protected
Photoresist is left, in other positions formation complete exposure area, photoresist is removed, to the first metal foil of complete exposure area
Film performs etching and peels off remaining photoresist, forms gate electrode 11 and the pattern of grid line 20.Then, a gate insulation layer 12 is deposited,
The covering grid electrode 11 of gate insulation layer 12 and the pattern of grid line 20, as shown in Fig. 3 A, Fig. 3 B.Wherein, substrate can use substrate of glass
Or quartz substrate, the first metallic film can using platinum Pt, ruthenium Ru, gold Au, silver Ag, molybdenum Mo, chromium Cr, aluminium Al, tantalum Ta, titanium Ti,
One or more in the metals such as tungsten W, gate insulation layer can be answered using silicon nitride SiNx, silicon oxide sio x or SiNx/SiOx
Close film.
In second of patterning processes, in the substrate for being formed with gate electrode pattern and gate insulation layer, pass through patterning processes shape
Into source electrode and data line pattern.Forming source electrode and data line pattern includes：One second metal is deposited on gate insulation layer 12
Film, one layer of photoresist is coated on the second metallic film, photoresist is exposed and developed using monotone mask plate,
Source electrode and data line pattern position form unexposed area, remain with photoresist, in other positions formation complete exposure area,
Photoresist is removed, and the second metallic film of complete exposure area is performed etching and remaining photoresist is peeled off, and forms source electricity
Pole 14 and the pattern of data wire 30, data wire 30 and the part of the overlapping region of gate electrode 11 are used as source electrode 14, i.e. source electrode 14
On surface of the gate electrode 11 away from substrate, orthographic projection of the source electrode 14 in substrate and positive throwing of the gate electrode 11 in substrate
Shadow is at least partly overlapped, as shown in Fig. 4 A, Fig. 4 B.Wherein, the second metallic film can using platinum Pt, ruthenium Ru, gold Au, silver Ag,
One or more in the metals such as molybdenum Mo, chromium Cr, aluminium Al, tantalum Ta, titanium Ti, tungsten W.
In third time patterning processes, on the substrate of active electrode pattern is formed, to form active by patterning processes
Layer pattern.Forming active layer pattern includes：An active layer film is deposited in the substrate for be formed with aforementioned pattern, it is thin in active layer
One layer of photoresist is coated on film, photoresist is exposed and developed using monotone mask plate, in active layer pattern position shape
Into unexposed area, photoresist is remained with, in other positions formation complete exposure area, photoresist is removed, to exposure completely
The active layer film in region performs etching and peels off remaining photoresist, forms the pattern of active layer 13, and active layer 13 is located at grid electricity
On surface of the pole 11 away from substrate, orthographic projection of the active layer 13 in substrate and orthographic projection of the gate electrode 11 in substrate at least portion
Divide and overlap, as shown in Fig. 5 A, Fig. 5 B.Wherein, active layer thickness is 2000~8000 angstroms, and material both can be non-crystalline silicon, polycrystalline
Silicon or microcrystalline silicon materials, form LTPS thin film transistor (TFT)s or metal oxide materials, form Oxide thin film transistor (TFT)s,
Metal oxide materials can be indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO) or the oxidation of indium tin zinc
Thing (Indium Tin Zinc Oxide, ITZO).
In 4th patterning processes, it is being formed with the substrate of active layer pattern, drain electrode is formed by patterning processes.Shape
Include into drain electrode pattern：One the 3rd metallic film is deposited in the substrate for be formed with aforementioned pattern, on the 3rd metallic film
One layer of photoresist is coated, photoresist is exposed and developed using monotone mask plate, in the formation of drain electrode pattern position not
Exposure area, remains with photoresist, and in other positions formation complete exposure area, photoresist is removed, to complete exposure area
The 3rd metallic film perform etching and peel off remaining photoresist, formed the pattern of drain electrode 15, drain electrode 15 be located at gate electrode
On 11 surfaces away from substrate, orthographic projection of the drain electrode 15 in substrate and orthographic projection of the gate electrode 11 in substrate are at least partly
Overlap, as shown in Fig. 6 A, Fig. 6 B.Wherein, the 3rd metallic film can using platinum Pt, ruthenium Ru, gold Au, silver Ag, molybdenum Mo, chromium Cr,
One or more in the metals such as aluminium Al, tantalum Ta, titanium Ti, tungsten W.
By preparing thin film transistor (TFT) process as can be seen that the present embodiment passes through 4 common masks shown in Fig. 3 A~6B
Patterning processes, form the thin film transistor (TFT) of vertical channel structure.The thin film transistor (TFT) of existing level channel structure, due to source
Electrode and drain electrode are be arranged in parallel, and source electrode, drain electrode and raceway groove are arranged on gate electrode, it is therefore desirable to by the width of gate electrode
Degree is designed to be more than three's width sum so that width of the gate electrode width equivalent to three data wires.Due to the present embodiment source
Electrode, active layer and drain electrode are folded be located on surface of the gate electrode away from substrate successively, and source electrode, active layer and drain electrode exist
The orthographic projection of orthographic projection in substrate with gate electrode in substrate is at least partly overlapped so that by the width design of gate electrode into etc.
In or slightly larger than source electrode (i.e. data wire) or drain electrode width.With the thin film transistor (TFT) phase of existing level channel structure
Than, the size of the present embodiment thin film transistor (TFT) can reduce 50%~60%, not only effectively reduce the size of thin film transistor (TFT),
And effectively prevent prepare in the display that causes of the factor such as aligning accuracy it is bad, so as to improve aperture opening ratio, improve non-defective unit
Rate.
In the present embodiment, " width " refers to the characteristic size in the data-line width direction of array base palte, in other words, refers to hang down
Directly in the characteristic size of data wire length direction.Therefore, the width or gate electrode of gate electrode width of orthographic projection in substrate are
Refer to, in the vertical direction (A-A to) as shown in Fig. 3 A~6B of data line length, the characteristic size in gate electrode section.Source electrode
The width of orthographic projection refers in substrate with the width or source electrode and drain electrode of drain electrode, in the vertical direction of data line length
(A-A to) as shown in Fig. 3 A~6B, the characteristic size in source electrode section and drain electrode section.In actually implementing, generally will
The lap of data wire and gate electrode is as source electrode, therefore the width of source electrode is equal to the width of data wire, or source electrode
The width of orthographic projection is equal to the width of data wire in substrate.In addition, in the present embodiment, " at least partly overlapping " refers to source electricity
Orthographic projection scope of the orthographic projection scope of pole, drain electrode or active layer in substrate with gate electrode in substrate is identical, i.e.,
The width of source electrode, drain electrode or the active layer orthographic projection in substrate is equal to orthographic projection width of the gate electrode in substrate, or
Refer to source electrode, the orthographic projection scope of drain electrode or active layer in substrate be located at orthographic projection scope of the gate electrode in substrate it
Interior, i.e., the width of source electrode, drain electrode or the active layer orthographic projection in substrate is less than the width of orthographic projection of the gate electrode in substrate
Degree, or refer to orthographic projection scope of the gate electrode in substrate positioned at the orthographic projection of source electrode, drain electrode or active layer in substrate
Within the scope of, i.e., the width of source electrode, drain electrode or the active layer orthographic projection in substrate is more than positive throwing of the gate electrode in substrate
The width of shadow.When actually implementing, the position relationship between source electrode, active layer and drain electrode can also be set, set wherein
One orthographic projection in substrate is identical with another or two orthographic projections in substrate, or, one of them
Orthographic projection in substrate is located in another or two orthographic projections in substrate.
Second embodiment
Fig. 7~Fig. 8 prepares the schematic diagram of thin film transistor (TFT) second embodiment for the present invention.The present embodiment is real based on first
A kind of extension of example is applied, and first embodiment unlike, the present embodiment forms vertical channel structure using 3 patterning processes
Thin film transistor (TFT).
In first time patterning processes, pass through patterning processes formation gate electrode and grid line pattern, such as Fig. 3 A, Fig. 3 B in substrate
It is shown.The present embodiment first time patterning processes are identical with the first time patterning processes of first embodiment, repeat no more here.
In second of patterning processes, in the substrate for being formed with gate electrode pattern and gate insulation layer, pass through patterning processes shape
Into source electrode, data wire and active layer pattern.Forming source electrode, data wire and active layer pattern includes：On gate insulation layer 12
The second metallic film and active layer film are sequentially depositing, one layer of photoresist is coated on active layer film, using intermediate tone mask
Version or gray tone mask plate carry out ladder exposure to photoresist and developed, in active layer pattern position formation unexposed area, tool
There is the photoresist of first thickness, in data wire pattern position formation partial exposure area, the photoresist with second thickness, at it
Remaining position forms complete exposure area, and unglazed photoresist, first thickness is more than second thickness.Etched away by first time etching technics
The active layer film and the second metallic film of complete exposure area, carry out photoresist ashing processing, photoresist is gone on the whole
Except second thickness, the active layer film of partial exposure area is exposed, passes through second of etching technics etch away sections exposure region
The active layer film in domain, peels off remaining photoresist, forms source electrode 14, the (not shown) of data wire 30 and the figure of active layer 13
Case, source electrode 14 is located on gate insulation layer 12, and active layer 13 is located in source electrode 14, both source electrode 14 and active layer 13 patterns
It is identical, orthographic projection at least partly weight of the orthographic projection of source electrode 14 and active layer 13 in substrate with gate electrode 11 in substrate
Close, as shown in Figure 7.
In third time patterning processes, it is being formed with the substrate of above-mentioned pattern, by patterning processes formation drain electrode, is such as scheming
Shown in 8.The present embodiment third time patterning processes are identical with the 4th patterning processes of first embodiment, repeat no more here.
During actual implementation, second of patterning processes can also form source electrode, data using the patterning processes of common mask
Line and active layer pattern, be specially：The second metallic film and active layer film are sequentially depositing on gate insulation layer, it is thin in active layer
One layer of photoresist is coated on film, photoresist is exposed and developed using common mask plate, in source electrode and data line pattern
Position forms unexposed area, remains with photoresist, and complete exposure area, unglazed photoresist are formed in remaining position.Pass through etching
Technique etches away the active layer film and the second metallic film of complete exposure area, peels off remaining photoresist, forms source electricity
Pole, data wire and active layer pattern.Wherein, active layer film is remained with data wire.
By preparing thin film transistor (TFT) process as can be seen that the present embodiment is by 3 shown in Fig. 3 A, Fig. 3 B, Fig. 7 and Fig. 8
Secondary patterning processes form the thin film transistor (TFT) of vertical channel structure, and 3 patterning processes can be 2 common masks and 1 time half
Tone mask plate or gray tone mask or 3 common masks.In the present embodiment, the parameter such as each film material and thickness
It is identical with first embodiment.Compared with the thin film transistor (TFT) of existing level channel structure, the size of the present embodiment thin film transistor (TFT)
50%~60% can be reduced.
3rd embodiment
Fig. 9~Figure 10 prepares the schematic diagram of thin film transistor (TFT) 3rd embodiment for the present invention.The present embodiment is to be based on first
A kind of extension of embodiment, and first embodiment unlike, the present embodiment forms vertical channel structures using 3 patterning processes
Thin film transistor (TFT).
In first time patterning processes, pass through patterning processes formation gate electrode and grid line pattern, such as Fig. 3 A, Fig. 3 B in substrate
It is shown.The present embodiment first time patterning processes are identical with the first time patterning processes of first embodiment, repeat no more here.
In second of patterning processes, in the substrate for being formed with gate electrode pattern and gate insulation layer, pass through patterning processes shape
Into source electrode and data line pattern, as shown in Fig. 4 A, Fig. 4 B.The second of second of patterning processes of the present embodiment and first embodiment
Secondary patterning processes are identical, repeat no more here.
In third time patterning processes, in the substrate for forming active electrode and data line pattern, formed by patterning processes
Active layer and drain electrode pattern.Forming active layer and drain electrode pattern includes：Sunk successively in the substrate for be formed with aforementioned pattern
The active layer film of product and the 3rd metallic film, coat one layer of photoresist, using intermediate tone mask on the 3rd metallic film film
Version or gray tone mask plate carry out ladder exposure to photoresist and developed, in drain electrode pattern position formation unexposed area, tool
There is the photoresist of first thickness, in active layer pattern position formation partial exposure area, the photoresist with second thickness, at it
Remaining position forms complete exposure area, and unglazed photoresist, first thickness is more than second thickness.Etched away by first time etching technics
3rd metallic film of complete exposure area and active layer film, carry out photoresist ashing processing, photoresist is gone on the whole
Except second thickness, the 3rd metallic film of partial exposure area is exposed, is exposed by second of etching technics etch away sections
3rd metallic film in region, peels off remaining photoresist, forms active layer 13 and the pattern of drain electrode 15, and active layer 13 is located at
In source electrode 14, drain electrode 15 is located on active layer 13, and orthographic projection width of the drain electrode 15 in substrate exists less than active layer 13
Orthographic projection width in substrate, the orthographic projection of active layer 13 and drain electrode 15 in substrate and positive throwing of the gate electrode 11 in substrate
Shadow is at least partly overlapped, as shown in Figure 9.
During actual implementation, third time patterning processes can also be using the patterning processes formation active layer of common mask and electric leakage
Pole figure case, be specially：Active layer film and the 3rd metallic film are sequentially depositing in the substrate for be formed with aforementioned pattern, the 3rd
One layer of photoresist is coated on metallic film film, photoresist is exposed and developed using common mask plate, in electric leakage pole figure
Case position forms unexposed area, remains with photoresist, and complete exposure area, unglazed photoresist are formed in remaining position.By carving
Etching technique etches away the 3rd metallic film and active layer film of complete exposure area, peels off remaining photoresist, is formed with
Active layer and drain electrode pattern.Wherein, both drain electrode and active layer pattern are identical.
By preparing thin film transistor (TFT) process as can be seen that the present embodiment shown in Fig. 3 A, Fig. 3 B, Fig. 4 A, Fig. 4 B and Fig. 9
The thin film transistor (TFT) of vertical channel structure is formd by 3 patterning processes, 3 patterning processes can be 2 common masks and 1
Secondary intermediate tone mask version or gray tone mask or 3 common masks.In the present embodiment, each film material and thickness etc.
Parameter is identical with first embodiment.Compared with the thin film transistor (TFT) of existing level channel structure, the present embodiment thin film transistor (TFT)
Size can reduce 50%~60%.
Fourth embodiment
On the basis of foregoing first~3rd embodiment technical scheme, include aforementioned film present invention also provides one kind brilliant
The array base palte of body pipe.The preparation process of array base palte includes：
Thin film transistor (TFT) is formed in substrate.
A passivation layer is deposited in the substrate for be formed with thin film transistor (TFT), one layer of photoresist is coated over the passivation layer, is used
Monotone mask plate is exposed and developed to photoresist, in passivation layer via hole pattern position formation complete exposure area, photoetching
Glue is removed, and is formed unexposed area in remaining position, is remained with photoresist, the passivation layer of complete exposure area is performed etching
And remaining photoresist is peeled off, passivation layer via hole pattern is formed, passivation layer via hole is located at second electrode position.Wherein, it is blunt
Silicon nitride SiNx, silicon oxide sio x or SiNx/SiOx laminated film can be used by changing layer.
A transparent conductive film is deposited over the passivation layer, one layer of photoresist is coated on transparent conductive film, using monochrome
Adjust mask plate to be exposed and develop photoresist, form unexposed area in pixel electrode pattern position, remain with photoresist,
Complete exposure area is formed in remaining position, photoresist is removed, the transparent conductive film of complete exposure area is performed etching
And remaining photoresist is peeled off, the pattern of pixel electrode 17 is formed, pixel electrode is connected by passivation layer via hole with second electrode, such as
Shown in Figure 10 A, Figure 10 B.
Array base palte prepared by the present embodiment includes：Grid line, data wire, thin film transistor (TFT) and pixel electrode, wherein, it is thin
Film transistor and pixel electrode are located in the pixel cell that grid line and data wire square crossing are limited, grid line and thin film transistor (TFT)
Gate electrode connection, the second electrode of pixel electrode and thin film transistor (TFT) connects, orthographic projection of the data wire in substrate with it is described
Orthographic projection of the gate electrode in substrate has an overlapping region, and the corresponding data wire part in the overlapping region is allocated as thin film transistor (TFT)
First electrode.Specifically, array base palte includes：
Gate electrode 11 and grid line 20 on the substrate 10 is set；
The gate insulation layer 12 of covering grid electrode 11 and grid line 20；
The first electrode 14 and data wire 30 being arranged on gate insulation layer 12, first electrode 14 are data wire 30 and gate electrode
11 lap, orthographic projection of the orthographic projection with gate electrode 11 in substrate in substrate is at least partly overlapped；
Be arranged on the active layer 13 in first electrode 14, its orthographic projection in substrate and gate electrode 11 in substrate just
Projection is at least partly overlapped；
Be arranged on the second electrode 15 on active layer 13, its orthographic projection in substrate and gate electrode 11 in substrate just
Projection is at least partly overlapped；
The passivation layer 16 of above-mentioned pattern is covered, passivation layer via hole is offered in the position of second electrode 15；
The pixel electrode 17 on passivation layer 16 is arranged on, pixel electrode 17 is connected by passivation layer via hole with second electrode 15
Connect.
Wherein, the first electrode 14 set, active layer 13 and the formation vertical channel structure of second electrode 15 are folded successively.First electricity
Extremely source electrode, second electrode is drain electrode；Or, first electrode is drain electrode, and second electrode is source electrode.The thickness of active layer
Spend for 2000~8000 angstroms, active layer material both can be polysilicon, form LTPS thin film transistor (TFT)s or metal oxidation
Thing, forms Oxide thin film transistor (TFT)s.The width of first electrode and the second electrode orthographic projection in substrate is 3~5 microns, grid electricity
The width of pole orthographic projection in substrate is 4~6 microns, and the width of gate electrode is the 1.0 of the width of first electrode or second electrode
~2.0 times, it is preferable that the width of gate electrode is 1.2~1.3 times of the width of first electrode or second electrode.
A kind of array base palte is present embodiments provided, is folded successively due to first electrode, active layer and second electrode and is located at grid
On surface of the electrode away from substrate, and the orthographic projection and gate electrode of first electrode, active layer and second electrode in substrate are in base
Orthographic projection on bottom is at least partly overlapped, and with less film crystal pipe size, can not only be improved aperture opening ratio, be realized high score
Resolution is shown, and can ensure aligning accuracy and line width control, improves yields.
5th embodiment
Inventive concept based on previous embodiment, the embodiments of the invention provide a kind of preparation method of thin film transistor (TFT),
Including：
S1, formation gate electrode and gate insulation layer in substrate；
S2, formed on gate insulation layer and to fold the first electrode being located on surface of the gate electrode away from substrate, active layer successively
And second electrode.
In one embodiment, step S2 can include：
S211, form first electrode on gate insulation layer by patterning processes, orthographic projection of the first electrode in substrate with
Orthographic projection of the gate electrode in substrate is at least partly overlapped；
S212, form active layer on the first electrode by patterning processes, orthographic projection of the active layer in substrate and grid electricity
Orthographic projection of the pole in substrate is at least partly overlapped；
S213, second electrode, orthographic projection and grid of the second electrode in substrate are formed on active layer by patterning processes
Orthographic projection of the electrode in substrate is at least partly overlapped.
In another embodiment, step S2 can include：
S221, folded the first electricity set is formed on gate insulation layer by the patterning processes of intermediate tone mask or gray tone mask
Orthographic projection at least partly weight of the orthographic projection of pole and active layer, first electrode and active layer in substrate with gate electrode in substrate
Close；
S222, second electrode, orthographic projection and grid of the second electrode in substrate are formed on active layer by patterning processes
Orthographic projection of the electrode in substrate is at least partly overlapped.
In another embodiment wherein, step S2 can include：
S231, form first electrode on gate insulation layer by patterning processes, orthographic projection of the first electrode in substrate with
Orthographic projection of the gate electrode in substrate is at least partly overlapped；
S232, by the patterning processes of intermediate tone mask or gray tone mask the folded active layer set is formed on the first electrode
And second electrode, orthographic projection at least partly weight of the orthographic projection of active layer and second electrode in substrate with gate electrode in substrate
Close.
Wherein, the first electrode set, active layer and second electrode formation vertical channel structure are folded successively.First electrode is source
Electrode, second electrode is drain electrode；Or, first electrode is drain electrode, and second electrode is source electrode.The thickness of active layer is
2000~8000 angstroms, active layer material both can be polysilicon, form LTPS thin film transistor (TFT)s or metal oxide,
Form Oxide thin film transistor (TFT)s.The width of first electrode and the second electrode orthographic projection in substrate is 3~5 microns, and gate electrode exists
The width of orthographic projection is 4~6 microns in substrate, and the width of gate electrode is the 1.0~2.0 of the width of first electrode or second electrode
Times, it is preferable that the width of gate electrode is 1.2~1.3 times of the width of first electrode or second electrode.
Sixth embodiment
Inventive concept based on previous embodiment, the embodiment of the present invention additionally provides a kind of display panel, the display panel
Including the thin film transistor (TFT) using previous embodiment, or including the array base palte using previous embodiment.Display panel can be：
Any production with display function such as mobile phone, panel computer, television set, display, notebook computer, DPF, navigator
Product or part, can be liquid crystal (Liquid Crystal Display, LCD) display panel or organic light-emitting diodes
Manage (Organic Light-Emitting Diode, OLED) display panel etc..
In the description of the embodiment of the present invention, it is to be understood that term " middle part ", " on ", " under ", "front", "rear",
The orientation or position relationship of the instruction such as " vertical ", " level ", " top ", " bottom " " interior ", " outer " be based on orientation shown in the drawings or
Position relationship, is for only for ease of the description present invention and simplifies description, rather than indicate or imply that the device or element of meaning must
There must be specific orientation, with specific azimuth configuration and operation, therefore be not considered as limiting the invention.
, it is necessary to which explanation, unless otherwise clearly defined and limited, term " are pacified in the description of the embodiment of the present invention
Dress ", " connected ", " connection " should be interpreted broadly, for example, it may be fixedly connected or be detachably connected, or integratedly
Connection；Can be mechanical connection or electrical connection；Can be joined directly together, can also be indirectly connected to by intermediary,
It can be the connection of two element internals.For the ordinary skill in the art, above-mentioned art can be understood with concrete condition
The concrete meaning of language in the present invention.
Although disclosed herein embodiment as above, described content be only readily appreciate the present invention and use
Embodiment, is not limited to the present invention.Technical staff in any art of the present invention, is taken off not departing from the present invention
On the premise of the spirit and scope of dew, any modification and change, but the present invention can be carried out in the form and details of implementation
Scope of patent protection, must be still defined by the scope of which is defined in the appended claims.
Claims (14)
1. a kind of thin film transistor (TFT), including the gate electrode being arranged in substrate and the gate insulation layer for covering the gate electrode, it is special
Levy and be, also including folding the first electrode, active layer and the second electrode that are located on surface of the gate electrode away from substrate successively.
2. thin film transistor (TFT) according to claim 1, it is characterised in that described fold successively is located at the gate electrode away from base
First electrode, active layer and second electrode on the surface at bottom include：The first electrode be arranged on gate insulation layer and its
Orthographic projection of the orthographic projection with the gate electrode in substrate in substrate is at least partly overlapped, and the active layer is arranged on the first electricity
The orthographic projection at least part of extremely upper and orthographic projection that it is in substrate with the gate electrode in substrate is overlapped, the second electrode
It is arranged on active layer and its orthographic projection of orthographic projection with the gate electrode in substrate in substrate is at least partly overlapped, according to
The secondary folded first electrode set, active layer and second electrode formation vertical channel structure.
3. thin film transistor (TFT) according to claim 2, it is characterised in that the first electrode, active layer or second electrode
The orthographic projection of orthographic projection in substrate with the gate electrode in substrate at least partly overlap including：First electrode, active layer
Or orthographic projection scope of orthographic projection scope of the second electrode in substrate with gate electrode in substrate is identical, or, first
The orthographic projection scope of electrode, active layer or second electrode in substrate is located within the scope of orthographic projection of the gate electrode in substrate.
4. thin film transistor (TFT) according to claim 1, it is characterised in that the material of the active layer includes polysilicon or gold
Belong to oxide, thickness is 2000~8000 angstroms.
5. according to any described thin film transistor (TFT) of Claims 1 to 4, it is characterised in that the gate electrode is just thrown in substrate
The width of shadow is first electrode or second electrode 1.2~1.3 times of the width of orthographic projection in substrate.
6. a kind of preparation method of thin film transistor (TFT), it is characterised in that including：
Gate electrode and gate insulation layer are formed in substrate；
To be formed fold successively on gate insulation layer and be located at first electrode on surface of the gate electrode away from substrate, active layer and the
Two electrodes.
7. preparation method according to claim 6, it is characterised in that it is described formed to fold successively on gate insulation layer be located at institute
First electrode, active layer and the second electrode on surface of the gate electrode away from substrate are stated, including：
First electrode, orthographic projection of the first electrode in substrate and the grid are formed on gate insulation layer by patterning processes
Orthographic projection of the electrode in substrate is at least partly overlapped；Active layer is formed on the first electrode by patterning processes, it is described active
Orthographic projection of orthographic projection of the layer in substrate with the gate electrode in substrate is at least partly overlapped；By patterning processes active
Second electrode is formed on layer, orthographic projection of the second electrode in substrate and orthographic projection of the gate electrode in substrate are at least
Partially overlap.
8. preparation method according to claim 6, it is characterised in that it is described formed to fold successively on gate insulation layer be located at institute
First electrode, active layer and the second electrode on surface of the gate electrode away from substrate are stated, including：
By the patterning processes of intermediate tone mask or gray tone mask the folded first electrode set is formed on gate insulation layer and active
Layer, orthographic projection at least partly weight of the orthographic projection of the first electrode and active layer in substrate with the gate electrode in substrate
Close；Second electrode is formed on active layer by patterning processes, orthographic projection of the second electrode in substrate exists with the gate electrode
Orthographic projection in substrate is at least partly overlapped.
9. preparation method according to claim 6, it is characterised in that it is described formed to fold successively on gate insulation layer be located at institute
First electrode, active layer and the second electrode on surface of the gate electrode away from substrate are stated, including：
First electrode, orthographic projection of the first electrode in substrate and the grid are formed on gate insulation layer by patterning processes
Orthographic projection of the electrode in substrate is at least partly overlapped；By the patterning processes of intermediate tone mask or gray tone mask in the first electricity
It is extremely upper to form the folded active layer set and second electrode, the orthographic projection of the active layer and second electrode in substrate and grid electricity
Orthographic projection of the pole in substrate is at least partly overlapped.
10. preparation method according to claim 6, it is characterised in that the material of the active layer includes polysilicon or gold
Belong to oxide, thickness is 2000~8000 angstroms.
11. the preparation method according to claim 7,8 or 9, it is characterised in that the first electrode, active layer or second
The orthographic projection of orthographic projection of the electrode in substrate and the gate electrode in substrate at least partly overlap including：First electrode, have
Orthographic projection scope of the orthographic projection scope of active layer or second electrode in substrate with gate electrode in substrate is identical, or,
The orthographic projection scope of first electrode, active layer or second electrode in substrate be located at orthographic projection scope of the gate electrode in substrate it
It is interior.
12. according to any described preparation method of claim 6~10, it is characterised in that the gate electrode is just thrown in substrate
The width of shadow is first electrode or second electrode 1.2~1.3 times of the width of orthographic projection in substrate.
13. a kind of array base palte, it is characterised in that including grid line, data wire, pixel electrode and such as any institute of Claims 1 to 5
The thin film transistor (TFT) stated, the grid line is connected with the gate electrode of the thin film transistor (TFT), and the pixel electrode is brilliant with the film
The second electrode connection of body pipe, orthographic projection of orthographic projection of the data wire in substrate with the gate electrode in substrate has
Overlapping region, the corresponding data wire part in the overlapping region is allocated as the first electrode for thin film transistor (TFT).
14. a kind of display panel, it is characterised in that including array base palte as claimed in claim 13.
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107845687A (en) * | 2017-10-27 | 2018-03-27 | 合肥鑫晟光电科技有限公司 | Thin film transistor (TFT) and preparation method thereof, electronic equipment |
| CN107845676A (en) * | 2017-10-23 | 2018-03-27 | 京东方科技集团股份有限公司 | Thin film transistor (TFT), array base palte and display device |
| CN108257981A (en) * | 2018-01-22 | 2018-07-06 | 深圳市华星光电半导体显示技术有限公司 | Display base plate |
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| WO2019041553A1 (en) * | 2017-09-01 | 2019-03-07 | 深圳市华星光电技术有限公司 | Vertical channel organic thin film transistor for pixel structure and preparation method therefor |
| CN107845676A (en) * | 2017-10-23 | 2018-03-27 | 京东方科技集团股份有限公司 | Thin film transistor (TFT), array base palte and display device |
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| US20190229129A1 (en) * | 2018-01-22 | 2019-07-25 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display substrate |
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| US10790311B2 (en) * | 2018-01-22 | 2020-09-29 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display substrate |
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| US10868060B2 (en) | 2018-08-16 | 2020-12-15 | Boe Technology Group Co., Ltd. | Photoelectric detection substrate, method for fabricating the same, and photoelectric detection device |
| CN109686744A (en) * | 2018-12-25 | 2019-04-26 | 武汉天马微电子有限公司 | TFT substrate, OLED display panel and manufacturing method |
| CN109686744B (en) * | 2018-12-25 | 2020-06-26 | 武汉天马微电子有限公司 | TFT substrate, OLED display panel and manufacturing method |
| WO2021184910A1 (en) * | 2020-03-18 | 2021-09-23 | 京东方科技集团股份有限公司 | Thin film transistor and method for manufacturing same, and display device |
| CN111370496B (en) * | 2020-03-18 | 2021-10-26 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method thereof and display device |
| CN111370496A (en) * | 2020-03-18 | 2020-07-03 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method thereof and display device |
| US12041795B2 (en) | 2020-03-18 | 2024-07-16 | Boe Technology Group Co., Ltd. | Thin film transistor and method for manufacturing the same, display device |
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| WO2023245604A1 (en) * | 2022-06-24 | 2023-12-28 | 京东方科技集团股份有限公司 | Thin-film transistor and preparation method therefor, and display device |
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