CN106877870A - Adc circuit and its method for sampling - Google Patents
Adc circuit and its method for sampling Download PDFInfo
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- CN106877870A CN106877870A CN201510927264.6A CN201510927264A CN106877870A CN 106877870 A CN106877870 A CN 106877870A CN 201510927264 A CN201510927264 A CN 201510927264A CN 106877870 A CN106877870 A CN 106877870A
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Abstract
The invention provides a kind of adc circuit and its method for sampling, adc circuit includes：Integrator, controller, counter and comparator；The input of integrator is with the first switching switch so that its input switches between signal to be sampled and multiple reference signals, and its output end is connected with the first input end of comparator；Second input of comparator is switched by the second switching switch between at least one reference signal and ground end signal, and its output end is connected with counter；Controller is used to control the first switching switch to switch between signal to be sampled and multiple reference signals, and counter starts counting up and terminates to count.Integrator is being treated after sampled signal carries out positive integration, by the way that multiple reference signals are carried out with multistep reverse integral, improves the conversion speed and sampling precision of adc circuit, improves the authenticity of sampled signal.
Description
Technical field
The present invention relates to application of electronic technology field, especially a kind of adc circuit and its method for sampling.
Background technology
Electronic integrator is that a kind of output valve that can make any time was equal to input signal before the moment
The electronic equipment of the summation of all input values, is applied to various occasions.In TOKAMAK experiment, generally
Using magnetic induction principle come the magnetic field inside measurement apparatus and magnetic flux, it is therefore desirable to integrator to magnetic probe,
Luo Ke coils and the differential signal of single turn ring output are integrated, so as to carry out diagnosis and the position shape of plasma
Control.
As shown in figure 1, traditional adc circuit includes：One with input switching switch 102 integrator 101,
One comparator, 103, counter 104 and a controller 105.Input switching switch 102 causes institute
The input for stating integrator 101 can switch between signal to be sampled and reference voltage, the integrator 101
Output end be connected with an input of the comparator 103.Another input of the comparator 103
End is connected to ground, and output end is connected with the counter 104, and the controller 105 is used to control described cutting
Change switch 102.
Its operation principle is：Input voltage is transformed into the time interval being directly proportional to its average value, then this
Time interval is converted into digital quantity.
Specifically, as shown in Fig. 2 the process of method A/D conversions is divided into two stages：
First stage：The controller first controls the switching switch so that the input termination of the integrator
Lead to signal Vin to be sampled, the signal Vin to be sampled is analog signal, and the integrator is since zero moment
It is fixed the positive integration of time T0.
Second stage：The controller first controls the switching switch so that the input termination of the integrator
Lead to the reference voltage Vref, the reference voltage Vref and signal Vin opposite polarities to be sampled, the product
Dividing device carries out reverse integral, while the counter is started counting up, until integrator output Vo is 0V
When stop integration, i.e., described comparator output voltage Vc is 0V, and counter stops counting, and count value is
Count1, the reverse integral time is T1.Vin is bigger, and the output voltage during integrator forward direction integration is bigger,
The reverse integral time is also more long.The numerical value that the counter is counted within the reverse integral time, it is exactly described to treat
Digital quantity corresponding to sampled signal Vin, this process realizes an A/D conversion.Complete an A/D
Time required for conversion is (T0+T1), wherein, T1=count1*Tclk, when Tclk is the counter
Clock cycle time.Digital acquisition signal corresponding to the signal Vin to be sampled is count1.In whole A/D
During conversion, conversion speed is slow, it is impossible to the need for meeting high speed acquisition.
The content of the invention
It is an object of the invention to provide a kind of adc circuit and its method for sampling, to solve A/D conversion speed
The slow problem of degree.
In order to achieve the above object, the invention provides a kind of adc circuit and its method for sampling, wherein, institute
Stating adc circuit includes：Integrator, controller, counter and comparator；
The input of the integrator with one first switching switch so that its input signal to be sampled with
Switch between multiple reference signals, its output end is connected with the first input end of the comparator；
Second input of the comparator by one second switching switch in reference signal described at least one and
Switch between ground end signal, its output end is connected with the input of the counter；
The output end of the counter is connected with the input of controller；
The controller is used to control the first switching switch in the signal to be sampled and multiple reference signals
Between switch, and control it is described second switching switch reference signal described at least one and ground end signal between
Switching.
Preferably, in above-mentioned adc circuit, the reference signal of the second input connection of the comparator
Signal value absolute value less than the integrator input connect reference signal signal value it is absolute
Value.
Preferably, in above-mentioned adc circuit, the reference signal is provided with M, and M is more than 1
Positive integer, the reference signal of the wherein maximum absolute value of signal value is set to the first reference signal；
When the input of the integrator connects first reference signal, the second input of the comparator
Connect i-th reference signal, 1 ＜ i≤M；Then the controller control the first switching switch causes institute
The input for stating integrator connects i-th reference signal, while control the second switching switch causes institute
The second input for stating comparator connects j-th reference signal or ground end signal, wherein, 1 ＜ j≤M；
If the second input of the comparator connects j-th reference signal, first switching is controlled
Switch causes that the input of the integrator connects j-th reference signal, while control second switching
The signal that second input of the switch adjustment comparator is connected, is so repeated up to the comparator
Second input connection ground end signal.
Preferably, in above-mentioned adc circuit, the absolute value of the signal value of first reference signal is letter
N times of the minimum reference signal of the absolute value of number value, N is the positive integer more than 1.
Preferably, in above-mentioned adc circuit, the multiple reference signal is negative signal, described to be sampled
Signal is positive signal.
Preferably, in above-mentioned adc circuit, the multiple reference signal is positive signal, described to be sampled
Signal is negative signal.
Preferably, in above-mentioned adc circuit, the signal to be sampled and reference signal are voltage signal.
Present invention also offers a kind of method sampled using adc circuit as described above, including：
Sampled signal is treated to be integrated；
Step integration is carried out to multiple reference signals, counter is started counting up, until the output signal of comparator
Overturn, the counting of the counter is the digital acquisition signal of the signal to be sampled.
Preferably, in the above-mentioned adc circuit method of sampling, when being integrated to the signal to be sampled,
Controller controls the first switching switch to cause that the input signal of integrator input is signal to be sampled, comparator
First input end be connected with the output end of the integrator, the second input of the comparator connects with ground terminal
Connect.
Preferably, in the above-mentioned adc circuit method of sampling, step integration is carried out to multiple reference signals
During, the absolute value of the signal value of the reference signal of the second input connection of the comparator is less than described
The absolute value of the signal value of the reference signal of the input connection of integrator.
Preferably, in the above-mentioned adc circuit method of sampling, step integration is carried out to multiple reference signals
Step includes：
The reference signal is provided with M, and M is the positive integer more than 1, and wherein the absolute value of signal value is most
Big reference signal is set to the first reference signal；
Step one：When the input of the integrator connects first reference signal, the of the comparator
Two inputs connect i-th reference signal, 1 ＜ i≤M；
Step 2：Controller control the first switching switch causes the input connection of the integrator
I-th reference signal, while control the second switching switch causes the second input of the comparator
J-th reference signal or ground end signal are connected, wherein, 1 ＜ j≤M；
If the second input of the comparator connects j-th reference signal, two are repeated the above steps,
Until the second input connection ground end signal of the comparator.
Preferably, in the above-mentioned adc circuit method of sampling, the signal value of first reference signal it is exhausted
It is N times of the reference signal of the absolute value minimum of signal value to value, N is the positive integer more than 1.
Preferably, in the above-mentioned adc circuit method of sampling, the multiple reference signal is negative signal, institute
Signal to be sampled is stated for positive signal.
Preferably, in the above-mentioned adc circuit method of sampling, the multiple reference signal is positive signal, institute
Signal to be sampled is stated for negative signal.
Preferably, in the above-mentioned adc circuit method of sampling, the signal to be sampled and reference signal are
Voltage signal.
In the adc circuit and its method for sampling that the present invention is provided, the input of integrator is cut with one first
Change switch so that its input switches between signal to be sampled and multiple reference signals, and the integrator exists
After carrying out positive integration to the signal to be sampled, reversely accumulated by carrying out multistep to the multiple reference signal
Point, the conversion speed and sampling precision of the adc circuit are improved, improve the authenticity of sampled signal.
Brief description of the drawings
Fig. 1 is the schematic diagram of traditional adc circuit；
Fig. 2 is the schematic diagram of traditional adc circuit A/D conversions；
Fig. 3 is the schematic diagram of adc circuit in the embodiment of the present invention；
Fig. 4 is the schematic diagram of adc circuit A/D conversions in the embodiment of the present invention；
Fig. 5 is the flow chart of the adc circuit method of sampling in the embodiment of the present invention；
In figure：101- integrators；102- input switching switches；103- comparators；104- counters；105- is controlled
Device processed；
201- integrators；The switching switches of 202- first；203- comparators；204- counters；205- controllers；
The switching switches of 206- second.
Specific embodiment
Specific embodiment of the invention is described in more detail below in conjunction with schematic diagram.According to following
Description and claims, advantages and features of the invention will become apparent from.It should be noted that, accompanying drawing is used
Very simplified form and use non-accurately ratio, be only used to conveniently, lucidly aid in illustrating the present invention
The purpose of embodiment.
A kind of adc circuit and its method for sampling are the embodiment of the invention provides, wherein, as shown in figure 3, institute
Stating adc circuit includes：Integrator 201, controller 205, counter 204 and comparator 203.
Specifically, the input of the integrator 201 is with one first switching switch 202 so that its input
Switch between signal to be sampled and multiple reference signals.The pole of the multiple reference signal and signal to be sampled
Property is opposite.And the order of magnitude of the signal value of the multiple reference signal is different, for example, will be the multiple
The reference signal of the maximum absolute value of signal value is set to the first reference signal Vref_max in reference signal, letter
The minimum reference signal of the absolute value of number value is set to the second reference signal Vref_min,
Vref_max=N*Vref_min.(formula 1)
Wherein, N>1.
N can be natural number, or fraction or decimal, that is to say, that first reference signal can be with
It is the natural several times of the second reference signal, it is also possible to be not nature several times.
Further, the absolute value of first reference signal is more than the reference voltage Vref in tradition ADC,
Speed of the integrator during reverse integral could so be improved.
The output end of the integrator 204 is connected with an input of the comparator 203, i.e., with it is described
The first input end connection of comparator 203, and another input of the comparator 203, i.e., second are defeated
Enter end, switch 206 by one second switching switches between reference signal described at least one and ground end signal.
Further, when the described first switching switch 202 switches between the multiple reference signal,
The second switching switch 206 also switches between reference signal described at least one and ground end signal, to protect
Demonstrate,prove the input of the input signal less than the input of the integrator 201 of the second input of the comparator 203
Signal, so as to realize step integration.
Specifically, the reference signal is provided with M, M is the positive integer more than 1, wherein signal value
The reference signal of maximum absolute value is set to the first reference signal.
First, the input of the integrator is connected into first reference signal, the second of the comparator
Input connects i-th reference signal, 1 ＜ i≤M.Then the controller control first switching is switched
So that the input of the integrator connects i-th reference signal, while control the second switching switch
So that the second input of the comparator connects j-th reference signal or ground end signal, wherein, 1 ＜ j≤M；
Absolute value of j-th absolute value of the signal value of reference signal less than the signal value of i-th reference signal.
If the second input of the comparator connects j-th reference signal, first switching is controlled
Switch causes that the input of the integrator connects j-th reference signal, while control second switching
The signal that second input of the switch adjustment comparator is connected, the second input institute of the comparator
Connect the absolute value of the absolute value less than the signal value of j-th reference signal of the signal value of signal, so weight
Again until the second input connection ground end signal of the comparator.
The output end of the comparator 203 is connected with counter 204, and the controller 205 is used to control institute
State the first switching switch 202 and switch between the signal to be sampled and multiple reference signals, and the meter
Number device 204 starts counting up and terminates to count.The counter 204 is used to be carried out instead in the integrator 201
Counted in integral process.
In the present embodiment, by taking two reference signals as an example, i.e. the first reference voltage Vref _ 1 and second refers to
Voltage Vref_2, wherein, Vref_1=N*Vref_2, N>1.And second reference voltage Vref _ 2 and biography
Reference voltage in system adc circuit is equal, i.e. Vref_2=Vref, to ensure adc circuit in the present embodiment
The precision of A/D conversions is identical with traditional adc circuit A/D conversion accuracies.
As shown in figure 5, as follows using the method that adc circuit as described above is sampled：
S1：Sampled signal is treated to be integrated.
In the present embodiment, the signal to be sampled is positive voltage signal, and the reference signal is believed for negative voltage
Number.
Controller control the first switching switch so that the input signal of the input of the integrator
It is the signal to be sampled, meanwhile, the second input of the comparator is connected with ground terminal, the integrator
Carry out positive integration.
S2：Step integration is carried out to multiple reference signals, counter is started counting up, until the output of comparator
Signal overturns, and the counting of the counter is the digital acquisition signal of the signal to be sampled.
Specifically, the reference signal is provided with M, M is the positive integer more than 1, wherein signal value
The reference signal of maximum absolute value is set to the first reference signal.
The opposite polarity of the reference signal and signal to be sampled.I.e. when the signal to be sampled is positive signal,
The reference signal is negative signal.When the signal to be sampled is negative signal, the reference signal is positive letter
Number.In the present embodiment, the signal to be sampled is positive signal, and the reference signal is negative signal.And institute
State signal to be sampled and reference signal is voltage signal.
During step integration is carried out to the multiple reference signal, the second input of the comparator
The absolute value of the signal value of the reference signal of connection is less than the reference signal that the input of the integrator is connected
The absolute value of signal value.
Step S21：When the input of the integrator connects first reference signal, the of the comparator
It is natural number that two inputs connect i-th reference signal, 1 ＜ i≤M, and i.
Due to the absolute value of the signal value of first reference signal be in all reference signals it is maximum, therefore,
The absolute value of the signal value of i-th reference signal is absolute less than the signal value of first reference signal
Value.
Integrator carries out first step reverse integral, and unison counter is started counting up, until the comparator is defeated
When going out to overturn, the integrator stops first step reverse integral, and the counter stops counting.Then
Perform next step.
Step S22：Controller control the first switching switch causes the input connection of the integrator
I-th reference signal, while control the second switching switch causes the second input of the comparator
J-th reference signal or ground end signal are connected, wherein, i ≠ j, 1 ＜ j≤M, and j is natural number.
The absolute value of the signal value of j-th reference signal is less than the signal value of i-th reference signal
Absolute value.
The integrator starts another step reverse integral, while the counter is started counting up herein, until institute
When the output for stating comparator overturns again, the integrator stops the reverse integral of the step, the counting
Device stops counting again.
If now, the second input of the comparator connects j-th reference signal, then repeat step S22,
Until the second input connection ground end signal of the comparator.
When the second input connection ground end signal of the comparator, the integrator stops the step reverse integral
When, the counting of the counter is the digital acquisition signal of the signal to be sampled.
Using above-mentioned adc circuit sample and realize that the principle that A/D is changed is identical with traditional adc circuit,
As shown in figure 4, connecting example, the process of A/D conversions is divided into three phases, and specific method is as follows：
First stage：The same with tradition adc circuit, controller control the first switching switch makes
The input signal Vs for obtaining the input of the integrator is the signal to be sampled, meanwhile, the comparator
Second input is connected with ground terminal, and the integrator carries out positive integration.For convenience embody the present invention
Beneficial effect, signal described to be sampled in the present embodiment is identical with traditional adc circuit, is
Vin, the time that the integrator carries out positive integration is also identical, is T0.
Second stage, controller control the first switching switch so that the input of the integrator
Input signal Vs be the first reference voltage Vref _ 1, the input signal of the second input of the comparator is
Second reference voltage Vref _ 2, wherein, Vref_1=N*Vref_2=N*Vref, N>1.Described first
The polarity of reference voltage Vref _ 1 and the second reference voltage Vref _ 2 is opposite with the signal to be sampled.
The integrator starts reverse integral, and unison counter is started counting up, until the output of the integrator
When the output voltage Vo at end is Vref_2, i.e., when the output of described comparator overturns, the integrator stops
Only integrate, the counter stops counting, the counter is counted as count_1, and the integrator is reverse
The time of integration is t3.
Due to Vref_1=N*Vref, N>1, according to integral principle, in the present embodiment in this stage, i.e.,
So that during the output voltage of the integrator reaches this stage of Vref_2, the integrator reverse integral when
Between be 1/N, i.e. t3=(1/N) * t5, N in Fig. 4 in traditional adc circuit>1, then 1/N<1, t3<T5,
In Fig. 4 it is also seen that.
Phase III, controller control the first switching switch so that the integrator input
Input signal Vs is second reference voltage Vref _ 2, the polarity of second reference voltage Vref _ 2 also with
The signal to be sampled is conversely, simultaneously, control the second switching switch to cause that the comparator second is input into
End ground connection, the integrator proceeds reverse integral, while the counter continues to start counting up, until
When the output voltage Vo of the integrator is 0V, i.e., when the output of described comparator overturns again, institute
State integrator and stop integration, the counter stops counting, the counter is counted as count_2, described
The time of integrator reverse integral is t4.
Due to Vref_2=Vref, therefore, the integrator output voltage from Vref_2 reach 0V this
It is identical in the time of the integrator reverse integral and traditional adc circuit in stage, i.e. in Fig. 4
T4=t6.
So far, adc circuit realizes an A/D conversion in the embodiment of the present invention, and the signal institute to be sampled is right
The count value answered, i.e., corresponding digital acquisition signal after A/D conversions is carried out to the signal to be sampled is：
(count_1*N+count_2)。
Due in this embodiment it is assumed that signal to be sampled and tradition in the embodiment of the present invention in adc circuit
As in adc circuit, Vin is, that is, assumed using both different circuits to same letter to be sampled
Number Vin carries out A/D conversions, and, as an example embodiment that two kinds of circuit Counter clock period times are identical,
It is Tclk.
For traditional adc circuit, with reference to Fig. 1 and Fig. 2, it is known that：
Vin*T0=Vref*count1*Tclk.(formula 2)
For the adc circuit in the embodiment of the present invention, with reference to Fig. 3 and Fig. 4, it is known that：
Vin*T0=Vref_1*count_1*Tclk+Vref_2*count_2*Tclk.(formula 3)
Convolution 2 and formula 3 understand：
Vref*count1*Tclk=Vref_1*count_1*Tclk+Vref_2*count_2*Tclk.(formula 4)
Wherein：Vref_1=N*Vref_2=N*Vref.(formula 5)
Convolution 4 and formula 5 understand：
Vref*count1*Tclk=N*Vref*count_1*Tclk+Vref*count_2*Tclk.
Further, count1=N*count_1+count_2.(formula 6)
Count1 is count value corresponding with the signal Vin to be sampled in traditional adc circuit,
(N*count_1+count_2) in adc circuit in the embodiment of the present invention with the signal Vin to be sampled
Corresponding count value, it is clear that two circuits are identical to the sampling precision of same signal Vin to be sampled.
On two sampling times of circuit, with reference to Fig. 4, the sampling time of traditional adc circuit is：
T_1=T0+T1=T0+t5+t6.(formula 7)
The sampling time of adc circuit is in the embodiment of the present invention：
T_2=T0+t3+t4.(formula 8)
Due to t3<T5, t4=t6, in conjunction with formula 7 and formula 8, it can be deduced that：
T_1>T_2.(formula 9)
I.e. the sampling time of adc circuit is less than the sampling time of traditional adc circuit in the embodiment of the present invention,
Can also be evident that in fig. 4.That is, on the premise of sampling precision is ensured, the embodiment of the present invention
The adc circuit for being provided improves the speed of A/D conversions.
Further, Vref_2 can also be reduced on the premise of A/D conversion speeds are ensured so that
|Vref_2|<| Vref | so that t4>T6, so that count1<(N*count_1+count_2), so as to improve
The precision of A/D conversions.
In other embodiments of the invention, the number of the reference signal may be arranged as three, four
Or more, so that multiple step integration is realized, to improve the speed of adc circuit A/D conversions.No matter
The number of the reference signal is how many, and the principle that the adc circuit carries out A/D conversions is identical, only
It is that the detailed process that A/D is changed is different, for example, when the number of the reference signal is three, A/D
The process of conversion will experience four-stage.When the number of the reference signal is four, the mistake of A/D conversions
Journey will experience five stages etc., will not be repeated here.
To sum up, in adc circuit provided in an embodiment of the present invention and its method for sampling, the input of integrator
With one first switching switch so that its input switches between signal to be sampled and multiple reference signals,
The integrator enters after positive integration is carried out to the signal to be sampled by the multiple reference signal
Row multistep reverse integral, improves the conversion speed and sampling precision of the adc circuit, improves sampled signal
Authenticity.
The preferred embodiments of the present invention are above are only, any restriction effect is not played to the present invention.Appoint
What person of ordinary skill in the field, is not departing from the range of technical scheme, to the present invention
The technical scheme and technology contents of exposure make any type of equivalent or modification etc. variation, belong to without departing from
The content of technical scheme, still falls within protection scope of the present invention.
Claims (15)
1. a kind of adc circuit, it is characterised in that including：Integrator, controller, counter and ratio
Compared with device；
The input of the integrator with one first switching switch so that its input signal to be sampled with
Switch between multiple reference signals, its output end is connected with the first input end of the comparator；
Second input of the comparator by one second switching switch in reference signal described at least one and
Switch between ground end signal, its output end is connected with the input of the counter；
The output end of the counter is connected with the input of controller；
The controller is used to control the first switching switch in the signal to be sampled and multiple reference signals
Between switch, and control it is described second switching switch reference signal described at least one and ground end signal between
Switching.
2. adc circuit as claimed in claim 1, it is characterised in that the second input of the comparator
The absolute value of signal value of the reference signal of connection is held less than the reference signal that the input of the integrator is connected
Signal value absolute value.
3. adc circuit as claimed in claim 2, it is characterised in that the reference signal is provided with M
Individual, M is the positive integer more than 1, and the reference signal of the wherein maximum absolute value of signal value is set to the first ginseng
Examine signal；
When the input of the integrator connects first reference signal, the second input of the comparator
Connect i-th reference signal, 1<i≤M；Then the controller control the first switching switch causes institute
The input for stating integrator connects i-th reference signal, while control the second switching switch causes institute
The second input for stating comparator connects j-th reference signal or ground end signal, wherein, 1<j≤M；
If the second input connection of the comparator is j-th reference signal, described first is controlled
Switching switch causes that the input of the integrator connects j-th reference signal, while control described second
The signal that second input of the switching switch adjustment comparator is connected, is so repeated up to the comparing
The second input connection ground end signal of device.
4. adc circuit as claimed in claim 2, it is characterised in that the letter of first reference signal
The absolute value of number value is N times of the minimum reference signal of absolute value of signal value, and N is the positive integer more than 1.
5. adc circuit as claimed in claim 1, it is characterised in that the multiple reference signal is negative
Signal, the signal to be sampled is positive signal.
6. adc circuit as claimed in claim 5, it is characterised in that the multiple reference signal is for just
Signal, the signal to be sampled is negative signal.
7. adc circuit as claimed in claim 1, it is characterised in that the signal to be sampled and reference
Signal is voltage signal.
8. a kind of method that use adc circuit as described in any one in claim 1-7 is sampled, it is special
Levy and be, including：
Sampled signal is treated to be integrated；
Step integration is carried out to multiple reference signals, counter is started counting up, until the output signal of comparator
Overturn, the counting of the counter is the digital acquisition signal of the signal to be sampled.
9. the adc circuit method of sampling as claimed in claim 8, it is characterised in that to described to be sampled
When signal is integrated, controller controls the first switching switch so that the input signal of integrator input is to treat
Sampled signal, the first input end of comparator is connected with the output end of the integrator, and the of the comparator
Two inputs are connected with ground terminal.
10. the adc circuit method of sampling as claimed in claim 8, it is characterised in that to multiple with reference to letter
During number carrying out step integration, the signal value of the reference signal of the second input connection of the comparator
Absolute value less than the integrator input connect reference signal signal value absolute value.
The 11. adc circuit method of samplings as claimed in claim 10, it is characterised in that referred to multiple
The step of signal carries out step integration includes：
The reference signal is provided with M, and M is the positive integer more than 1, and wherein the absolute value of signal value is most
Big reference signal is set to the first reference signal；
Step one：When the input of the integrator connects first reference signal, the of the comparator
Two inputs connect i-th reference signal, 1<i≤M；
Step 2：Controller control the first switching switch causes the input connection of the integrator
I-th reference signal, while control the second switching switch causes the second input of the comparator
J-th reference signal or ground end signal are connected, wherein, 1<j≤M；
If the second input of the comparator connects j-th reference signal, two are repeated the above steps,
Until the second input connection ground end signal of the comparator.
The 12. adc circuit method of samplings as claimed in claim 11, it is characterised in that first ginseng
The absolute value for examining the signal value of signal is N times of the minimum reference signal of absolute value of signal value, N be more than
1 positive integer.
The 13. adc circuit method of samplings as claimed in claim 8, it is characterised in that the multiple reference
Signal is negative signal, and the signal to be sampled is positive signal.
The 14. adc circuit method of samplings as claimed in claim 8, it is characterised in that the multiple reference
Signal is positive signal, and the signal to be sampled is negative signal.
The 15. adc circuit method of samplings as claimed in claim 8, it is characterised in that the letter to be sampled
Number and reference signal be voltage signal.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114384314A (en) * | 2021-12-31 | 2022-04-22 | 芯海科技（深圳）股份有限公司 | Signal detection circuit, method, integrated circuit, detection device and electronic equipment |
| WO2024000921A1 (en) * | 2022-06-29 | 2024-01-04 | 圣邦微电子（北京）股份有限公司 | Undervoltage detector and power supply system having said undervoltage detector |
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| CN116430213B (en) * | 2021-12-31 | 2024-06-25 | 芯海科技（深圳）股份有限公司 | Signal detection circuit, signal detection method, integrated circuit, detection device and electronic equipment |
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