CN106847852A - A kind of backside structure of electron multiplying charge coupled apparatus and preparation method thereof - Google Patents
A kind of backside structure of electron multiplying charge coupled apparatus and preparation method thereof Download PDFInfo
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Abstract
Backside structure the present invention relates to electron multiplying charge coupled apparatus and preparation method thereof, backside structure includes EMCCD chips, electrode draw-out area, photosensitive area, storage gain region, ion implanted region, anti-reflection film and metal screen layer, electrode draw-out area is arranged at EMCCD chip backs both sides, pressure welding figure is interval with electrode draw-out area, the photosensitive area of EMCCD chip backs and storage gain zone position are between electrode draw-out area, there is the ion implanted region formed by low energy ion beam implantation inside photosensitive area and storage gain region, in the anti-reflection film on photosensitive area surface, standing wave effect can be reduced, reduce reflection light；In the metal screen layer on storage gain region surface, it is prevented from incident light and is transmitted on storage gain region surface.The present invention can be used for improving the photoelectric transformation efficiency of electron multiplying charge coupled apparatus, while element manufacturing cost can also be reduced, and improve the yield rate of product.
Description
Technical field
The present invention relates to a kind of backside structure of electron multiplying charge coupled apparatus and preparation method thereof, belong to Charged Couple
Device arts.
Background technology
Electron multiplying charge coupled apparatus（EMCCD）By development for many years, oneself is through being widely used in image scanning, work
The numerous areas such as industry non-cpntact measurement, Aero-Space, astronomical remote sensing, military affairs, medical science.Electron multiplying charge coupled apparatus is a kind of
Large-scale integrated photoelectric device, with opto-electronic conversion, the function such as electric charge storage, electric charge transfer, charge measurement is also equipped with highly sensitive
Degree, high s/n ratio, lofty tone modulation trnasfer function and the technical characterstic such as all solid state, no matter in traditional daytime with digitized video industry
Technology upgrading transformation aspect, such as X-ray digital imaging system, various frame frequency cameras high, or in the exploitation side of lll night vision
Face, such as low-light level television, industrial monitoring and survey of deep space, and new industry aspect, such as smart city, internet+, make
For the electron multiplying charge coupled apparatus of the reliable Low Light Level Imaging System core devices of general round the clock, light weight all serve it is inadvisable
The crucial effect in generation.
In recent years because the market scale of industrial automation and digitized video is expanded rapidly, the market demand of fainter light detector
Also sharp increase, the manufacture craft for having benefited from electronic device is constantly upgraded, the backside structure of electron multiplying charge coupled apparatus
Design and fabrication reaches its maturity so that back side illuminaton electron multiplying charge coupled apparatus be increasingly widely used in production and living with
It is that the digitized video collection of core devices and processing system exist using back side illuminaton electron multiplying charge coupled apparatus in work
The fields such as consumer electronics, medical treatment, industrial monitoring, Aero-Space, military affairs have and largely use, such as the monitoring in subway transportation management
Camera, video conference, video camera etc..However, the backside structure research of current country's electron multiplying charge coupled apparatus is also
Development is in, unrealized cost and technique reach suitable balance.The backside structure preparation method of current main flow is in grinding and polishing
When need multistep adjusting process parameter, not only cause that process efficiency is low to be also easily caused chip rupture, it is necessary to customize special fixation
Fixture, it is relatively costly, and also existing back side manufacturing technology generally existing litho pattern is single, and Graph Control precision is more rough,
The problems such as applicable device solution is less, is not suitable for the making of the backside structure of electron multiplying charge coupled apparatus.
The content of the invention
The present invention provides a kind of backside structure of electron multiplying charge coupled apparatus and preparation method thereof, to overcome existing skill
Drawbacks described above present in art, by using the technology that suitable grinding and polishing process and multiple choices lithographic method are combined, very
Realize well ultra-thin and uniform, electron multiplying charge coupled apparatus back side thickness is thinning, and, thinning speed is fast, and defect is less,
The structure of electron multiplying charge coupled apparatus backside structure pattern is realized using the semiconductor lithography process of multistep standard, was both reduced
The production cost of device, can guarantee that the superperformance of device again, there is a preferable economic benefit.
The technical scheme of electron multiplying charge coupled apparatus backside structure and preparation method thereof is by the grinding and polishing of the device back side
The processing steps such as the photoetching corrosion of burn into low energy p-type ion implanting, laser annealing, multilayer film ise and electrode draw-out area
Realize, after the completion of Facad structure, reduction processing is carried out to the device back side with reference to various etching process using grinding and polishing, then to flat
The back surfaces of smoothization carry out low energy p-type ion implanting, and short annealing is carried out using laser annealing after the completion of injection, formed from
Sub- injection region, next deposits anti-reflection film and metal screen layer, and carry out figure photoetching completion photosensitive area and storage gain region table
Face pattern, electrode draw-out area is produced finally by the photoetching corrosion to multiple material, is fabricated to complete electron multiplying charge
Coupled apparatus backside structure.
A kind of backside structure of electron multiplying charge coupled apparatus, it is characterised in that：Set at the back side of EMCCD chips (1)
There are electrode draw-out area (2), photosensitive area (3), storage gain region (4), ion implanted region (5), anti-reflection film (6) and metal screen layer
(7), electrode draw-out area (2), photosensitive area (3), gain region (4) are adjacent is formed in the back side silicon body of EMCCD chips (1) for storage
Portion, is internally formed ion implanted region (5), in photosensitive area by low energy ion beam implantation in photosensitive area (3) and storage gain region (4)
(3) surface is covered with anti-reflection film (6), and storage gain region (4) surface is provided with anti-reflection film (6) and metal screen layer (7).
Wherein, the electron multiplying charge Coupled Device chip backplate draw-out area, photosensitive area and the increasing above it
Permeable membrane, storage gain region and its anti-reflection film above and metal screen layer are adjacent successively to form three-level step appearance.
Electron multiplying charge Coupled Device chip back side storage gain region and its anti-reflection film above and metal screen layer,
Electrode draw-out area is adjacent successively to form two stage steps pattern.
The first order step that the second level step that photosensitive area (3) and anti-reflection film (6) are formed is formed with electrode draw-out area (2)
Between side wall and first order ledge surface angle α at 90 °~150 °, storage gain region (4) metal screen layer (7) shape above
Into the second level step that is formed of third level step and photosensitive area (3) and anti-reflection film (6) between side wall and second level step table
Face angle β is at 90 °~150 °.
The second level step and electrode that the anti-reflection film (6) of storage gain region (4) and top, metal screen layer (7) are formed draw
The side wall gone out between the first order step of area (2) formation is with second level ledge surface angle γ at 90~150 °.
Electrode draw-out area (2) thickness h 0 is at 0.5~10 μm.
The second level step that the first order step that electrode draw-out area (2) is formed is formed with photosensitive area (3) and anti-reflection film (6)
Between height of side wall h1 at 10~30 μm.
Second level step and store the metal screen layer above gain region (4) that photosensitive area (3) and anti-reflection film (6) are formed
(7) the height of side wall h2 between the third level step for being formed is at 0.5~5 μm.
The depth d0 of the ion implanted region in the backside structure is at 0.1~2 μm.
The thickness d 1 of the anti-reflection film in the backside structure is at 0.01~1 μm
The thickness d 2 of the metal screen layer in the backside structure is at 0.5~5 μm.
The preparation method of described EMCCD chip back structures is after EMCCD chip front side techniques are completed, to press
Following steps are carried out:
1) EMCCD chips (1) back side is combined by mechanical lapping, wet etching and CMP process makes the back side
It is thinned to 10~50 μm；
2) at thinning EMCCD chips (1) back side by low energy ion beam implantation, implanting p-type ion, in EMCCD chips
Back side silicon body is internally formed ion implanted region (5)；
3) laser annealing treatment is carried out to ion implanted region (5), lattice damage is repaired by short annealing；
4) at EMCCD chips (1) back by depositing one layer of anti-reflection film (6) of evaporation；
5) sputtering deposit layer of metal screen layer (7) is used above in anti-reflection film (6)；
6) photoetching corrosion metal screen layer (7), realize the transfer of mask pattern, and etching cutoff layer is anti-reflection film (6) layer, is formed
Store the metal screen layer (7) on gain region (4) surface；
7) using photoetching corrosion anti-reflection film (6), figure is set up on the surface of photosensitive area (3), etching cutoff layer is ion implanted region
(5) anti-reflection film (6) layer on photosensitive area (3) surface, is formed；
8) using sense coupling and with reference to wet etching and/or dry etching, in EMCCD chips (1) back of the body
Produce electrode draw-out area (2) in portion.
The present invention uses thinning grinding and polishing, wet etching, dry etching, chemically mechanical polishing etc. many in EMCCD chip backs
Step process forms step appearance structure, and the side wall of step is not vertical, and side wall is with the horizontal certain angle, present invention application
Multi-step process method can effectively control thinning uniformity, it is possible to achieve back side silicon body is uniformly and effectively removed, and reduce
The stress that EMCCD chip internals are produced, is not susceptible to chip rupture, and can reduce the damage of back surfaces.This hair
It is bright by ion implanted region, the formation built in field inside photosensitive area and storage gain region, the electrical potential difference of built in field drives
Due to the light induced electron that incident light back surface incident silicon body is produced so that light induced electron is effectively transferred to the integration of EMCCD devices
Potential well, is conducive to improving the photoresponse time of EMCCD devices, it is ensured that device photoresponse time and device free-carrier-absorptio
Better trade-off between rate.
The invention provides a kind of EMCCD chip backs structure and preparation method thereof, in EMCCD chip front side structure fabrications
After the completion of, with Mechanical polishing, by selecting suitable grinding and polishing material, grinding and polishing pad and grinding and polishing speed by EMCCD cores during grinding and polishing
Piece is thinned to target thickness, and target thickness setting is 20 μm, and such target thickness is thinned to using Mechanical polishing, can be reduced
The fragmentation probability of EMCCD chips, then by using low heating corrosive liquid at a slow speed, and coordinates high-accuracy temperature of the prior art
Control instrument carries out corrosion rate and the controllable wet etching of corrosion precision, and this caustic solution not only has selectivity, additionally it is possible to
Increase EMCCD chips back corrosion accuracy, and this caustic solution can also as far as possible reduce corrosive liquid EMCCD chips back
The pollution on surface.Then, inductive couple plasma ICP dry etching technologies are continuing with to perform etching EMCCD chip backs
Operation, due to ICP etchings with controllability is good and uniformity consistency is high the features such as, can realize to the realization of EMCCD chips compared with
Good controllable et ch profiles and clean etching, following applied chemistry mechanically polish CMP, by select polishing fluid particle size,
It is fabulous that polishing flow velocity, the pH value of polishing fluid and the condition such as pad material and polishing pad pressure obtain EMCCD chip backs
Flatness, obtain the EMCCD chips back smooth surface of high-flatness, and reduce EMCCD chips back surfaces damage.This
Invention uses ion implanting in EMCCD chip backs, can not only effectively reduce this capture state defect in surface and photoproduction is carried
Flow son generation compound action, can also by due to ion implanting effect produced in the silicon body at EMCCD chips back it is built-in
Electrical potential difference improves the signal collection efficiency of EMCCD chips.The present invention is reduced in EMCCD chip backs photosensitive area evaporation anti-reflection film
Due to the optical energy loss of EMCCD chips back surfaces reflection, the photoelectric efficiency of device is improve.The present invention is subtracted by using grinding and polishing
The multistep manufacture of semiconductor method such as thin, semiconductor etching, chemically mechanical polishing, ion implanting and photoetching process realizes EMCCD
Chip back structure and its making.Present invention process is controllable, processing step is succinct, can not only be effectively improved and realize EMCCD chips
The low problem of back side pattern process efficiency, moreover it is possible to greatly promote the opto-electronic conversion performance of EMCCD chips, the present invention adds with the back side
Work high precision, the characteristics of support various device back side graphics-optimized, the present invention can be greatly reduced EMCCD chip back structures
Cost of manufacture, realizes that manufacturing cost reaches optimum balance with properties of product, and the present invention is for promoting China's fainter light detector autonomous
Development, has important practical significance.
Brief description of the drawings
Fig. 1 is structural representation of the invention.
Fig. 2 is that ion implanted region forms diagram.
Fig. 3 is anti-reflection film and metal screen layer formation figure.
Fig. 4 is that photosensitive area and storage gain region form schematic diagram.
Fig. 5 forms the schematic diagram of electrode draw-out area.
Specific embodiment
Embodiments of the invention are described in further detail below in conjunction with the accompanying drawings.
As shown in Fig. 1 the structural representation of present invention：A kind of EMCCD chip backs structure include EMCCD chips 1,
The electrode draw-out area 2 of EMCCD chips 1, photosensitive area 3, storage gain region 4, ion implanted region 5, anti-reflection film 6 and metallic shield
Layer 7.Electrode draw-out area 2, photosensitive area 3, gain region 4 is adjacent is formed at portion in the back side silicon body of EMCCD chips 1 for storage, passes through
Low energy ion beam implantation is internally formed ion implanted region 5 in photosensitive area 3 and storage gain region 4, and anti-reflection film is covered with the surface of photosensitive area 3
6, there are anti-reflection film 6 and metal screen layer 7 in the storage surface of gain region 4.
Electrode draw-out area 2 is arranged at the back side both sides of EMCCD chips 1, and pressure welding figure is interval with electrode draw-out area 2, pressure
Weldering figure can be used to be bonded interconnection with the mounting structure of EMCCD chips 1, and the photosensitive area 3 at the back side of EMCCD chips 1 and storage increase
The position of beneficial area 4 has what is formed by low energy ion beam implantation between electrode draw-out area 2 inside photosensitive area 3 and storage gain region 4
Ion implanted region 5, is by cleaning, the anti-reflection film for bakeing, sputtering the formation of the semiconductor processing methods such as evaporation on the surface of photosensitive area 3
6, the anti-reflection film 6 on the surface of photosensitive area 3 can reduce standing wave effect and reduce the light that incident light reflects on the surface of photosensitive area 3, deposit
The storage surface of gain region 4 is the metal screen layer 7 made by the semiconductor technology method of cleaning, drying, sputtering, stores gain region
The metal screen layer 7 on 4 surfaces can effectively prevent what incident light from transmiting on the storage surface of gain region 4.
Electrode draw-out area 2, photosensitive area 3 and anti-reflection film 6 in Fig. 1 schematic structural views of the invention on the back side of EMCCD chips 1
, storage gain region 4 and metal screen layer 7 formed three-level step appearance, wherein, electrode draw-out area 2 is on the back side of EMCCD chips 1
First order step is formed, photosensitive area 3 and anti-reflection film 6 form second level step, metal screen layer 7 on the back side of EMCCD chips 1
Third level step is formed on the back side of EMCCD chips 1.
Electrode draw-out area 2, storage gain region 4, anti-reflection film in Fig. 1 schematic structural views of the invention on the back side of EMCCD chips 1
6 and metal screen layer 7 formed two stage steps pattern, wherein, electrode draw-out area 2 forms the first order on the back side of EMCCD chips 1
Step, storage gain region 4 and anti-reflection film 6 and metal screen layer 7 form second level step on the back side of EMCCD chips 1.
Side wall in Fig. 1 schematic structural views of the invention between the first order step and second level step of three-level step appearance with
The angle of first order ledge surface is α, the folder of the side wall between first order step and second level step and second level ledge surface
Angle is β., at 90~150 °, angle β is at 90~150 ° for angle α.
Side wall in Fig. 1 schematic structural views of the invention between the first order step and second level step of two stage steps pattern with
The angle of second level ledge surface is γ.Angle γ is at 90~150 °.
The thickness of electrode draw-out area 2 is h0 in Fig. 1 schematic structural views of the invention.Thickness h 0 is at 0.5~10 μm.
Side wall in Fig. 1 schematic structural views of the invention between the first order step and second level step of three-level step appearance is high
Degree is h1.Height of side wall h1 is at 10~30 μm.
Side wall in Fig. 1 schematic structural views of the invention between the second level step and third level step of three-level step appearance is high
Degree is h2.Height of side wall h2 is at 0.5~5 μm.
The depth of Fig. 1 schematic structural view of the invention intermediate ions injection region 5 is d0.Depth d0 is at 0.1~2 μm.
The thickness of anti-reflection film 6 is d1 in Fig. 1 schematic structural views of the invention.Thickness d 1 is at 0.01~1 μm.
The thickness of metal screen layer 7 is d2 in Fig. 1 schematic structural views of the invention.Thickness d 2 is at 0.5~5 μm.
Fig. 2 is that ion implanted region forms diagram, and low energy p-type ion implanting is carried out at the thinning back side of EMCCD chips 1,
The back side silicon body of EMCCD chips 1 is internally formed ion implanted region 5, ion implanted region 5 can reduce back surfaces lattice damage and
Defect, and ion implanted region 5 can also form the built in field driving effective transfer of light induced electron generation.
Fig. 3 is anti-reflection film and metal screen layer formation figure, at the thinning back side of EMCCD chips 7 by sputtering, evaporation etc. half
Conductor processing method forms anti-reflection film 6 and metal screen layer 7, and anti-reflection film 6 can reduce incident light in the back table of EMCCD chips 7
The reflex that face occurs, metal screen layer 7 can effectively prevent incident light to be transmitted into ion implanted region 5.
Fig. 4 is that photosensitive area and storage gain region form schematic diagram, to the anti-reflection film 6 and metal of the deposit of the back side of EMCCD chips 1
Screen layer 7 uses semiconductor lithography process, and mask plate patterns to photoresist above anti-reflection film 6 and metal screen layer 7 are shifted first
Layer is exposed development, then by etching transition diagram 6 and metal screen layer 7 from photoresist layer to anti-reflection film, by feature
Figure forms photosensitive area 3 and storage gain region 4 in ion implanted region 5.
Fig. 5 forms the schematic diagram of electrode draw-out area, and sense coupling is used simultaneously at the back side of EMCCD chips 1
With reference to other dry etchings and wet-etching technology, the multi-level material in back of etching EMCCD chips 1 is produced according to pattern image
The electrode draw-out area 2 at EMCCD chips back.
The preparation method of EMCCD chip back structures is after EMCCD chip front side techniques are completed, by following tool
The detailed step of body is carried out:
1) back side of EMCCD chips 1 is combined by techniques such as mechanical lapping, wet etching and chemically mechanical polishings makes the back side
It is thinned to 10~50 μm；
2) at the thinning back side of EMCCD chips 1 by low energy ion beam implantation, implanting p-type ion, implantation dosage is 1E14
~5E15, Implantation Energy is 0.1KeV~10KeV, forms ion implanted regions 5 of the depth d0 at 0.1~2 μm；
3) ion implanted region 5 at the back side of EMCCD chips 1 carries out laser annealing treatment, laser annealing use operation wavelength for
The laser beam that 100nm~500nm, energy density are 0.1J/cm2~20J/cm2, pulse width is 50ns~500ns；
4) one layer of anti-reflection film 6, anti-reflection film 6 are deposited with by depositing on the surface of ion implanted region 5 at the thinning back of EMCCD chips 1
Thickness degree is 0.01~1 μm；
5) metal screen layer 7 at the back of photoetching corrosion EMCCD chips 1, transfer mask pattern to the back of EMCCD chips 1, etching
Cutoff layer is antireflective coating 6, forms the metal screen layer 7 on the storage surface of gain region 4, and the thickness of metal screen layer 7 is 0.5~5 μ
m；
6) using the anti-reflection film 6 of the back evaporation of photoetching corrosion EMCCD chips 1, figure is set up on the surface of photosensitive area 3, etching is cut
Only layer is the ion implanted region 5 at EMCCD chips back, forms 6 layers of the anti-reflection film on the surface of photosensitive area 3, and the thickness that 6 layers of anti-reflection film is
0.01~1 μm；
7）Using sense coupling and with reference to wet etching and dry etching, made at the back of EMCCD chips 1
Electrode draw-out area 2.
The present invention is carried on the back by manufacturing method thereofs such as Mechanical polishing, semiconductor etching, chemically mechanical polishings to EMCCD chips (1)
Portion's thickness has good control ability, and back side machining accuracy is high, and the litho pattern to the back side is without particular limitation, can realize various
Back side graphic scheme, it is simple and reliable, invention also reduces production cost, shorten the research and development of products cycle.
The above, preferably specific embodiment only of the invention, but the invention is not restricted to above-mentioned one exemplary embodiment
Details, and without departing from the spirit or essential characteristics of the present invention, any technology people for being familiar with the art
Member the invention discloses technical scope in, the change or replacement that can be readily occurred in can in other specific forms realize this
Invention, should all be included within the scope of the present invention.Which point therefore, no matter from the point of view of, embodiment all should be regarded as
It is exemplary, and be nonrestrictive, the scope of the present invention is limited by appended claims rather than described above, therefore purport
Included in the present invention by all changes fallen in the implication and scope of the equivalency of claim.Right should not be wanted
Any reference asked is considered as the claim involved by limitation.
Moreover, it will be appreciated that although the present invention is been described by according to implementation method, not each implementation method is only included
One independent technical scheme, this narrating mode is only that for clarity, those skilled in the art should be by above-mentioned legend
Illustrate as an entirety, the technical scheme in each embodiment can also be through appropriately combined, and forming those skilled in the art can be with
The other embodiment of understanding.
Claims (10)
1. a kind of backside structure of electron multiplying charge coupled apparatus, it is characterised in that：It is provided with the back side of EMCCD chips (1)
Electrode draw-out area (2), photosensitive area (3), storage gain region (4), ion implanted region (5), anti-reflection film (6) and metal screen layer (7),
Electrode draw-out area (2), photosensitive area (3), gain region (4) are adjacent is formed at portion in the back side silicon body of EMCCD chips (1) for storage, lead to
Cross low energy ion beam implantation and be internally formed ion implanted region (5) in photosensitive area (3) and storage gain region (4), on photosensitive area (3) surface
Anti-reflection film (6) is covered with, storage gain region (4) surface is provided with anti-reflection film (6) and metal screen layer (7).
2. the backside structure of electron multiplying charge coupled apparatus according to claim 1, it is characterised in that:EMCCD chips
(1) three-level is formed when electrode draw-out area (2) on the back side, photosensitive area (3), anti-reflection film (6) and metal screen layer (7) adjacent successively
Step appearance, wherein, electrode draw-out area (2) form first order step on EMCCD chips (1) back side, photosensitive area (3) and anti-reflection
Film (6) forms second level step on EMCCD chips (1) back side, and metal screen layer (7) is formed on EMCCD chips (1) back side
Third level step.
3. the backside structure of electron multiplying charge coupled apparatus according to claim 1, it is characterised in that:EMCCD chips
(1) formed when electrode draw-out area (2) on the back side, storage gain region (4), anti-reflection film (6) and metal screen layer (7) adjacent successively
Two stage steps pattern, wherein, electrode draw-out area (2) form first order step on EMCCD chips (1) back side, store gain region
(4), anti-reflection film (6) and metal screen layer (7) form second level step on EMCCD chips (1) back side.
4. the backside structure of electron multiplying charge coupled apparatus according to claim 1 and 2, it is characterised in that:Photosensitive area
(3) side wall and between the first order step of second level step and electrode draw-out area (2) formation that is formed of anti-reflection film (6) and the
One-level ledge surface angle α stores the third level step that gain region (4) metal screen layer (7) above is formed at 90 °~150 °
And the side wall between the second level step that photosensitive area (3) and anti-reflection film (6) are formed and second level ledge surface angle β 90 °~
150°。
5. the backside structure of the electron multiplying charge coupled apparatus according to claim 1 or 3, it is characterised in that:Storage increases
What the second level step and electrode draw-out area (2) that the anti-reflection film (6) of beneficial area (4) and top, metal screen layer (7) are formed were formed
Side wall between first order step is with second level ledge surface angle γ at 90 °~150 °.
6. the backside structure of electron multiplying charge coupled apparatus according to claim 1 and 2, it is characterised in that:Electrode draws
Go out area (2) thickness h 0 in 0.5~10 μm, first order step and photosensitive area (3) and anti-reflection film (6) that electrode draw-out area (2) are formed
Height of side wall h1 between the second level step of formation is in 10~30 μm, the second level that photosensitive area (3) and anti-reflection film (6) are formed
Height of side wall h2 between the third level step that metal screen layer (7) above step and storage gain region (4) is formed 0.5~
5μm。
7. the backside structure of electron multiplying charge coupled apparatus according to claim 1 or claim 2, it is characterised in that:It is described from
The depth d0 of sub- injection region (5) is at 0.1~2 μm.
8. the backside structure of electron multiplying charge coupled apparatus according to claim 1 or claim 2, it is characterised in that:Described increasing
The thickness d 1 of permeable membrane (6) is at 0.01~1 μm.
9. the backside structure of electron multiplying charge coupled apparatus according to claim 1 or claim 2, it is characterised in that:Described
The thickness d 2 of metal screen layer (7) is at 0.5~5 μm.
10. a kind of preparation method of electron multiplying charge coupled apparatus backside structure, it is characterised in that：By EMCCD chip front sides
After technique is finished, the making of backside structure is carried out according to the following steps：
1）EMCCD chips (1) back side is combined by mechanical lapping, wet etching and CMP process subtracts the back side
It is as thin as 10~50 μm；
2）At thinning EMCCD chips (1) back side by low energy ion beam implantation, implanting p-type ion, in the EMCCD chips back of the body
Face silicon body is internally formed ion implanted region (5)；
3）Laser annealing treatment is carried out to ion implanted region (5)；
4）At EMCCD chips (1) back by depositing one layer of anti-reflection film (6) of evaporation；
5）Sputtering deposit layer of metal screen layer (7) is used above in anti-reflection film (6)；
6）Photoetching corrosion metal screen layer (7), realizes the transfer of mask pattern, and etching cutoff layer is anti-reflection film (6) layer, and formation is deposited
Storage gain 6）The metal screen layer (7) on area (4) surface；
7）Using photoetching corrosion anti-reflection film (6), figure is set up on the surface of photosensitive area (3), etching cutoff layer is ion implanted region
(5) anti-reflection film (6) layer on photosensitive area (3) surface, is formed；
8）Using sense coupling and with reference to wet etching and/or dry etching, in EMCCD chips (1) back of the body
Produce electrode draw-out area (2) in portion.
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| CN113113440A (en) * | 2021-04-13 | 2021-07-13 | 中国电子科技集团公司第四十四研究所 | EMCCD structure of anti-radiation reinforcing grid medium |
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