CN106847790A - The interconnection structure and its manufacture method of a kind of integrated CNT and Graphene - Google Patents
The interconnection structure and its manufacture method of a kind of integrated CNT and Graphene Download PDFInfo
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- CN106847790A CN106847790A CN201710036094.1A CN201710036094A CN106847790A CN 106847790 A CN106847790 A CN 106847790A CN 201710036094 A CN201710036094 A CN 201710036094A CN 106847790 A CN106847790 A CN 106847790A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53276—Conductive materials containing carbon, e.g. fullerenes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
- H01L2221/1094—Conducting structures comprising nanotubes or nanowires
Abstract
The invention discloses a kind of interconnection structure and its manufacture method, the structure includes at least one interconnection structure, the interconnection structure includes connected medium layer, the lower surface insertion of connected medium layer is provided with Graphene interconnection layer, and the CNT through-hole interconnection for the upper surface of connected medium layer to be connected with Graphene interconnection layer is provided with connected medium layer.The method includes：Graphene layer is prepared on connected medium layer in substrate or lower section interconnection structure；Graphene layer is constituted into Graphene interconnection layer；Catalyst is deposited on Graphene interconnection layer；Connected medium layer is deposited on connected medium layer in substrate or lower section interconnection structure；Through hole is prepared in connected medium layer；Carbon nano pipe array is grown on Graphene interconnection layer；Carbon nano pipe array is formed into CNT through-hole interconnection.Interconnection structure of the invention and manufacture method can solve the problem that the problems such as traditional resistor is high, interconnection structure current carrying capacity is limited.The composite can be widely applied to the manufacture field of semiconductor devices.
Description
Technical field
CNT is used as vertical mutual the present invention relates to the manufacturing technology field of semiconductor devices, more particularly to one kind
Connect the interconnection structure and its manufacture method of material, Graphene as horizontal interconnection material.
Background technology
The lasting diminution of integrated circuit technology characteristic size so that the device count every on lsi unit area
Individual new technology node will be doubled.And the diminution of transistor feature size not only increases the integrated level of chip, reduce
The operating voltage and power consumption of transistor, and also improve the working frequency of transistor.But at the same time, due to metal grain
The electron scattering effect on boundary and surface increases, and the resistance of the interconnecting metal layer based on the material such as copper and tungsten is with feature chi
Very little diminution increases sharply, and then causes the delay of electric signal transmission to increase, and limits the overall performance of integrated circuit.The opposing party
Face, through-hole interconnection and ground floor interconnection line with transistor directly contact can bear larger current density, in long-term work
In be susceptible to caused by electromigration fracture failure.Accordingly, it would be desirable to further improve the property of integrated circuit interconnection structure
Can, increased and the problems such as fracture failure with solving the resistance that present interconnections material and structure faced.
Currently in order to solve the problems, such as it is above-mentioned, propose in the prior art it is a kind of based on formed on metal interconnecting layer carbon-coating and
The interconnection structure of CNT through hole.But due to the application of metal level, the overall current ability to bear of the interconnection structure is subject to
Limitation, therefore it cannot fundamentally solve the problems, such as that contact resistance is big, cannot particularly to improve integrated circuit required
High current bearing capacity.In addition, for Graphene, although it is a kind of c-based nanomaterial of two dimension, is carried with high current
The advantages of ability, high carrier mobility and high thermal conductivity, but, when it comes and metal structure as horizontal interconnection material
When interconnection material is used in conjunction with, similarly with the problem that contact resistance is big, and for the conductance of single-layer graphene, it is difficult to
Compared with metal material, and the realization of its integrated technique has suitable difficulty, therefore, using Graphene as interconnection material and now
Some metal interconnection structures carry out integrated, and big and integrated carrying current limited the problem of contact resistance is faced in this same meet.
The content of the invention
In order to solve the above-mentioned technical problem, it is an object of the invention to provide the interconnection of a kind of integrated CNT and Graphene
Structure.
It is a further object of the present invention to provide a kind of integrated CNT and the interconnection structure manufacture method of Graphene.
The technical solution adopted in the present invention is：A kind of interconnection structure of integrated CNT and Graphene, including at least
One interconnection structure, the interconnection structure includes connected medium layer, and the lower surface insertion of the connected medium layer is provided with graphite
Alkene interconnection layer, is provided with the carbon for the upper surface of connected medium layer to be connected with Graphene interconnection layer in the connected medium layer
Nanotube through-hole interconnection.
Further, the number of the interconnection structure is at least two, and at least two interconnection structure is from bottom to up successively
Superposition is set, wherein, in two neighbouring interconnection structures, it is arranged below the CNT through-hole interconnection in interconnection structure
For the Graphene interconnection layer that will be arranged below in interconnection structure and the Graphene interconnection layer being disposed in interconnection structure
Connection.
Further, the Graphene interconnection layer is multi-layer graphene.
Further, the thickness of the Graphene interconnection layer is more than or equal to 3nm.
Further, the connected medium layer is fabricated by using the dielectric material of low-k.
Another technical scheme of the present invention is：A kind of interconnection structure manufacturer of integrated CNT and Graphene
Method, the step included by the method has：
Graphene layer is prepared on S1, the connected medium layer in substrate or lower section interconnection structure；
S2, on graphene layer prepare have patterned Graphene interconnection line or graphene-channel so that constitute Graphene interconnection
Layer；
S3, on the through hole link position of Graphene interconnection layer deposit catalyst；
Connected medium layer is deposited on S4, the connected medium layer in substrate or lower section interconnection structure, the Graphene in step S3 is made
Interconnection layer insertion is arranged on the lower surface of connected medium layer；
S5, connected medium layer in prepare through hole, the through hole is correspondingly arranged on the through hole link position of Graphene interconnection layer；
S6, based on the catalyst for being deposited, grow carbon nano pipe array on the through hole link position of Graphene interconnection layer；
S7, Filled Dielectrics are carried out to carbon nano pipe array after carry out CMP process so that formed CNT interconnection
Through hole, wherein, the upper surface that the CNT through-hole interconnection is used for connected medium layer connects with Graphene interconnection layer.
Further, described in the step S1 the step for preparing graphene layer on substrate, it is specially：
The method and the method for metallic film thermal annealing shifted using chemical vapor deposition synthesizing graphite alkene, so as in lining
Graphene layer is prepared on bottom.
Further, described in the step S1 in the interconnection structure of lower section connected medium layer on prepare graphene layer this
One step, it is specially：
Using chemical gas-phase deposition method and metallic film thermal annealing process, so as to the connected medium layer in the interconnection structure of lower section
On prepare graphene layer.
Further, carbon nano pipe array is grown on the through hole link position of Graphene interconnection layer described in the step S6
The step for, it is specially：
Using chemical gas-phase deposition method, so as to grow carbon nano pipe array on the through hole link position of Graphene interconnection layer.
Further, the catalyst is at least one of Fe, Ni, Co, FeAl, NiAl.
The beneficial effects of the invention are as follows：Interconnection structure proposed by the invention be one kind by Graphene as horizontal interconnection layers
And by CNT as perpendicular interconnection layer interconnection structure, it can make full use of the height electricity that CNT and Graphene have
Stream bearing capacity, the advantage of high conductivity and high thermal conductivity, solve institute in the prior art it is unavoidable because of CNT or
Contacted between grapheme material and interconnection materials and cause the problem that resistance is high, interconnection structure current carrying capacity is limited.
Another beneficial effect of the invention is：By using interconnection structure manufacture method of the invention, can manufacture and draw
It is a kind of by Graphene as horizontal interconnection layers and by CNT as perpendicular interconnection layer interconnection structure, it can make full use of carbon
The advantage of high current bearing capacity, high conductivity and high thermal conductivity that nanotube and Graphene have, solves in the prior art
Institute is unavoidable to cause that resistance is high, interconnection structure because being contacted between CNT or grapheme material and interconnection materials
The limited problem of current carrying capacity；And because manufacture method of the invention is directly to prepare carbon on Graphene interconnection layer to receive
Metal catalyst materials are completely eliminated in mitron, therefore the interconnection structure that finally gives of its manufacturer's decree for being used, this
It is high that sample resistance occurs can avoiding junction because there is carbon-based material and the contact of metal material；Simultaneously for carbon
Nano-tube array, its manufacture method for being used can be formed directly in the close contact of CNT and Graphene, eliminate metal
Influence of the presence to interface.Therefore as can be seen here, integrated CNT proposed by the invention and the interconnection structure of Graphene
Manufacture method, it realizes two kinds of seamless connections of carbon-based material, enhances bond strength of two kinds of materials in contact position, can be with
Obtain the interconnection structure of high conductivity and high thermal conductivity.
Brief description of the drawings
Fig. 1 is a specific embodiment structural representation of the interconnection structure of a kind of integrated CNT of the present invention and Graphene
Figure；
Fig. 2 is the another specific embodiment structural representation of the interconnection structure of a kind of integrated CNT of the present invention and Graphene；
Fig. 3 is that shown structural representation after the first graphene layer is prepared on substrate；
Fig. 4 is that the first graphene layer is prepared into shown structural representation after the first Graphene interconnection layer；
Fig. 5 is shown after deposit catalyst structural representation on the first Graphene interconnection layer；
Fig. 6 is that shown structural representation after the first connected medium layer is prepared on substrate；
Fig. 7 is structural representation shown after preparing through hole in the first connected medium layer；
Fig. 8 is structural representation shown after grown carbon nano pipe array on the through hole link position of the first Graphene interconnection layer
Figure；
Fig. 9 is to prepare shown structural representation after the first CNT through-hole interconnection；
Figure 10 is structural representation shown after preparing the second graphene layer on the first connected medium layer；
Figure 11 is that the second graphene layer is prepared into shown structural representation after the second Graphene interconnection layer；
Figure 12 is the transmission electron microscope photo schematic diagram that multi-layer graphene is prepared on substrate；
Figure 13 is that shown surface scan Electronic Speculum schematic diagram after catalyst is prepared on multi-layer graphene；
Figure 14 is shown after growth CNT cross-sectional scans electromicroscopic photograph schematic diagram on multi-layer graphene.
Specific embodiment
In order to solve tradition because between CNT or grapheme material and interconnection materials contact cause resistance it is high,
The limited problem of interconnection structure current carrying capacity, the present invention proposes the interconnection structure of a kind of integrated CNT and Graphene,
It includes at least one interconnection structure, and the interconnection structure includes connected medium layer, the lower surface insertion of the connected medium layer
Graphene interconnection layer is provided with, is provided with the connected medium layer for the upper surface of connected medium layer and Graphene to be interconnected
The upper surface of the CNT through-hole interconnection of layer connection, i.e., described CNT through-hole interconnection, its one end and connected medium layer
Connection, the other end is connected with the through hole link position of Graphene interconnection layer.
For at least one interconnection structure of the invention, it is in use, its upper surface and top for being provided in substrate
Between the lower surface of interconnection layer, and closest to the CNT through-hole interconnection in the interconnection structure of top interconnection layer, it is then used for
Graphene interconnection layer in the interconnection structure is connected with top interconnection layer；
When the number of interconnection structure is one, it is mutual with top that the connected medium layer in the interconnection structure is arranged on substrate top surface
Even between layer lower surface, i.e., the Graphene that the upper surface of the interconnection structure is set in top interconnection layer, and the interconnection structure is mutual
Company's layer is arranged on the upper surface of substrate and is embedded in the lower surface for being arranged on connected medium layer, and the CNT in the interconnection structure
Through-hole interconnection, it is arranged in connected medium layer, and its one end is connected with the through hole link position of top interconnection layer, the other end
Then connected with the through hole link position of Graphene interconnection layer；
When the number of interconnection structure is at least two, at least two interconnection structure is sequentially overlapped setting from bottom to up, and
And they are arranged between substrate top surface and top interconnection layer lower surface, i.e., in described at least two interconnection structure, the top
The upper surface of interconnection structure top interconnection layer is set, wherein, at least two interconnection structure, neighbouring two are mutually
Link in structure, the CNT through-hole interconnection being arranged below in interconnection structure is used for the stone that will be arranged below in interconnection structure
Black alkene interconnection layer is connected with the Graphene interconnection layer being disposed in interconnection structure.
For the Graphene interconnection layer in above-mentioned at least one interconnection structure, it can be multi-layer graphene, and now, graphite
Being prepared on alkene interconnection layer has Graphene interconnection line；Preferably, the thickness of the Graphene interconnection layer is more than or equal to 3nm.
And for the Graphene interconnection layer in the interconnection structure closest to substrate, its except can be multi-layer graphene, its
Can be the individual layer or few layer graphene material for constituting transistor channel, and now, the graphite closest in the interconnection structure of substrate
Being prepared on alkene interconnection layer has graphene-channel, it is preferable that its thickness is individual layer or few layer.
Interconnection structure of the invention is illustrated below in conjunction with specific embodiment.
Embodiment 1
When interconnection structure number is 1, as shown in figure 1, the interconnection structure of a kind of integrated CNT and Graphene includes one
Individual interconnection structure, the interconnection structure is arranged between the upper surface of substrate 101 and the lower surface of top interconnection layer 110；
Specifically, the interconnection structure includes：
First connected medium layer 103, is arranged between the upper surface of substrate 101 and the lower surface of top interconnection layer 110；
First Graphene interconnection layer 102, is arranged on the upper surface of substrate 101 and insertion is arranged under the first connected medium layer 103
Surface；
First CNT through-hole interconnection 104, insertion is arranged in the first connected medium layer 103, and its one end and the first stone
Black alkene interconnection layer 102 through hole link position connection, its other end by the first connected medium layer 103 so as to top interconnection layer
110 through hole link position connection, i.e., now, the first CNT through-hole interconnection 104 is by the first connected medium layer 103
Upper surface connects with the first Graphene interconnection layer 102.Wherein, for the top interconnection layer 110, it is mutual that it is substantially a Graphene
Connect layer, i.e. top Graphene interconnection layer.
Used as the preferred embodiment of the present embodiment, the first Graphene interconnection layer 102 and top interconnection layer 110 are many
Layer graphene, and now, Graphene interconnection line has been prepared on the first Graphene interconnection layer 102 and top interconnection layer 110；
Preferably, the thickness of the first Graphene interconnection layer 102 and top interconnection layer 110 is more than or equal to 3nm.
And for the first above-mentioned Graphene interconnection layer 102,, except that can be multi-layer graphene, it be alternatively composition crystal for it
The individual layer in pipe trench road or few layer graphene material, and now, on the first Graphene interconnection layer 102 preparing has Graphene ditch
Road, it is preferable that its thickness is individual layer or few layer.
Used as the preferred embodiment of the present embodiment, the first connected medium layer 103 uses the medium of low-k
Material manufacture, wherein, the dielectric material of the low-k includes but is not limited to porous media material, comprising part
Dielectric material of air-gap etc..
Embodiment 2
When interconnection structure number is two, as shown in Fig. 2 the interconnection structure of a kind of integrated CNT and Graphene includes the
One interconnection structure and the second interconnection structure, the substrate 101, the first interconnection structure, the second interconnection structure and top interconnection layer 110
Setting is sequentially overlapped from bottom to up, wherein, first interconnection structure includes that the first Graphene interconnection layer 102, first is interconnected and is situated between
Matter layer 103 and the first CNT through-hole interconnection 104, second interconnection structure include the second Graphene interconnection layer 105, second
Connected medium layer 106 and the second CNT through-hole interconnection 107；
First connected medium layer 103, is arranged between the upper surface of substrate 101 and the second connected medium 106 lower surface of layer；
First Graphene interconnection layer 102, is arranged on the upper surface of substrate 101 and insertion is arranged under the first connected medium layer 103
Surface；
First CNT through-hole interconnection 104, insertion is arranged in the first connected medium layer 103, and its one end and the first stone
Black alkene interconnection layer 102 through hole link position connection, its other end by the first connected medium layer 103 so as to the second Graphene
The through hole link position connection of interconnection layer 105, i.e., now, the first CNT through-hole interconnection 104 is by the first connected medium
The upper surface of layer 103 connects with the first Graphene interconnection layer 102；
Second connected medium layer 106, is arranged between the first connected medium 103 upper surface of layer and the lower surface of top interconnection layer 110；
Second Graphene interconnection layer 105, is arranged on the first connected medium 103 upper surface of layer and insertion is arranged on the second connected medium
The lower surface of layer 106；
Second CNT through-hole interconnection 107, insertion is arranged in the second connected medium layer 106, and its one end and the second stone
Black alkene interconnection layer 105 through hole link position connection, its other end by the second connected medium layer 106 so as to top interconnection layer
110 through hole link position connection, i.e., now, the second CNT through-hole interconnection 107 is by the second connected medium layer 106
Upper surface connects with the second Graphene interconnection layer 105.Wherein, for the top interconnection layer 110, it is mutual that it is substantially a Graphene
Connect layer, i.e. top Graphene interconnection layer.
As the preferred embodiment of the present embodiment, the first Graphene interconnection layer 102, the second Graphene interconnection layer
105th, top interconnection layer 110 is multi-layer graphene, and now, the first Graphene interconnection layer 102, the interconnection of the second Graphene
Graphene interconnection line has been prepared on layer 105, top interconnection layer 110, it is preferable that the first Graphene interconnection layer 102, second
Graphene interconnection layer 105, the thickness of top interconnection layer 110 are all higher than being equal to 3nm.
And for the first above-mentioned Graphene interconnection layer 102,, except that can be multi-layer graphene, it be alternatively composition crystal for it
The individual layer in pipe trench road or few layer graphene material, and now, on the first Graphene interconnection layer 102 preparing has Graphene ditch
Road, it is preferable that its thickness is individual layer or few layer.
Used as the preferred embodiment of the present embodiment, the first connected medium layer 103 and the second connected medium layer 106 are adopted
It is fabricated by with the dielectric material of low-k, wherein, the dielectric material of the low-k includes but is not limited to many
Hole dielectric material, the dielectric material comprising partial air gap etc..
From the present embodiment 2, when the number of interconnection structure is more than 2, the structure setting is then analogized and just may be used as described above.
Embodiment 3
For the manufacture method of the interconnection structure described in above-described embodiment 1, it has been specifically included：
S101, as shown in figure 3, prepare the first graphene layer 201 on the substrate 101, wherein, the substrate 101 can be by semiconductor
Silicon substrate on material silicon, germanium silicon, insulating barrier etc. is constituted, and may also comprise compound semiconductor materials, such as III-V, two or six races,
The materials such as carborundum, and New Two Dimensional semi-conducting material, such as Graphene, molybdenum bisuphide, two tungsten selenides, black phosphorus material；
For above-mentioned steps S101, its method that can be shifted using chemical vapor deposition synthesizing graphite alkene and metallic film
The method of thermal annealing, so as to prepare the first graphene layer 201 on the substrate 101；
In the present embodiment, the step S101 is specially：
Layer of metal nickel is deposited with sputtering or method of evaporating on an extra substrate, thickness is between 50 nm-500 nm；
Then the substrate is put into plasma vapor deposition equipment, is warming up to 900 degrees Celsius under the protection of hydrogen atmosphere, it is then additional
Power 200W is passed through the gas source containing carbon such as methane come for exciting plasma, is needed to keep gas according to thickness
It is general between 10 seconds to 5 minutes that body is passed through the time；Carbon-containing gas source, applied power and heating power are finally closed, by substrate
Rapid drop in temperature is to room temperature, so as to multi-layer graphene of the thickness in more than 3nm can be prepared；The spin coating on Graphene is used afterwards
Photoresist or polymer to be placed the substrate into and erode nickel metal layer in the solution such as dust technology as mechanical support, so swum in
The graphene layer of solution surface can be transferred in target substrate 101, remove mechanical support layer；Then then sample is carried out repeatedly
Clean or carry out to be annealed under 300 degrees Celsius of high temperature, the quality for lifting Graphene；
In addition, preparing the technical process that the first graphene layer 201 is used on the substrate 101 for above-mentioned, ginseng is prepared by it
Several adjustment, also can on the substrate 101 prepare individual layer or few layer graphene；
S102, as shown in figure 4, by the processing step such as photoetching and etching, being prepared on the first graphene layer 201 has patterned
Graphene interconnection line or graphene-channel, so as to constitute the first Graphene interconnection layer 102；
For described step S102, it is specially：Concrete shape manufacture mask plate according to required wire, on graphene layer
Coating photoresist；The series of steps such as it is exposed, developed and removed photoresist using the mask plate for having manufactured, by the graphite of required reservation
Alkene layer is covered with photoresist；Dry etching is carried out using plasma, and obtain the first Graphene interconnection layer after removing photoresist
102；Wherein, dry plasma is used to the etching that the first graphene layer carries out dry etching, i.e. Graphene using plasma
Body lithographic method, the gas employed in this process can be that the fluorination of oxygen, argon gas, hydrogen, nitrogen, hydrocarbon or carbon is closed
The mixture of thing, or above-mentioned gas, and using photoresist as mask in photoetching, this can be easy to the removal after etching,
In addition, it also can combine other hard masks using photoresist（Such as metal, silicon nitride material）To realize the mask；
S103, as shown in figure 5, on the through hole link position of the first Graphene interconnection layer 102 deposit catalyst 401, wherein, it is right
In the catalyst 401, its position for being formed needs to correspond to the first CNT through-hole interconnection 104 that subsequent step is formed
Position, and the catalyst 401 can be the superposition of Fe, Ni, Co, FeAl, NiAl etc., or above-mentioned material；In addition, institute
The preparation of catalyst 401 is stated, it can be prepared using the method for being evaporated in vacuo or sputtering, the thickness of the catalyst 401 prepared
For between 0.5 nm to 10nm；
S104, as shown in fig. 6, deposit on the substrate 101 the first connected medium layer 103, make the first Graphene in step S3 mutual
Even layer 102 is embedded in the lower surface for being arranged on the first connected medium layer 103；
Wherein, the first connected medium layer 103 can be the dielectric material of low-k, the medium of the low-k
Material includes but is not limited to porous media material, the dielectric material comprising partial air gap etc.；The first connected medium layer 103
Can be prepared by modes such as vapor deposition, sputterings, and the thickness of the first connected medium layer 103 prepared is generally in 200 nm
To between 2 μm, it can also meet special applications demand in the external of this scope；
S105, as shown in fig. 7, by the processing step such as photoetching and etching, preparing through hole in the first connected medium layer 103, institute
Through hole is stated to be correspondingly arranged on the through hole link position of the first Graphene interconnection layer, wherein, the institute in the first connected medium layer 103
The through hole of preparation, its position corresponds to the position that deposited catalyst 401 shown in Fig. 5；
For the step S105, that is, the manufacturing process of through hole is formed, it is specially：
After coating photoresist on the first connected medium layer 103, photoetching, exposure, development are carried out, and the figure of mask used plate is used
The dielectric layer of through hole is spilt in acquisition after development is caused；Perform etching to form through hole using dry plasma afterwards；
Due to ensure that metallic catalyst is not etched after dry plasma, therefore in the present embodiment, used
Etching technics is：Inductively coupled plasma power is set to 935 W, reactive plasma power is set to 100 W, and gas is set to
The fluorocarbon 10sccm and sccm of hydrogen 8, and the sccm of helium 174 is passed through for back side refrigeration；This technological parameter is to metal
Material has etching selection ratio higher, and combines the detection technique of etching terminal, can be protected so after the completion of etching
Stay metallic catalyst；
S106, as shown in figure 8, based on the catalyst 401 for being deposited, it is mutual in the first Graphene using chemical gas-phase deposition method
Connect the array of direct growth CNT 701 on the through hole link position of layer 102, wherein, the chemical gas-phase deposition method includes
Plasma chemical vapor deposition method, thermal chemical vapor deposition method, Microwave plasma CVD method etc., when
During using plasma chemical gas-phase deposition method, its growth temperature can be 350 degrees Celsius to 850 degrees Celsius；
In the present embodiment, the gas employed in chemical gas-phase deposition method and proportioning are methane 30sccm：Nitrogen 35sccm：
Hydrogen 40sccm, growth time is 1 minute, and growth temperature is 650 degrees Celsius；Methane and nitrogen are closed after the completion of growth, in hydrogen
Room temperature is down in gas atmosphere；As shown in figure 8, catalyst granules 702 is located at the top of CNT 701 in growth course, and
The root of CNT 701 is then directly connected with the first Graphene interconnection layer 102；The length of the CNT 701 after growth
It is not fully consistent, by controlling growth time the length of most of CNT 701 should be caused higher than the first connected medium layer 103
Thickness；
S107, as shown in figure 9, carrying out Filled Dielectrics to the array of CNT 701 after carry out CMP process so that shape
Into the first CNT through-hole interconnection 104, wherein, the first CNT through-hole interconnection 104 is used for the first connected medium layer
103 upper surface connects with the first Graphene interconnection layer 102；
Wherein, the medium filled can be silica, silicon nitride and aluminum oxide etc., and the method for Filled Dielectrics can be atom
Layer deposition technology, chemical vapor deposition or physical vapor deposition technology etc.；When Filled Dielectrics are carried out, need to be according to CNT
Spacing sets the thickness of filled media, is generally filled with the thickness of medium for 10nm~50nm scopes, and after carrying out Filled Dielectrics
The carbon nanotube portion for being higher by the first connected medium layer 103 is then removed using CMP process, the first carbon is formed and is received
Mitron through-hole interconnection 104；
S108, as shown in Figure 10, the first connected medium layer 103 on prepare the second graphene layer 901, in this embodiment, second
Graphene layer 901 is substantially top graphene layer, i.e., equivalent to the first connected medium layer 103 and the first CNT through-hole interconnection
Top graphene layer is prepared on 104；
For step S108, using chemical gas-phase deposition method and metallic film thermal annealing process, in the way of direct growth, from
And the second graphene layer 901 is formed on the first connected medium layer 103, it directly connects with the first CNT through-hole interconnection 104
It is logical；
In the present embodiment, the preparation process of second graphene layer 901 is specially：Formed sediment on the first connected medium layer 103
Product layer of metal Ni, thickness is 50 nm~500 nm；Carbon source material is ready for, one layer of carbon-coating of deposit, deposit diamond-like is performed
The steps such as stone film, ion implanting carbon material；Then thermal anneal process is carried out to W metal in protective gas, temperature is 600
Degree Celsius~1000 degrees Celsius；Thereafter upper strata W metal is removed using solution such as dust technologies, in Ni and the first connected medium layer 103
Interface growth have the second graphene layer 901 of multilayer；
S109, by processing steps such as photoetching and etchings, being prepared on the second graphene layer 901 has patterned Graphene to interconnect
Layer, so as to constitute top interconnection layer 110, now, the first CNT through-hole interconnection 104 by the first Graphene interconnection layer 102 with
Top interconnection layer 110 is connected；For the preparation process of the top interconnection layer 110 in step S109, its with step S102 in first
The preparation process of Graphene interconnection layer 102 is identical；
By above-mentioned manufacturing step, it is as shown in Figure 1 that it finally prepares the interconnection structure for drawing.
Embodiment 4
For the manufacture method of the interconnection structure described in above-described embodiment 2, it has been specifically included：
S201, as shown in figure 3, prepare the first graphene layer 201 on the substrate 101, wherein, the substrate 101 can be by semiconductor
Silicon substrate on material silicon, germanium silicon, insulating barrier etc. is constituted, and may also comprise compound semiconductor materials, such as III-V, two or six races,
The materials such as carborundum, and New Two Dimensional semi-conducting material, such as Graphene, molybdenum bisuphide, two tungsten selenides, black phosphorus material；
For above-mentioned steps S201, its method that can be shifted using chemical vapor deposition synthesizing graphite alkene and metallic film
The method of thermal annealing, so as to prepare the first graphene layer 201 on the substrate 101；
In the present embodiment, the step S201 is specially：
Layer of metal nickel is deposited with sputtering or method of evaporating on an extra substrate, thickness is between 50 nm-500 nm；
Then the substrate is put into plasma vapor deposition equipment, is warming up to 900 degrees Celsius under the protection of hydrogen atmosphere, it is then additional
Power 200W is passed through the gas source containing carbon such as methane come for exciting plasma, is needed to keep gas according to thickness
It is general between 10 seconds to 5 minutes that body is passed through the time；Carbon-containing gas source, applied power and heating power are finally closed, by substrate
Rapid drop in temperature is to room temperature, so as to multi-layer graphene of the thickness in more than 3nm can be prepared；The spin coating on Graphene is used afterwards
Photoresist or polymer to be placed the substrate into and erode nickel metal layer in the solution such as dust technology as mechanical support, so swum in
The graphene layer of solution surface can be transferred in target substrate 101, remove mechanical support layer；Then then sample is carried out repeatedly
Clean or carry out to be annealed under 300 degrees Celsius of high temperature, the quality for lifting Graphene；
In addition, preparing the technical process that the first graphene layer 201 is used on the substrate 101 for above-mentioned, ginseng is prepared by it
Several adjustment, also can on the substrate 101 prepare individual layer or few layer graphene；
S202, as shown in figure 4, by the processing step such as photoetching and etching, being prepared on the first graphene layer 201 has patterned
Graphene interconnection line and graphene-channel, so as to constitute the first Graphene interconnection layer 102；
For described step S202, it is specially：Concrete shape manufacture mask plate according to required wire, on graphene layer
Coating photoresist；The series of steps such as it is exposed, developed and removed photoresist using the mask plate for having manufactured, by the graphite of required reservation
Alkene layer is covered with photoresist；Dry etching is carried out using plasma, and obtain the first Graphene interconnection layer after removing photoresist
102；Wherein, dry plasma is used to the etching that the first graphene layer carries out dry etching, i.e. Graphene using plasma
Body lithographic method, the gas employed in this process can be that the fluorination of oxygen, argon gas, hydrogen, nitrogen, hydrocarbon or carbon is closed
The mixture of thing, or above-mentioned gas, and using photoresist as mask in photoetching, this can be easy to the removal after etching,
In addition, it also can combine other hard masks using photoresist（Such as metal, silicon nitride material）To realize the mask；
S203, as shown in figure 5, on the through hole link position of the first Graphene interconnection layer 102 deposit catalyst 401, wherein, it is right
In the catalyst 401, its position for being formed needs to correspond to the first CNT through-hole interconnection 104 that subsequent step is formed
Position, and the catalyst 401 can be the superposition of Fe, Ni, Co, FeAl, NiAl etc., or above-mentioned material；In addition, institute
The preparation of catalyst 401 is stated, it can be prepared using the method for being evaporated in vacuo or sputtering, the thickness of the catalyst 401 prepared
For between 0.5 nm to 10nm；
S204, as shown in fig. 6, deposit on the substrate 101 the first connected medium layer 103, make the first Graphene in step S3 mutual
Even layer 102 is embedded in the lower surface for being arranged on the first connected medium layer 103；
Wherein, the first connected medium layer 103 can be the dielectric material of low-k, the medium of the low-k
Material includes but is not limited to porous media material, the dielectric material comprising partial air gap etc.；The first connected medium layer 103
Can be prepared by modes such as vapor deposition, sputterings, and the thickness of the first connected medium layer 103 prepared is generally in 200 nm
To between 2 μm, it can also meet special applications demand in the external of this scope；
S205, as shown in fig. 7, by the processing step such as photoetching and etching, preparing through hole in the first connected medium layer 103, institute
Through hole is stated to be correspondingly arranged on the through hole link position of the first Graphene interconnection layer, wherein, the institute in the first connected medium layer 103
The through hole of preparation, its position corresponds to the position that deposited catalyst 401 shown in Fig. 5；
For the step S205, that is, the manufacturing process of through hole is formed, it is specially：
After coating photoresist on the first connected medium layer 103, photoetching, exposure, development are carried out, and the figure of mask used plate is used
The dielectric layer of through hole is spilt in acquisition after development is caused；Perform etching to form through hole using dry plasma afterwards；
Due to ensure that metallic catalyst is not etched after dry plasma, therefore in the present embodiment, used
Etching technics is：Inductively coupled plasma power is set to 935 W, reactive plasma power is set to 100 W, and gas is set to
The fluorocarbon 10sccm and sccm of hydrogen 8, and the sccm of helium 174 is passed through for back side refrigeration；This technological parameter is to metal
Material has etching selection ratio higher, and combines the detection technique of etching terminal, can be protected so after the completion of etching
Stay metallic catalyst；
S206, as shown in figure 8, based on the catalyst 401 for being deposited, it is mutual in the first Graphene using chemical gas-phase deposition method
Connect the array of direct growth CNT 701 on the through hole link position of layer 102, wherein, the chemical gas-phase deposition method includes
Plasma chemical vapor deposition method, thermal chemical vapor deposition method, Microwave plasma CVD method etc., when
During using plasma chemical gas-phase deposition method, its growth temperature can be 350 degrees Celsius to 850 degrees Celsius；
In the present embodiment, the gas employed in chemical gas-phase deposition method and proportioning are methane 30sccm：Nitrogen 35sccm：
Hydrogen 40sccm, growth time is 1 minute, and growth temperature is 650 degrees Celsius；Methane and nitrogen are closed after the completion of growth, in hydrogen
Room temperature is down in gas atmosphere；As shown in figure 8, catalyst granules 702 is located at the top of CNT 701 in growth course, and
The root of CNT 701 is then directly connected with the first Graphene interconnection layer 102；The length of the CNT 701 after growth
It is not fully consistent, by controlling growth time the length of most of CNT 701 should be caused higher than the first connected medium layer 103
Thickness；
S207, as shown in figure 9, carrying out Filled Dielectrics to the array of CNT 701 after carry out CMP process so that shape
Into the first CNT through-hole interconnection 104, wherein, the first CNT through-hole interconnection 104 is used for the first connected medium layer
103 upper surface connects with the first Graphene interconnection layer 102；
Wherein, the medium filled can be silica, silicon nitride and aluminum oxide etc., and the method for Filled Dielectrics can be atom
Layer deposition technology, chemical vapor deposition or physical vapor deposition technology etc.；When Filled Dielectrics are carried out, need to be according to CNT
Spacing sets the thickness of filled media, is generally filled with the thickness of medium for 10nm~50nm scopes, and after carrying out Filled Dielectrics
The carbon nanotube portion for being higher by the first connected medium layer 103 is then removed using CMP process, the first carbon is formed and is received
Mitron through-hole interconnection 104；
S208, as shown in Figure 10, the first connected medium layer 103 on prepare the second graphene layer 901, in this embodiment, second
Graphene layer 901 is substantially to be used to prepare the second Graphene interconnection layer 105 in the second interconnection structure, i.e., equivalent to the first interconnection
The second graphene layer 901 is prepared on the CNT through-hole interconnection 104 of dielectric layer 103 and first；
For step S208, using chemical gas-phase deposition method and metallic film thermal annealing process, in the way of direct growth, from
And the second graphene layer 901 is formed on the first connected medium layer 103, it directly connects with the first CNT through-hole interconnection 104
It is logical；
In the present embodiment, the preparation process of second graphene layer 901 is specially：Formed sediment on the first connected medium layer 103
Product layer of metal Ni, thickness is 50 nm~500 nm；Carbon source material is ready for, one layer of carbon-coating of deposit, deposit diamond-like is performed
The steps such as stone film, ion implanting carbon material；Then thermal anneal process is carried out to W metal in protective gas, temperature is 600
Degree Celsius~1000 degrees Celsius；Thereafter upper strata W metal is removed using solution such as dust technologies, in Ni and the first connected medium layer 103
Interface growth have the second graphene layer 901 of multilayer；
S209, as shown in figure 11, by the processing step such as photoetching and etching, being prepared on the second graphene layer 901 has graphical
Graphene interconnection layer, so as to constitute the second Graphene interconnection layer 105, now, the first CNT through-hole interconnection 104 is by first
Graphene interconnection layer 102 is connected with the second Graphene interconnection layer 105；For the second Graphene interconnection layer 105 in step S209
Preparation process, it is identical with the preparation process of the first Graphene interconnection layer 102 in step S202；
S210, using step S203 to the preparation process of step S207 come realize the second connected medium layer 106 and second carbon nanometer
The preparation of pipe through-hole interconnection 107；
S211, realized using the graphene layer preparation process of step S208 the second connected medium layer 106 on prepare the 3rd
Graphene layer, now, the 3rd described graphene layer is top graphene layer, then, is interconnected using the Graphene of step S209
Layer preparation process is realized for top graphene layer being prepared into top interconnection layer 110；
By above-mentioned manufacturing step, it is as shown in Figure 2 that it finally prepares the interconnection structure for drawing.
Can be obtained by the interconnection structure manufacture method step of above-described embodiment 4, when the number of interconnection structure is more than 2, then existed
After having prepared the first interconnection structure, and before top interconnection layer 110 is prepared, repeat the preparation of step S208 ~ 210
Process, the interconnection structure for constituting the corresponding number of plies just may be used.
Embodiment 5
It is the oxide layer substrate on silicon when multi-layer graphene, and backing material is prepared on substrate using manufacture method of the present invention
When, the multi-layer graphene on substrate that preparation draws, its transmission electron microscope photo is as shown in figure 12.Wherein, label 111 is marked in figure
What is known is oxide layer substrate on silicon, and it is multi-layer graphene that label 112 is identified.
Embodiment 6
When using manufacture method of the present invention that the Fe catalyst for preparing 2nm is sputtered on multi-layer graphene, then formed sediment in chemical gaseous phase
It is as shown in figure 13 the surface scan electron microscope after high annealing to be carried out in product equipment.Can draw in fig. 13, after the high-temperature anneal,
The Fe films of deposit form nano particle, and this can be used for the carbon nano tube growth of subsequent step.
Embodiment 7
Figure 14 show the cross-sectional scans electron microscopic picture of the CNT of direct growth on multi-layer graphene.Wherein, grow
Using the nm of Fe catalyst 2,700 degrees Celsius of growth temperature, growth time is 3 minutes, and passes through the carbon that this specific method is grown
Nanotube has good vertical orientated, can meet the requirement of CNT through-hole interconnection.Further, since catalyst granules is in life
CNT top is located at after length, can be removed in subsequent polishing step, therefore in the interconnection structure for finally producing,
Interface between connected medium layer completely eliminated the influence of metal material, realize the seamless company of CNT and Graphene
Connect.
Above is preferable implementation of the invention is illustrated, but the invention is not limited to the implementation
Example, those of ordinary skill in the art can also make a variety of equivalent variations or replace on the premise of without prejudice to spirit of the invention
Change, these equivalent deformations or replacement are all contained in the application claim limited range.
Claims (10)
1. the interconnection structure of a kind of integrated CNT and Graphene, it is characterised in that：It is described including at least one interconnection structure
Interconnection structure includes connected medium layer, and the lower surface insertion of the connected medium layer is provided with Graphene interconnection layer, the interconnection
The CNT through-hole interconnection for the upper surface of connected medium layer to be connected with Graphene interconnection layer is provided with dielectric layer.
2. the interconnection structure of a kind of integrated CNT and Graphene according to claim 1, it is characterised in that：The interconnection
The number of structure is at least two, and at least two interconnection structure is sequentially overlapped setting from bottom to up, wherein, it is neighbouring
In two interconnection structures, the CNT through-hole interconnection being arranged below in interconnection structure is used to that interconnection structure will to be arranged below
In Graphene interconnection layer connected with the Graphene interconnection layer being disposed in interconnection structure.
3. the interconnection structure of a kind of integrated CNT according to claim 1 or claim 2 and Graphene, it is characterised in that：It is described
Graphene interconnection layer is multi-layer graphene.
4. the interconnection structure of a kind of integrated CNT and Graphene according to claim 3, it is characterised in that：The graphite
The thickness of alkene interconnection layer is more than or equal to 3nm.
5. the interconnection structure of a kind of integrated CNT according to claim 1 or claim 2 and Graphene, it is characterised in that：It is described
Connected medium layer is fabricated by using the dielectric material of low-k.
6. the interconnection structure manufacture method of a kind of integrated CNT and Graphene, it is characterised in that：Step included by the method
Suddenly have：
Graphene layer is prepared on S1, the connected medium layer in substrate or lower section interconnection structure；
S2, on graphene layer prepare have patterned Graphene interconnection line or graphene-channel so that constitute Graphene interconnection
Layer；
S3, on the through hole link position of Graphene interconnection layer deposit catalyst；
Connected medium layer is deposited on S4, the connected medium layer in substrate or lower section interconnection structure, the Graphene in step S3 is made
Interconnection layer insertion is arranged on the lower surface of connected medium layer；
S5, connected medium layer in prepare through hole, the through hole is correspondingly arranged on the through hole link position of Graphene interconnection layer；
S6, based on the catalyst for being deposited, grow carbon nano pipe array on the through hole link position of Graphene interconnection layer；
S7, Filled Dielectrics are carried out to carbon nano pipe array after carry out CMP process so that formed CNT interconnection
Through hole, wherein, the upper surface that the CNT through-hole interconnection is used for connected medium layer connects with Graphene interconnection layer.
7. the interconnection structure manufacture method of a kind of integrated CNT and Graphene according to claim 6, it is characterised in that：
Described in the step S1 the step for preparing graphene layer on substrate, it is specially：
The method and the method for metallic film thermal annealing shifted using chemical vapor deposition synthesizing graphite alkene, so as in lining
Graphene layer is prepared on bottom.
8. the interconnection structure manufacture method of a kind of integrated CNT and Graphene according to claim 6, it is characterised in that：
The step for preparing graphene layer on the layer of the connected medium in the interconnection structure of lower section described in the step S1, its is specific
For：
Using chemical gas-phase deposition method and metallic film thermal annealing process, so as to the connected medium layer in the interconnection structure of lower section
On prepare graphene layer.
9. according to claim any one of 6-8 a kind of integrated CNT and Graphene interconnection structure manufacture method, its
It is characterised by：Carbon nano pipe array this step is grown described in the step S6 on the through hole link position of Graphene interconnection layer
Suddenly, it is specially：
Using chemical gas-phase deposition method, so as to grow carbon nano pipe array on the through hole link position of Graphene interconnection layer.
10. according to claim any one of 6-8 a kind of integrated CNT and Graphene interconnection structure manufacture method, its
It is characterised by：The catalyst is at least one of Fe, Ni, Co, FeAl, NiAl.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107658264A (en) * | 2017-09-28 | 2018-02-02 | 江苏师范大学 | A kind of vertical interconnected method of three-dimensional silicon hole based on multi-layer graphene auxiliary layer |
| CN108470765A (en) * | 2018-03-21 | 2018-08-31 | 中国人民解放军国防科技大学 | graphene vertical heterojunction device and preparation method thereof |
| CN109708766A (en) * | 2019-01-02 | 2019-05-03 | 华南理工大学 | A kind of detector and its manufacturing method using acoustic resonator and carbon nanotube |
| WO2023287538A1 (en) * | 2021-07-14 | 2023-01-19 | Micron Technology, Inc. | Integrated assemblies having graphene-containing-structures |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070148963A1 (en) * | 2005-12-27 | 2007-06-28 | The Hong Kong University Of Science And Technology | Semiconductor devices incorporating carbon nanotubes and composites thereof |
| CN102007571A (en) * | 2008-02-25 | 2011-04-06 | 斯莫特克有限公司 | Deposition and selective removal of conducting helplayer for nanostructure processing |
| CN102130091A (en) * | 2010-12-17 | 2011-07-20 | 天津理工大学 | Composite through-hole interconnecting structure for integrated circuit chip and preparation method thereof |
| CN102130040A (en) * | 2010-12-17 | 2011-07-20 | 天津理工大学 | Method for forming through-hole interconnection and metalizing contact of carbon nano tube |
| CN102403304A (en) * | 2011-12-06 | 2012-04-04 | 上海集成电路研发中心有限公司 | Interconnection structure and manufacturing method thereof |
| CN102881651A (en) * | 2012-10-25 | 2013-01-16 | 天津理工大学 | Method for improving electrical interconnection characteristic of carbon nano tube |
| CN103456677A (en) * | 2012-06-05 | 2013-12-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
-
2017
- 2017-01-17 CN CN201710036094.1A patent/CN106847790A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070148963A1 (en) * | 2005-12-27 | 2007-06-28 | The Hong Kong University Of Science And Technology | Semiconductor devices incorporating carbon nanotubes and composites thereof |
| CN102007571A (en) * | 2008-02-25 | 2011-04-06 | 斯莫特克有限公司 | Deposition and selective removal of conducting helplayer for nanostructure processing |
| CN102130091A (en) * | 2010-12-17 | 2011-07-20 | 天津理工大学 | Composite through-hole interconnecting structure for integrated circuit chip and preparation method thereof |
| CN102130040A (en) * | 2010-12-17 | 2011-07-20 | 天津理工大学 | Method for forming through-hole interconnection and metalizing contact of carbon nano tube |
| CN102403304A (en) * | 2011-12-06 | 2012-04-04 | 上海集成电路研发中心有限公司 | Interconnection structure and manufacturing method thereof |
| CN103456677A (en) * | 2012-06-05 | 2013-12-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN102881651A (en) * | 2012-10-25 | 2013-01-16 | 天津理工大学 | Method for improving electrical interconnection characteristic of carbon nano tube |
Non-Patent Citations (1)
| Title |
|---|
| CHANGJIAN ZHOU，RICHARD SENEGOR，ZACHARY BARON: "Synthesis and interface characterization of CNTs on graphene", 《NANOTECHNOLOGY》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107658264A (en) * | 2017-09-28 | 2018-02-02 | 江苏师范大学 | A kind of vertical interconnected method of three-dimensional silicon hole based on multi-layer graphene auxiliary layer |
| CN108470765A (en) * | 2018-03-21 | 2018-08-31 | 中国人民解放军国防科技大学 | graphene vertical heterojunction device and preparation method thereof |
| CN108470765B (en) * | 2018-03-21 | 2021-07-23 | 中国人民解放军国防科技大学 | Graphene vertical heterojunction device and preparation method thereof |
| CN109708766A (en) * | 2019-01-02 | 2019-05-03 | 华南理工大学 | A kind of detector and its manufacturing method using acoustic resonator and carbon nanotube |
| WO2023287538A1 (en) * | 2021-07-14 | 2023-01-19 | Micron Technology, Inc. | Integrated assemblies having graphene-containing-structures |
| US11682623B2 (en) | 2021-07-14 | 2023-06-20 | Micron Technology, Inc. | Integrated assemblies having graphene-containing-structures |
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