CN106847744B - 阵列基板的制备方法、阵列基板及显示装置 - Google Patents

阵列基板的制备方法、阵列基板及显示装置 Download PDF

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CN106847744B
CN106847744B CN201710090921.5A CN201710090921A CN106847744B CN 106847744 B CN106847744 B CN 106847744B CN 201710090921 A CN201710090921 A CN 201710090921A CN 106847744 B CN106847744 B CN 106847744B
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layer
array substrate
photoresist
insulating layer
hole
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CN106847744A (zh
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宫奎
段献学
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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Publication of CN106847744A publication Critical patent/CN106847744A/zh
Priority to US15/762,292 priority patent/US10553624B2/en
Priority to PCT/CN2017/101051 priority patent/WO2018149119A1/zh
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Abstract

一种阵列基板的制备方法、阵列基板及显示装置。该阵列基板的制备方法包括：提供衬底基板；在衬底基板上依次形成有源层和覆盖有源层的第一绝缘层；对第一绝缘层进行一次构图工艺，在第一绝缘层中形成暴露有源层的第一通孔和第二通孔，并在第一绝缘层表面上形成第一凹槽；在构图后的第一绝缘层上形成导电层，导电层填充在第一通孔、第二通孔和第一凹槽中；进行研磨工艺以分别形成源极、漏极和像素电极。该阵列基板的制备方法通过两道掩膜工艺形成阵列基板，减少了掩膜工艺的次数，简化了工艺制作流程，降低了生产成本，缩短了制备时间，提高了生产效率，提升了产品良率。

Description

阵列基板的制备方法、阵列基板及显示装置
技术领域
本公开的实施例涉及一种阵列基板的制备方法、阵列基板以及具有该阵列基板的显示装置。
背景技术
随着显示技术的发展，液晶显示器(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被日益广泛地应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，已经成为显示装置中的主流。
液晶显示器根据驱动液晶的电场方向，分为垂直电场型和水平电场型。垂直电场型包括扭曲向列(TN，Twist Nematic)型，其需要在阵列基板上形成像素电极，在彩膜基板上形成公共电极；水平电场型包括共平面切换(IPS,In-Plane Switching)型、边界电场切换(FFS，Fringe Field Switching)型和高级超维场转换技术(ADS，Advanced SuperDimension Switch)型等，其需要在阵列基板上形成像素电极和公共电极。目前，无论对于垂直电场型液晶显示器，还是水平电场型液晶显示器，其阵列基板通常都需要经过4次或5次掩膜工艺，使得阵列基板的制备工艺复杂、生产效率低、生产成本高，且随着液晶显示器朝大尺寸制造发展，其多次掩膜工艺还会导致产品良率降低、产能下降。
发明内容
本公开至少一实施例提供一种阵列基板的制备方法，包括：提供衬底基板；在所述衬底基板上依次形成有源层和覆盖所述有源层的第一绝缘层；对所述第一绝缘层进行一次构图工艺，在所述第一绝缘层中形成暴露所述有源层的第一通孔和第二通孔，并在所述第一绝缘层表面上形成第一凹槽；在构图后的所述第一绝缘层上形成导电层，所述导电层填充在所述第一通孔、第二通孔和第一凹槽中；进行研磨工艺以去除所述第一绝缘层表面上的所述导电层，且在所述第一通孔、第二通孔和第一凹槽中保留所述导电层，从而分别形成源极、漏极和像素电极。
本公开至少一实施例提供一种阵列基板，包括：衬底基板；设置在所述衬底基板上的有源层以及覆盖所述有源层的第一绝缘层，所述第一绝缘层具有暴露所述有源层的第一通孔和第二通孔以及设置在所述第一绝缘层表面上的第一凹槽，分别设置在所述第一绝缘层的第一通孔和第二通孔中与所述有源层连接的源极和漏极，以及设置在所述第一凹槽中的像素电极。
本公开至少一实施例提供一种显示装置，包括上述任一实施例中的阵列基板。
本公开至少一实施例提供一种阵列基板的制备方法、阵列基板及显示装置。这些实施例的阵列基板的制备方法可以利用两道掩膜工艺制作阵列基板，减少了掩膜工艺的次数，简化了工艺制作流程，降低了工艺复杂度、生产成本，由此缩短了制备时间，提高了生产效率，提升了产品良率。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1a为本公开一实施例提供的一种阵列基板的平面示意图；
图1b为沿图1a中线A-A'方向该阵列基板的截面结构示意图；
图1c为沿图1a中线B-B'方向该阵列基板的截面结构示意图；
图2a为一种石墨烯的分子结构示意图；
图2b为一种掺氮石墨烯的分子结构示意图；
图3a-4j为本公开一实施例提供的一种阵列基板的制备方法的工艺流程图；
图5a-5b为本公开一实施例提供的另一种阵列基板的制备方法的工艺流程图；
图6a为本公开一实施例提供的另一种阵列基板的平面示意图；
图6b为沿图6a中线C-C'方向该阵列基板的一个示例的截面结构示意图；
图6c为沿图6a中线C-C'方向该阵列基板的另一个示例的截面结构示意图；
图7a为本公开另一实施例提供的一种阵列基板的平面示意图；
图7b为沿图7a中线D-D'方向该阵列基板的截面结构示意图；
图7c为沿图7a中线E-E'方向该阵列基板的截面结构示意图；
图8为本公开另一实施例提供的一种阵列基板的截面结构示意图。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
附图中各个部件或结构并非严格按照比例绘制，为了清楚起见，可能夸大或缩小各个部件或结构的尺寸，例如增加层的厚度、电极的宽度等，但是这些不应用于限制本公开的范围。为了保持本公开实施例的以下说明清楚且简明，可省略已知功能和已知部件的详细说明。
薄膜晶体管阵列基板的制备工艺流程通常可以包括依次在衬底基板上形成有源层、绝缘层、金属栅极层、钝化层、源漏电极层以及像素电极层等，一般需要4次或5次掩膜工艺，每次掩膜工艺包括使用掩膜进行曝光，然后进行显影、刻蚀等，因此制作工艺复杂、生产效率低，而且掩膜板的成本较高，导致制造成本较高，另一方面，多次掩膜工艺会导致产品的制造时间增加，产品良率降低、产能下降，从而限制了薄膜晶体管阵列基板技术的发展。
本公开至少一实施例提供一种阵列基板的制备方法、阵列基板及显示装置。该阵列基板的制备方法包括：提供衬底基板；在所述衬底基板上依次形成有源层和覆盖所述有源层的第一绝缘层；对所述第一绝缘层进行一次构图工艺，在所述第一绝缘层中形成暴露所述有源层的第一通孔和第二通孔，并在所述第一绝缘层表面上形成第一凹槽；在构图后的所述第一绝缘层上形成导电层，所述导电层填充在所述第一通孔、第二通孔和第一凹槽中；进行研磨工艺以去除所述第一绝缘层表面上的所述导电层，且在所述第一通孔、第二通孔和第一凹槽中保留所述导电层，从而分别形成源极、漏极和像素电极。
该阵列基板的制备方法，通过一道掩膜工艺形成有源层，再通过一道掩膜工艺，然后经过一次研磨工序形成源极、漏极以及像素电极，减少了掩膜工艺的次数，简化了工艺制作流程，降低了工艺复杂度、生产成本，缩短了制备时间，提高了生产效率，提升了产品良率；而且在一些实施例中，有源层采用透明的类石墨烯半导体，栅线采用石墨烯导体，源极、漏极、栅极以及像素电极为透明氧化铟锡，从而该方法可以进一步减少掩膜工艺，而且还可以提高阵列基板的开口率、稳定性和透明度，且有源层的弯曲度能够满足柔性显示的需求。
下面对本公开的几个实施例进行详细说明，但是本公开并不限于这些具体的实施例。
实施例一
图1a示出了本实施例提供的阵列基板的平面示意图；图1b为沿图1a中线A-A'方向该阵列基板的截面结构示意图；图1c为沿图1a中线B-B'方向该阵列基板的截面结构示意图；图2a示出了一种石墨烯的分子结构示意图；图2b示出了一种掺氮石墨烯的分子结构示意图；图3a-4j示出了本实施例提供的阵列基板的制备方法的工艺流程图。图1a至4j中仅示出相关结构的一部分以便更清楚地说明。
例如，如图1a和1b所示，本实施例的阵列基板包括：衬底基板1；设置在衬底基板1上的有源层16；覆盖有源层16上的第一绝缘层21；设置在第一绝缘层21上的第一电极12、第二电极13和像素电极10。像素电极10与第二电极13彼此电连接。
例如，衬底基板1可以是透明绝缘基板，该衬底基板1的材料的示例可以为玻璃基板、石英基板、塑料基板或其他合适的材料。
例如，第一绝缘层21的材料的示例包括氮化硅(SiNx)、氧化硅(SiOx)、氧化铝(Al2O3)、氮化铝(AlN)或其他合适的材料，例如有机树脂材料。例如，该第一绝缘层21可以为由氮化硅或者氧化硅构成的单层结构，或者由氮化硅和氧化硅构成的双层结构。
例如，第一绝缘层21上设置有暴露有源层16的第一通孔121和第二通孔131，第一绝缘层21表面设置有第一凹槽101。第一电极12通过第一通孔121与有源层16电连接，第二电极13通过第二通孔131与有源层16电连接；像素电极10形成在第一凹槽101中。
例如，该阵列基板还包括设置在衬底基板1上的公共电极20，公共电极20被第一绝缘层21覆盖。
例如，公共电极20的材料可以为石墨烯导体，有源层16的材料可以为类石墨烯半导体。
例如，如图2a所示，石墨烯导体是由碳原子以sp2杂化轨道组成的六角型蜂巢晶格且厚度只有一个碳原子厚度的单层片状结构的导体材料。石墨烯导体具有良好的导电性、稳定性、透明度和柔韧性的特点，因而可以提高阵列基板的导电率、稳定性、透明度和柔韧性。
例如，类石墨烯半导体是通过改变石墨烯导体的化学结构得到的半导体材料，类石墨烯半导体例如可以通过控制替代元素对应的原子取代石墨烯导体中的部分碳原子形成，从而使得导带和价带重合的石墨烯导体的导带和价带分开具有一定带隙，从而降低了石墨烯导体的导电率，实现将导带和价带重合的石墨烯导体改变为价带和导带分开具有一定的带隙的类石墨烯半导体；另一方面，类石墨烯半导体为通过改变石墨烯导体的化学结构得到的类石墨烯材料，因而类石墨烯半导体和石墨烯导体类似，具有良好的稳定性、柔韧性和透明度，在对其进行弯曲、折叠以及揉搓时其价键都不会发生断裂。因此，由类石墨烯半导体制备的有源层16的弯曲度能够满足柔性显示的要求。
例如，替代元素可以为第五主族元素、第六主族元素、第七主族元素和镧系元素包括的各种元素中的至少一种元素。例如，如图2b所示，替代元素可以为氮(N)原子，利用N原子对石墨烯进行掺杂，例如控制N等离子与石墨烯直接接触，N等离子与石墨烯发生反应，在石墨烯中对应位置处，N原子取代部分碳(C)原子，形成C-N键，从而得到包括碳原子C和原子N的掺氮石墨烯，即类石墨烯半导体。又例如，替代元素还可以为氢(H)原子，通过氢气、氩气或两者的混合气体对石墨烯进行氢化处理，从而得到氢化石墨烯半导体。需要说明的是，替代元素还可以为其他元素，或者还可以采用其他方式控制替代元素对应的粒子与石墨烯进行反应，本公开的实施例对此不做限制。
例如，像素电极10和公共电极20可以为板状电极，也可以为狭缝电极。例如，像素电极10和公共电极20可以包括多个分支电极，即二者均具有梳状结构，且像素电极10的分支和公共电极20的分支例如彼此重叠或彼此交错布置。如图1a所示，像素电极10为狭缝电极，包括多个例如彼此平行的分支电极，分支电极由狭缝间隔开；公共电极20为板状电极。在本实施例中，像素电极10形成在公共电极20之上，该阵列基板例如用于高级超维场转换技术(Advanced Super Dimension Switch，简称ADS)型液晶面板。
第一示例
例如，如图1a和1c所示，阵列基板还包括设置在第一绝缘层21上的栅极14和设置在衬底基板1上的栅线11。栅线11被第一绝缘层21所覆盖，第一绝缘层21中还设置有暴露栅线11的第三通孔141，第一绝缘层21表面还设置有第二凹槽142，栅极14设置在第二凹槽142和第三通孔141中，且通过第三通孔141与栅线11电连接。
例如，栅线11和公共电极20可以一同形成，栅线11和公共电极20的材料也可以为石墨烯，因此栅线11具有较高的导电率，从而可以提高栅线11的扫描信号传输速率，提高显示质量。
例如，如图1a所示，该阵列基板还包括数据线15，数据线15在纵向上延伸，而栅线11在水平方向上延伸，二者彼此绝缘交叉，薄膜晶体管例如形成在二者交叉的位置处。例如，数据线15可以设置在第一绝缘层21上，从而第一电极12可以与数据线15彼此电连接或形成为一体。或者，数据线15可以设置在衬底基板1上且被第一绝缘层21覆盖(保证数据线15与栅线11彼此绝缘设置即可，例如在二者彼此交叉的位置设置绝缘且例如数据线15被栅线11隔开的各个线段通过桥接电极彼此电连接)，从而在第一绝缘层21上还可以包括一过孔(未示出)，第一电极12通过该过孔与数据线15电连接。虽然图中仅示出了一个像素区域，但是本领域的普通技术人员可以知道，该阵列基板可以包括多个这样的像素区域，该多个像素排列为阵列以构成显示区域。
例如，数据线15的材料可以包括铜基金属、铝基金属、镍基金属等。例如，该铜基金属为铜(Cu)、铜锌合金(CuZn)、铜镍合金(CuNi)或铜锌镍合金(CuZnNi)等性能稳定的铜基金属合金。
例如，第一电极12、有源层16、第二电极13、栅极14以及第一绝缘层21总地构成了薄膜晶体管，该薄膜晶体管可以作为数据线15和栅线11界定的像素区域的开关元件。这里，第一电极12可以为源极或漏极，相应地第二电极13可以为漏极或源极。当栅线11上被施加开启(ON)信号时，该薄膜晶体管导通，从而使得像素电极10与数据线15电连接，数据线15上施加的信号可以被传递至像素电极10；当栅线11上被施加关闭(OFF)信号时，薄膜晶体管截止，从而使得像素电极10与数据线15断开电连接。
例如，第一电极12、第二电极13、像素电极10和栅极14的材料可以为透明导电材料、金属材料或其他合适的材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟(In2O3)、氧化铝锌(AZO)和碳纳米管等。例如，第一电极12、第二电极13、像素电极10和栅极14可以均由氧化铟锡制备而成，因而该阵列基板可以具有较高的开口率。
需要注意的是，第一绝缘层21例如可以形成在衬底基板1上以覆盖全部像素区域(或显示区域)，然而在图1b中，为了更清楚地示出这些层结构，仅示出了它们的一部分，但是这并非表示这些层也仅形成有这些部分。类似地，例如像素电极10以及公共电极20等也都在图1b中仅示出了一部分以作为参考。
下面将结合图3a至图4j对第一示例的阵列基板的制备方法进行说明。图3a-3d、3f-3h、4a-4j仍为沿如图1b所示的线A-A'的位置剖取的截面图。图3a至图4j仍然仅示出相关结构的一部分以便更清楚地说明。
例如，如图3a所示，提供一衬底基板1，在衬底基板1上沉积一层石墨烯导体层40。
例如，石墨烯导体层40可以采用溅射或热蒸发的方式沉积而成，其厚度可以为5nm-100nm，例如，可以为30nm、50nm以及80nm等。
例如，如图3b所示，通过涂覆的方式在石墨烯导体层40上沉积一层光刻胶42。
例如，如图3c所示，通过一道半色调或灰色调掩膜对光刻胶42进行曝光，然后对曝光后的光刻胶42进行显影，形成包括光刻胶全保留区域P3、光刻胶半保留区域P2和光刻胶全部去除区域P1的第一光刻胶掩膜层43。
需要说明的是，光刻胶全保留区域P3为光刻胶42全部保留的区域，其光刻胶42的厚度为d；光刻胶半保留区域P2为部分保留光刻胶42的区域，其光刻胶42的厚度例如可以为d1，d1小于d；光刻胶全部去除区域P1为光刻胶42全部去除的区域。需要指出的是，光刻胶全保留区域P3仅表示该区域中的光刻胶在显影后基本能够保留或保留的厚度最大，而非限制为其中的光刻胶在显影后没有任何变化。
例如，光刻胶42的涂覆可以采用旋涂、刮涂或者辊涂的方式。
例如，如图3d和3e所示，以第一光刻胶掩膜层43作为掩膜对石墨烯导体层40进行刻蚀工艺，刻蚀光刻胶全部去除区域P1的石墨烯导体层40，从而形成彼此绝缘的第一区域石墨烯导体层401、第二区域石墨烯导体层402以及第三区域石墨烯导体层403。需要说明的是，第一区域石墨烯导体层401处于光刻胶半保留区域P2，第二区域石墨烯导体层402和第三区域石墨烯导体层403处于光刻胶全保留区域P3，但彼此间隔开。
例如，第二区域石墨烯导体层402用于形成栅线11，第三区域石墨烯导体层403用于形成公共电极20。
例如，刻蚀工艺可以采用干法刻蚀或湿法刻蚀。例如，干法刻蚀可以采用化学方法(例如等离子体腐蚀PE)、物理方法(例如离子腐蚀IE)或物理与化学相结合的方法(例如反应离子腐蚀RIE)。例如，刻蚀工艺还可以采用离子束刻蚀(IBE)，其具有方向性好，各向异性，分辨率高、陡直度高以及不收刻蚀材料限制等特点，从而可以精确刻蚀。
例如，如图3d所示，若采用离子束刻蚀，则光刻胶全保留区域P3和光刻胶半保留区域P2内的光刻胶42由于等离子体的垂直轰击，其厚度分别减薄为d1’和d’，且d1’<d1，d’<d。
例如，如图3f和3g所示，采用IBE技术刻蚀光刻胶半保留区域P2，去除光刻胶半保留区域P2内的光刻胶42，使第一区域石墨烯导体层401暴露出来；然后，利用光刻胶全保留区域P3内的光刻胶42作为阻挡掩膜，在等离子体条件下控制替代元素对应的原子取代第一区域石墨烯导体层401中的部分碳(C)原子形成有源层16。
例如，替代元素可以为N原子。在等离子条件下，对暴露出来的第一区域石墨烯导体层401表面通入氮气(N2)，以得到N等离子，控制N等离子与第一区域石墨烯导体层401直接接触而发生反应，N原子取代部分C原子，形成C-N键，使原来导带和价带重合的石墨烯的导带和价带分开，形成一定的带隙，降低其导电率，从而得到类石墨烯半导体，形成有源层16。需要说明的是，替代元素还可以为其他元素，或者还可以采用其他方式控制替代元素对应的原子与石墨烯进行反应，本实施例对此不做限制。
需要说明的是，在如图3f和3g所示的制备方法中，采用IBE技术去除光刻胶半保留区域P2内的光刻胶42，而不采用灰化工艺。灰化工艺主要采用干法刻蚀去除光刻胶，其通过化学反应来去除光刻胶42，例如干法灰化工艺可以利用氧等离子体中的高反应活性的单原子氧极易与光刻胶42中的碳氢氧高分子化合物发生聚合反应，从而生成易挥发性的反应物，最终达到去除光刻胶42的目的。然而，第一区域石墨烯导体层401的主要成分是碳原子，其极易与氧等离子体中的高反应活性的单原子氧发生反应，导致第一区域石墨烯导体层401的性质发生改变或者被刻蚀一部分，从而影响由第一区域石墨烯导体层401形成的有源层16的品质，进而影响阵列基板的质量。而IBE技术采用具有一定能量的离子束(例如Ar、Kr或Xe离子)轰击材料表面，使材料原子发生溅射，从而达到刻蚀的目的，其为纯物理的过程，因而石墨烯导体层40上的碳原子不会与之产生反应，从而保持石墨烯导体层40的性质不发生改变；且IBE具有高分辨率和各向异性等特点，可以精确控制光刻胶42的刻蚀厚度，防止第一区域石墨烯导体层401被刻蚀。
需要说明的是，如图3f和3g所示，光刻胶全保留区域P3内的光刻胶42由于等离子体的垂直轰击，其厚度进一步减薄为d2，且d2<d’。光刻胶42经过两次等离子体轰击减薄其厚度，为了保证刻蚀工艺，防止石墨烯层被不完全刻蚀；或者对第一区域石墨烯导体层401进行处理时，防止第二区域石墨烯导体层402和第三区域石墨烯导体层403也被暴露，光刻胶42的厚度需要较厚，例如可以为2.5μm-3μm。例如，可以为3μm。
例如，如图3h和3i所示，采用剥离工艺去除光刻胶全保留区域P3内的光刻胶42，从而在衬底基板1上形成有源层16、公共电极20和栅线11。
例如，如图4a所示，在有源层16、公共电极20和栅线11上沉积一层绝缘层薄膜，以形成第一绝缘层21。
例如，第一绝缘层21厚度可以为600nm-1500nm，例如，可以为800nm或1000nm。
例如，沉积绝缘层薄膜可以采用化学气相沉积(CVD)，如等离子体增强化学气相沉积法(PECVD)、低压力化学气相沉积(LPCVD)等，亦可以为物理气相沉积(PVD)等。
例如，如图4b-4g所示，对第一绝缘层21进行一次构图工艺，在第一绝缘层21中形成暴露有源层16的第一通孔121和第二通孔131，暴露栅线11的第三通孔141(截面中未示出，但可以参考第一通孔121或第二通孔131)，并在第一绝缘层21表面上形成第一凹槽101和第二凹槽142。
例如，该一次构图工艺包括使用灰色调掩模或半色调掩模的光刻工艺，一次构图工艺可以包括以下步骤：
步骤1、如图4b所示，在第一绝缘层21上涂覆一层光刻胶421。
步骤2、如图4c所示，使用灰色调掩膜或半色调掩膜对光刻胶421进行曝光，然后对曝光后的光刻胶421显影，形成第二光刻胶掩膜层50。例如，第二光刻胶掩膜层50的第一区域501和第二区域502分别对应形成第一电极12和第二电极13的区域，第一区域501和第二区域502包括两侧边缘的光刻胶全保留区域，中间的光刻胶全部去除区域以及光刻胶全保留区域与光刻胶全部去除区域之间的光刻胶半保留区域。需要说明的是，光刻胶全保留区域、光刻胶半保留区域和光刻胶全部去除区域可以与上述说明相同。
步骤3、如图4d所示，利用第二光刻胶图案50作为阻挡掩模，采用第一次刻蚀工艺在第一绝缘层21中形成第一盲孔170、第二盲孔171和第三盲孔(未示出)。
步骤4、如图4e所示，采用灰化工艺去除光刻胶半保留区域的光刻胶，得到第三光刻胶掩膜层51。
步骤5、如图4f所示，利用光刻胶全保留区域内的光刻胶作为阻挡掩膜，采用第二次刻蚀工艺分别在第一盲孔170、第二盲孔171和第三盲孔位置处形成暴露有源层16的第一通孔121、第二通孔131和暴露栅线11的第三通孔141(未示出)，同时还形成第一凹槽101和在第一通孔121和第二通孔131之间的第二凹槽142。这里，第一至第三通孔都具有在截面为较宽的倒梯形的上部和截面为较窄的倒梯形的下部之间的台阶。
步骤6、如图4g所示，采用剥离工艺去除剩余的光刻胶以形成需要的结构。
本实施例中，第一电极12、第二电极13、栅极14和像素电极10位于同一层(例如第一绝缘层21)上，与分层制备相比，不仅简化了制备工艺，还可以降低阵列基板的厚度，实现显示装置超薄化。
例如，第一凹槽101可以包括多个分支凹槽，从而使得通过第一凹槽101形成的像素电极10具有多个窄的分支电极。当然，第一凹槽101也可以为一个宽的凹槽，由此形成的像素电极10为板状电极。
例如，第一次刻蚀工艺可以采用感应耦合等离子体(ICP)刻蚀技术以SF6为刻蚀气体进行刻蚀。例如，可以通过调整刻蚀参数，使得第一盲孔170、第二盲孔171和第三盲孔的侧壁光滑，坡度平缓，刻蚀参数例如可以为ICP刻蚀设备的工作压力、功率以及刻蚀气体配比等。例如，第二次刻蚀工艺也可以采用感应耦合等离子体(ICP)刻蚀技术进行刻蚀。需要说明的是，第一次刻蚀工艺和第二次刻蚀工艺还可以采用其他的刻蚀技术，本实施例对此不做限制。
例如，第一通孔121和第二通孔131可以为台阶孔，第一通孔121可以包括远离衬底基板1一侧的第一部分1210和靠近衬底基板1一侧的第二部分1211，且第一部分1210的孔径大于第二部分1211的孔径，从而第一通孔121可以具有倒阶梯形状；第二通孔131可以包括远离衬底基板1一侧的第三部分1310和靠近衬底基板1一侧的第四部分1311，且第三部分1310的孔径大于第四部分1311的孔径，从而第二通孔131也可以具有倒阶梯形状。例如，如图2c所示，第三通孔141也可以为具有倒阶梯形状的台阶孔。例如，第一通孔121的第一部分1210、第二通孔131的第三部分1310、第一凹槽101和第二凹槽142的深度可以为500nm-800nm，例如，可以为600nm。
例如，如图4h所示，在第一绝缘层21上沉积一层导电层18，导电层18可以填充在第一通孔121、第二通孔131、第三通孔141、第一凹槽101和第二凹槽142中。例如，导电层18的厚度可以为40nm-200nm，例如，可以为100nm。
例如，沉积导电层18可以采用气相沉积法、磁控溅射法、真空蒸镀法或其他合适的处理形成。
例如，导电层18的材料可以为透明导电材料或其他合适的材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)和碳纳米管等。
例如，如图4i所示，对上述制备的阵列基板进行研磨工艺，以去除第一绝缘层21表面上的导电层18，且在第一通孔121、第二通孔131、第一凹槽101、第三通孔141和第二凹槽142保留导电层18，从而分别形成第一电极12、第二电极13、像素电极10和栅极14。第一电极12通过第一通孔121与有源层16电接触，第二电极13通过第二通孔131与有源层16电接触，栅极14通过第三通孔141与栅线11电连接。
例如，研磨工艺可以为化学机械抛光(CMP)工艺，CMP工艺通过比去除低处图形快的速度去除高处图形来获得均匀的表面，其能精确并均匀地将阵列基板抛光为所需的厚度和平坦度。例如，通过CMP工艺，将第一通孔121、第二通孔131、第三通孔141、第一凹槽101和第二凹槽142两侧边缘的凸起部分的厚度去除例如300nm左右，则第一绝缘层21表面上的导电层18将会被分成几个互相断连的区域，这样无需经过掩膜工艺，即可形成第一电极12、第二电极13、像素电极10和栅极14等，且它们相互之间彼此绝缘。
需要说明的是，第一通孔121、第二通孔131、第三通孔141、第一凹槽101和第二凹槽142两侧边缘的凸起部分采用研磨工艺被去除的厚度的大小与第一凹槽101和第二凹槽142的深度、导电层18的厚度正相关。例如，若第一凹槽101和第二凹槽142的深度为600nm，导电层18的厚度为100nm，则被去除的厚度可以大于100nm且小于700nm，从而保证导电层18被划分成相互绝缘的几个区域且在第一凹槽101和第二凹槽142内的导电层18可以部分或全部保留以形成像素电极10和栅极14。
例如，如图4j所示，可以对沉积有导电层18的第一绝缘层21进行研磨工艺后可以得到平坦表面。
需要说明的是，在通过一次构图工艺形成第一通孔121时，还可以形成与第一通孔121一体的第四凹槽；研磨工艺后，在第四凹槽保留导电层18以形成数据线15。
本示例中，有源层16采用透明的类石墨烯半导体制备，第一电极12、第二电极13、栅极14、数据线15和像素电极10采用透明导电材料制备，因此可以提高阵列基板的开口率。
在第一示例中，有源层16的材料为类石墨烯半导体，栅线11和公共电极20的材料为石墨烯，基于石墨烯掺杂，利用一道掩膜掩膜工艺形成有源层16、栅线11和公共电极20，从而其阵列基板可以利用两道掩膜工艺制备。
第二示例
本示例提供阵列基板的结构可以与第一示例基本相同。
需要说明的是，与第一示例不同，在本示例中，有源层16的材料例如还可以为非晶硅、多晶硅、氧化物半导体或其他合适的材料。多晶硅可以为高温多晶硅或低温多晶硅，氧化物半导体例如可以为氧化铟镓锌(IGZO)、氧化铟锌(IZO)、氧化锌(ZnO)或氧化镓锌(GZO)等。例如，栅线14和公共电极20的材料还可以为透明导电材料、金属材料或其他合适的材料，例如，该栅线14和公共电极20的材料可以为氧化铟锡(ITO)或氧化铟锌(IZO)等。
图5a-5b为本示例提供的阵列基板的制备方法的工艺流程图。
本示例提供的阵列基板的制备方法可以与第一示例的制备方法基本类似，在本示例中，如图5a所示，首先通过一道掩膜工艺，在衬底基板1上形成彼此绝缘的公共电极20和栅线11；如图5b所示，然后再利用一道掩膜工艺，在衬底基板1上形成有源层16，形成有源层16之后的步骤可以与第一示例相同，从而本示例的阵列基板可以利用三道掩膜工艺形成。
第三示例
在第一示例和第二示例中，阵列基板采用顶栅型薄膜晶体管，但是本实施例不限于此，阵列基板还可以采用底栅型薄膜晶体管，图6a为本示例提供阵列基板的平面示意图；图6b为沿图6a中线C-C'方向该阵列基板的一个示例的截面结构示意图；图6c为沿图6a中线C-C'方向该阵列基板的另一个示例的截面结构示意图。
例如，如图6a和6b所示，栅极14和栅线11设置在衬底基板1上。例如，栅线11和栅极14可以彼此电连接或一体形成，栅极14例如从栅线11分叉得到，由此扫描信号通过栅线11被施加到栅极14。该栅极14与有源层16在垂直于衬底基板1的方向上至少部分重叠。
例如，栅极14和栅线11的材料可以包括铜基金属、铝基金属、镍基金属或铬与其他金属的组合等。
例如，如图6a-6c所示，该阵列基板还包括第二绝缘层22，第二绝缘层22覆盖在栅极14和栅线11上，有源层16形成在第二绝缘层22上。例如，第二绝缘层22的材料可以包括氮化硅(SiNx)、氧化硅(SiOx)、氮氧化硅(SiNxOy)或其他合适的材料。例如，该第二绝缘层22可以为由上述材料中一种或几种构成的单层结构或多层结构。本示例阵列基板的其他各层的相对位置可以与第一示例相同，其他各层的材料制备也可以与第一示例相同，在此不再赘述。
需要说明的是，在本示例中，在垂直于衬底基板1的方向上，栅极14设置在有源层16下方且两者部分重叠，从而栅极14可以遮挡从衬底基板1一侧发出的光照射到有源层16上，减少薄膜晶体管的漏电流，改善薄膜晶体管的性能。
本示例提供的阵列基板的制备方法，首先通过一次掩膜工艺，在衬底基板1上形成栅极14和栅线11，接着在形成有栅极14和栅线11的衬底基板1上沉积一层绝缘层薄膜，以形成第二绝缘层22，然后在第二绝缘层22上形成有源层16，形成有源层16以及其余各层的步骤可以与第一示例相同。并且在形成有源层16之前、同时或之后，还可以形成公共电极20。在形成有源层16之前或之后形成公共电极20，则例如可以采用单独一道掩膜工艺来制备公共电极20；而在形成有源层16的同时形成公共电极20，则例如可以采用第一示例中的方式，通过石墨烯导体以及类石墨烯半导体来分别得到公共电极20和有源层16。
又或者，如图6c所示，可以在形成栅线11、栅极14的同时形成公共电极20，此时公共电极20与栅线11、栅极14形成在同一层上，也被第二绝缘层22所覆盖。
实施例二
图7a示出了本实施例提供的一种阵列基板的平面结构示意图；图7b为沿图7a中线D-D'方向该阵列基板的截面结构示意图；图7c为沿图7a中线E-E'方向该阵列基板的截面结构示意图。
需要说明的是，如图7a-7c所示，本实施例下面的描述中，阵列基板选取顶栅型薄膜晶体管进行说明，但本实施例的阵列基板还可以采用底栅型薄膜晶体管。
例如，本实施例提供的阵列基板中，像素电极10和公共电极20位于同一层上，即位于第一绝缘层21上，且彼此之间至少部分交错。例如，像素电极10和公共电极20均为梳状结构，且像素电极10的分支和公共电极20的分支彼此交替设置。
例如，公共电极20可以为采用透明导电材料、金属材料或其他合适的材料形成的单层或多层结构；例如，该公共电极20的材料可以包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟镓(IGO)、氧化镓锌(GZO)氧化锌(ZnO)、氧化铟(In2O3)、氧化铝锌(AZO)和碳纳米管等。
例如，该阵列基板还包括设置在衬底基板1上公共电极线23，公共电极线23被第一绝缘层21所覆盖，第一绝缘层21上还设置有暴露公共电极线23的第四通孔202，第一绝缘层21表面还设置有第三凹槽201，公共电极20设置在第三凹槽201和第四通孔202中，且通过第四通孔202与公共电极线23电连接。例如，公共电极线23的材料可以与栅线11相同。该实施例的阵列基板的其他各层的结构和制备材料可以与实施例一相同。
该实施例的阵列基板例如可以用于平面开关(IPS)型液晶面板。
例如，本实施例提供的阵列基板的制备方法，在形成栅线11时可以一同形成与栅线11平行延伸的公共电极线23，且在形成第一通孔121和第二通孔131时，还同时形成暴露公共电极线23的第四通孔202和在第一绝缘层21表面上的第三凹槽201，导电层18还可以填充在第三凹槽201和第四通孔202上，经过研磨工艺后，在第三凹槽201和第四通孔202中保留导电层18以形成公共电极20，公共电极20通过第四通孔202与公共电极线23电连接。本实施例的阵列基板其他各层的制备方法可以与实施例一相同，在此不再赘述。
例如，第三凹槽201可以包括多个分支凹槽，从而使得通过第三凹槽201形成的公共电极20具有多个分支电极。
实施例三
图8示出了本实施例提供的阵列基板的截面结构示意图。
需要说明的是，如图8所示，本实施例的阵列基板选取顶栅型薄膜晶体管进行说明，但本实施例的阵列基板还可以采用底栅型薄膜晶体管。
例如，本实施例提供的阵列基板中，公共电极20位于像素电极10之上。如图8所示，该阵列基板还包括钝化层30，钝化层30覆盖在第一电极12、第二电极13、栅极14和像素电极10上，公共电极20设置在钝化层30上。例如，公共电极20可以为狭缝电极。
例如，钝化层30的材料可以包括氮化硅(SiNx)、氧化硅(SiOx)、氮氧化硅(SiNxOy)或其他合适的材料。
该实施例的阵列基板例如也可以用于ADS型液晶面板。
本实施例提供的阵列基板的制备方法，在形成第一电极12、第二电极13、栅极14和像素电极10的第一绝缘层21上沉积一层绝缘层薄膜以形成钝化层30；然后在钝化层30上沉积透明导电材料并构图以形成公共电极20。该实施例的阵列基板的其他各层的制备方法可以与实施例一相同，在此不再赘述。
实施例四
本实施例提供了一种显示装置，其包括上述任一实施例的阵列基板。该显示装置可以为液晶显示装置、电子纸、有机发光二极管显示装置等显示器件以及包括这些显示器件的电视、数码相机、手机、手表、平板电脑、笔记本电脑、导航仪等任何具有显示功能的产品。
例如，该显示装置的一个示例为液晶显示装置，其中，阵列基板与对置基板彼此对置以形成液晶盒，在液晶盒中填充有液晶材料。该对置基板例如为彩膜基板。阵列基板的每个像素单元的像素电极用于施加电场对液晶材料的旋转的程度进行控制从而进行显示操作。在一些示例中，该液晶显示装置还包括为阵列基板提供背光的背光源。
该显示装置的另一个示例为有机电致发光显示装置(OLED)，其中，阵列基板上形成有有机发光材料叠层，每个像素单元的像素电极作为阳极或阴极用于驱动有机发光材料发光以进行显示操作。
该显示装置的再一个示例为电子纸显示装置，其中，阵列基板上形成有电子墨水层，每个像素单元的像素电极作为用于施加驱动电子墨水中的带电微颗粒移动以进行显示操作的电压。
本公开的实施例提供一种阵列基板的制备方法、阵列基板及显示装置。这些实施例的阵列基板的制备方法利用2次或3次掩膜工艺制作阵列基板，减少阵列基板制作所需的掩膜次数，简化了工艺制作流程，降低了工艺复杂度、制作成本，缩短了制备时间，提高了生产效率，提升了产品良率。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (14)

1.一种阵列基板的制备方法，包括：
提供衬底基板；
在所述衬底基板上依次形成有源层和覆盖所述有源层的第一绝缘层；
对所述第一绝缘层进行一次构图工艺，在所述第一绝缘层中形成暴露所述有源层的第一通孔和第二通孔，并在所述第一绝缘层表面上形成第一凹槽；
在构图后的所述第一绝缘层上形成导电层，所述导电层填充在所述第一通孔、所述第二通孔和所述第一凹槽中；
进行研磨工艺以去除所述第一绝缘层表面上的所述导电层，且在所述第一通孔、所述第二通孔和所述第一凹槽中保留所述导电层，从而分别形成源极、漏极和像素电极，
其中，所述一次构图工艺包括：
在所述第一绝缘层上涂覆第一光刻胶；
使用灰色调掩膜或半色调掩膜对所述第一光刻胶进行曝光，然后对曝光后的所述第一光刻胶显影，形成包括第一光刻胶全保留区域、第一光刻胶半保留区域和第一光刻胶全部去除区域的第一光刻胶掩膜层；
采用第一次刻蚀工艺形成第一盲孔和第二盲孔；
采用灰化工艺去除所述第一光刻胶半保留区域的第一光刻胶；
采用第二次刻蚀工艺在所述第一盲孔和第二盲孔位置形成暴露所述有源层的所述第一通孔和第二通孔，所述第一通孔为包括第一部分和第二部分的台阶孔，所述第二通孔为包括第三部分和第四部分的台阶孔；同时形成所述第一凹槽；
剥离所述第一光刻胶。
2.根据权利要求1所述的阵列基板的制备方法，其中，形成所述有源层包括：
在所述衬底基板上形成石墨烯导体层；
对所述石墨烯导体层进行处理，控制替代元素对应的原子取代所述石墨烯导体层中的部分碳原子，使所述石墨烯导体层转换成类石墨烯半导体层，从而在所述衬底基板上形成所述有源层。
3.根据权利要求2所述的阵列基板的制备方法，其中，所述石墨烯导体层包括彼此绝缘的第一区域和第二区域，所述第一区域被处理以形成所述有源层，所述第二区域用于形成栅线。
4.根据权利要求3所述的阵列基板的制备方法，其中，所述石墨烯导体层还包括与所述第一区域和所述第二区域绝缘的第三区域，所述第三区域用于形成公共电极。
5.根据权利要求2-4任一所述的阵列基板的制备方法，其中，对所述石墨烯导体层进行处理包括：
在所述石墨烯导体层上涂覆第二光刻胶；
使用所述灰色调掩膜或所述半色调掩膜对所述第二光刻胶进行曝光，然后对曝光后的所述第二光刻胶显影，形成包括第二光刻胶全保留区域、第二光刻胶半保留区域和第二光刻胶全部去除区域的第二光刻胶掩膜层；
刻蚀所述第二光刻胶半保留区域，暴露出所述石墨烯导体层；
在等离子条件下控制所述替代元素对应的原子取代所述石墨烯导体层中的部分碳原子形成所述有源层；其中，所述替代元素为第五主族元素、第六主族元素、第七主族元素和镧系元素包括的各种元素中的至少一种元素；
剥离所述第二光刻胶。
6.根据权利要求1所述的阵列基板的制备方法，还包括：
在形成所述第一绝缘层之前，在所述衬底基板上形成栅线；
在所述第一绝缘层中，在形成在所述第一通孔和所述第二通孔时，还形成暴露所述栅线的第三通孔和在所述第一通孔和所述第二通孔之间的第二凹槽，
进行所述研磨工艺之后，在所述第二凹槽和所述第三通孔中保留所述导电层以形成栅极，所述栅极通过所述第三通孔与所述栅线电连接。
7.根据权利要求1所述的阵列基板的制备方法，还包括：
在所述衬底基板上形成栅线和与所述栅线电连接的栅极；
形成覆盖所述栅线和所述栅极的第二绝缘层，其中，在所述第二绝缘层上形成所述有源层。
8.根据权利要求6或7所述的阵列基板的制备方法，还包括：
在形成所述栅线时一同形成公共电极。
9.根据权利要求1所述的阵列基板的制备方法，还包括：
形成钝化层以覆盖所述源极、所述漏极、所述像素电极，在所述钝化层上形成公共电极。
10.根据权利要求1所述的阵列基板的制备方法，还包括：
在所述第一绝缘层的表面上形成第三凹槽，所述第三凹槽中保留所述导电层以形成公共电极。
11.根据权利要求1所述的阵列基板的制备方法，其中，所述研磨工艺为化学机械抛光工艺，且对沉积有所述导电层的第一绝缘层进行所述研磨工艺后得到平坦表面。
12.一种根据权利要求1所述的阵列基板的制备方法制备的阵列基板，包括：
所述衬底基板；
设置在所述衬底基板上的所述有源层以及覆盖所述有源层的所述第一绝缘层，所述第一绝缘层具有暴露所述有源层的所述第一通孔和所述第二通孔以及设置在所述第一绝缘层表面上的所述第一凹槽，
分别设置在所述第一绝缘层的所述第一通孔和所述第二通孔中与所述有源层连接的所述源极和所述漏极，以及设置在所述第一凹槽中的所述像素电极；
设置在衬底基板上的公共电极和栅线，其中，所述公共电极和所述栅线被所述第一绝缘层覆盖，所述栅线、所述公共电极和所述有源层位于同一层；
设置在所述第一绝缘层中且暴露所述栅线的第三通孔和设置在所述第一绝缘层表面的第二凹槽，
设置在所述第二凹槽和所述第三通孔中的栅极，
其中，所述栅极通过所述第三通孔与所述栅线电连接，且所述栅极、所述源极、所述漏极和所述像素电极位于同一层。
13.根据权利要求12所述的阵列基板，其中，所述有源层为控制替代元素对应的原子取代石墨烯导体层中的部分碳原子形成的类石墨烯半导体层；所述替代元素为第五主族元素、第六主族元素、第七主族元素和镧系元素包括的各种元素中的至少一种元素。
14.一种显示装置，包括权利要求12或13所述的阵列基板。
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