CN106843351A - Adjustable voltage produces circuit - Google Patents
Adjustable voltage produces circuit Download PDFInfo
- Publication number
- CN106843351A CN106843351A CN201611261683.1A CN201611261683A CN106843351A CN 106843351 A CN106843351 A CN 106843351A CN 201611261683 A CN201611261683 A CN 201611261683A CN 106843351 A CN106843351 A CN 106843351A
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- Prior art keywords
- resistance
- voltage
- pmos transistor
- adjustable voltage
- produces circuit
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Control Of Electrical Variables (AREA)
Abstract
Circuit is produced the invention discloses a kind of adjustable voltage, the adjustable voltage generation circuit includes error amplifier, the first PMOS transistor, the second PMOS transistor, the 6th resistance, the 4th resistance, the 5th resistance, 6th resistance, the 4th resistance, the 5th resistance are sequentially connected in series, 4th resistance, the 5th resistance are all connected with the negative input of error amplifier, 4th resistance, the electrode input end of error amplifier all produce reference voltage to be connected with a band-gap reference, and the drain electrode of the first PMOS transistor, the grid of the second PMOS transistor are all connected with the 6th resistance.The present invention reduces production cost, increased the flexibility of the adjustment of output voltage numerical value.
Description
Technical field
The present invention relates to a kind of voltage generation circuit, adjustable voltage produces electricity under more particularly to a kind of N traps CMOS technology
Road.
Background technology
During IC design circuit, when the voltage of stabilization is used, the production method of existing reference voltage is to utilize mostly
The energy gap Eg of silicon constant characteristic, has negative temperature coefficient by the forward voltage of semiconductor diode or PN junction,
And two bipolar transistors are operated under unequal current density, the difference of their base emitter voltage with it is exhausted
Temperature is directly proportional.Influence by a certain suitable proportionality coefficient A to realize Positive and Negative Coefficient Temperature is offset each other, is such as schemed
Shown in 2, band-gap reference reference voltage such as following formula (1) is obtained：
VREF=VBE+A (VT ㏑ n) (1)
The reference voltage that VREF is intended to；VBE is the forward voltage of semiconductor diode or PN junction；A is an adjustment
Coefficient；VT ㏑ n are two differences of the base emitter voltage being operated under different current densities；N is both of the aforesaid electric current
The ratio of density；
Band-gap reference such as following formula (2)：
Vout=VBE2+ (VT ㏑ n) (R3+R2)/R3 (2)
Apparent this reference voltage VREF has a disadvantage that or weak point：
(1) in given power supply, this VREF can not possibly be infinitely great；
(2) find that the suitable current density ratio of searching is relatively difficult when wanting to obtain some VREF；
(3) find to find relatively difficult during a suitable adjustable coefficient A when wanting to obtain some VREF.
If have to by adjusting second resistance R2, the ratio of 3rd resistor R3 realize that this can cause R2, R3 ratio
Significantly change so as to cause the deterioration in accuracy of Vout because technique is mismatched；
If have to be realized by adjusting two conducting current densities of bipolar PNP transistor, its corresponding transmitting
The ratio of junction area will be very big, this as the process matching difficulty of PNP1 and PNP2 it is big and cause the precision of Vout compared with
Difference.
Shown in Fig. 3：The VREF produced based on band-gap reference produces Vo=VREF (R1+R2)/R1, is exactly defeated
Go out voltage can by adjusting second resistance R2, the ratio of 3rd resistor R3 adjusts.
Want not increase special processes step bipolar to realize earth-free NPN in the CMOS integrated circuits of N well techniques
Transistor npn npn (the first transistor Q1 and transistor seconds Q2 in Fig. 3) be it is highly difficult (note Fig. 2 in Q1 and Q2 be have 2
Individual pole ground connection), and transistor seconds Q2 requires that output high current is come if driving load, and it is suitable that this implements cost
It is high.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of adjustable voltage and produce circuit, and it reduces production cost, increase
The flexibility of the adjustment of output voltage numerical value is added.
The present invention is to solve above-mentioned technical problem by following technical proposals：A kind of adjustable voltage produces circuit, its
It is characterised by, the adjustable voltage generation circuit includes error amplifier, the first PMOS transistor, the second MOS transistor, the 6th
Resistance, the 4th resistance, the 5th resistance, the 6th resistance, the 4th resistance, the 5th resistance are sequentially connected in series, and the 4th resistance, the 5th resistance are all
Be connected with the negative input of error amplifier, the 4th resistance, error amplifier electrode input end all with a band-gap reference
Reference voltage connection, the grid of the first PMOS transistor, source electrode, the drain electrode of the second PMOS transistor is produced all to connect with the 6th resistance
Connect.
Preferably, the 4th resistance, the 5th resistance are all in parallel with a load.
Preferably, first PMOS transistor is output driving transistor, there is provided big output driving current.
Preferably, the 4th resistance, the 5th resistance are sampled to load voltage, and a part for load voltage is presented
Enter error amplifier for producing reference voltage to make comparisons with band-gap reference.
Preferably, one in error amplifier series connection onunit forced together with it drives error close to
Zero.
Preferably, the adjustable voltage produces circuit to use N well CMOS technologies.
Positive effect of the invention is：The present invention reduces production cost, increased the adjustment of output voltage numerical value
Flexibility, reduce transistor size, realize the reduction of shared silicon area so as to reach cost-effective purpose.
Brief description of the drawings
Fig. 1 is the circuit diagram that adjustable voltage of the present invention produces circuit.
Fig. 2 is the circuit diagram that existing band-gap reference is used.
Fig. 3 is the circuit diagram that reference voltage is produced based on band-gap reference.
Specific embodiment
Present pre-ferred embodiments are given below in conjunction with the accompanying drawings, to describe technical scheme in detail.
As shown in figure 1, adjustable voltage of the present invention produces the circuit to include error amplifier EA, the first PMOS transistor MP1, the
Two PMOS transistor MP2, the 6th resistance Rs, the 4th resistance R4, the 5th resistance R5, the 6th resistance Rs, the 4th resistance R4, the 5th electricity
Resistance R5 is sequentially connected in series, and the 4th resistance R4, negative inputs of the 5th resistance R5 all with error amplifier EA are connected, the 4th resistance
R4, the electrode input end of error amplifier EA all produce reference voltage VREF to be connected with a band-gap reference, a PMOS crystal
The grid of pipe MP1, source electrode, the drain electrode of the second PMOS transistor MP2 are all connected with the 6th resistance Rs.
4th resistance R4, the 5th resistance R5 are in parallel with a load, convenient use and output loading voltage.
First PMOS transistor MP1 is output driving transistor, there is provided big output driving current.4th resistance R4,
Five resistance R5 are sampled to load voltage Vo, and a part of feed-in error amplifier EA of load voltage Vo (is reversely input into
End) it is used to produce reference voltage VREF to make comparisons with band-gap reference.
A series connection onunit in error amplifier EA forces error close to zero together with it drives.If certain
Moment, load voltage Vo has a little change (Vo numbers of the caused Vo such as noise jamming, disturbance of load below or above setting
Value), it is desirable to the grid voltage of the first PMOS transistor MP1 adjusts to change the output of the first PMOS transistor MP1 in time
Driving current Io and load voltage Vo, this needs larger gain to realize, the second PMOS transistor MP2's and the 6th resistance Rs
Introducing seeks to realize this function.Such as certain moment output voltage is Vo '.If Vo '<Vo, through the 4th resistance R4, the 5th electricity
The numerical value Vf that resistance R5 sampling networks give EA is less than band-gap reference generation reference voltage VREF, now error amplifier EA outputs
Larger voltage Vo1 diminishes the degree that the second PMOS transistor MP2 is opened, and this causes Vo2 '<(Vo2 ' i.e. now is less than Vo2
Vo2 when normal), the grid Vo2 ' of the first PMOS transistor MP1 is connected by the 6th resistance Rs with output Vo ', Vo ' now
<The absolute value of the VGS1 (=Vo2 '-VI) of Vo, MP1 is bigger than normal when more normal, and the conducting electric current of MP1 is increased, this electric current for increasing
Load voltage Vo ' is pulled to the normal value Vo of setting；If Vo '>Vo, send through the 4th resistance R4, the 5th resistance R5 sampling networks
Band-gap reference being greater than to the numerical value Vf of error amplifier EA and producing reference voltage VREF, now error amplifier EA outputs are smaller
Second PMOS transistor MP2 opening degrees are become big by voltage, and the grid Vo2 ' of the first PMOS transistor MP1 can be opened degree change
The second big PMOS transistor MP2 pulls to input power VI higher, due to the first PMOS transistor MP1 VGS1 (=Vo2 '-
VI absolute value) is reducing, and the electric current of the output of the first PMOS transistor MP1 will reduce therewith, this electricity for reducing therewith
Stream can be such that output voltage Vo ' is drawn close to the direction of normal value Vo.During Vo '=Vo, circuit is in poised state, related device work
Make state and keep constant, node voltage and passage current keep constant.By the ratio for changing the 4th resistance R4, the 5th resistance R5
The load voltage Vo of output can be changed, the flexibility of the adjustment of output voltage numerical value is increased, Vo=is finally realized
VREF·(R4+R5)/R4。
Adjustable voltage of the present invention produces circuit to use N well CMOS technologies, and the electricity of adjustable voltage can be realized under N well CMOS technologies
Pressure produces circuit, reduces the lifting for increasing the production cost that processing step is brought.Circuit of the invention is simple, required component
Number is less, and benefit is the complexity for reducing integrated circuit, cost-effective, has reached reduction technique and has realized difficulty, and reducing increases
The raising of the production cost that processing step brings；Output voltage can be adjusted flexibly；Transistor size is reduced, is realized shared
The reduction of silicon area is so as to reach cost-effective purpose.
Particular embodiments described above, technical problem, technical scheme and beneficial effect to solution of the invention are carried out
Further describe, should be understood that and the foregoing is only specific embodiment of the invention, be not limited to
The present invention, all any modification, equivalent substitution and improvements within the spirit and principles in the present invention, done etc., should be included in this
Within the protection domain of invention.
Claims (6)
1. a kind of adjustable voltage produces circuit, it is characterised in that the adjustable voltage generation circuit includes error amplifier, first
PMOS transistor, the second MOS transistor, the 6th resistance, the 4th resistance, the 5th resistance, the 6th resistance, the 4th resistance, the 5th electricity
Resistance is sequentially connected in series, and the 4th resistance, the 5th resistance are all connected with the negative input of error amplifier, and the 4th resistance, error are amplified
The electrode input end of device all produces reference voltage to be connected with a band-gap reference, grid, source electrode, second of the first PMOS transistor
The drain electrode of PMOS transistor is all connected with the 6th resistance.
2. adjustable voltage as claimed in claim 1 produces circuit, it is characterised in that the 4th resistance, the 5th resistance all with
One load is in parallel.
3. adjustable voltage as claimed in claim 1 produces circuit, it is characterised in that first PMOS transistor is that output is driven
Dynamic transistor, there is provided big output driving current.
4. adjustable voltage as claimed in claim 1 produces circuit, it is characterised in that the 4th resistance, the 5th resistance are to negative
Carry voltage to be sampled, and a part of feed-in error amplifier of load voltage is used to produce reference voltage to make with band-gap reference
Compare.
5. adjustable voltage as claimed in claim 1 produces circuit, it is characterised in that a series connection in the error amplifier
Onunit forces error close to zero together with it drives.
6. adjustable voltage as claimed in claim 1 produces circuit, it is characterised in that the adjustable voltage produces circuit to use N
Well CMOS technology.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611261683.1A CN106843351A (en) | 2016-12-30 | 2016-12-30 | Adjustable voltage produces circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611261683.1A CN106843351A (en) | 2016-12-30 | 2016-12-30 | Adjustable voltage produces circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106843351A true CN106843351A (en) | 2017-06-13 |
Family
ID=59114189
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611261683.1A Pending CN106843351A (en) | 2016-12-30 | 2016-12-30 | Adjustable voltage produces circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106843351A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108646843A (en) * | 2018-08-06 | 2018-10-12 | 上海晟矽微电子股份有限公司 | Band-gap circuit and electronic equipment |
| CN109036301A (en) * | 2018-07-06 | 2018-12-18 | 武汉精测电子集团股份有限公司 | A kind of distal end voltage compensating method compensated automatically based on hardware circuit |
| CN114356007A (en) * | 2021-12-06 | 2022-04-15 | 武汉华中天经通视科技有限公司 | High-voltage high-power piezoelectric ceramic driving circuit |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009053783A (en) * | 2007-08-24 | 2009-03-12 | Ricoh Co Ltd | Overshoot suppression circuit and voltage regulator using overshoot suppression circuit, and electronic equipment |
| US20100327834A1 (en) * | 2009-06-27 | 2010-12-30 | Lowe Jr Brian Albert | Voltage regulator using depletion mode pass driver and boot-strapped, input isolated floating reference |
| CN103592991A (en) * | 2013-12-01 | 2014-02-19 | 西安电子科技大学 | Power limitation type protection circuit used for double-pole linear voltage regulator |
| CN103970176A (en) * | 2014-05-26 | 2014-08-06 | 万高(杭州)科技有限公司 | Low-dropout linear voltage-stabilizing circuit and application system thereof |
| CN204242021U (en) * | 2014-12-04 | 2015-04-01 | 成都信息工程学院 | A kind of low pressure difference linear voltage regulator driving large current load |
-
2016
- 2016-12-30 CN CN201611261683.1A patent/CN106843351A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009053783A (en) * | 2007-08-24 | 2009-03-12 | Ricoh Co Ltd | Overshoot suppression circuit and voltage regulator using overshoot suppression circuit, and electronic equipment |
| US20100327834A1 (en) * | 2009-06-27 | 2010-12-30 | Lowe Jr Brian Albert | Voltage regulator using depletion mode pass driver and boot-strapped, input isolated floating reference |
| CN103592991A (en) * | 2013-12-01 | 2014-02-19 | 西安电子科技大学 | Power limitation type protection circuit used for double-pole linear voltage regulator |
| CN103970176A (en) * | 2014-05-26 | 2014-08-06 | 万高(杭州)科技有限公司 | Low-dropout linear voltage-stabilizing circuit and application system thereof |
| CN204242021U (en) * | 2014-12-04 | 2015-04-01 | 成都信息工程学院 | A kind of low pressure difference linear voltage regulator driving large current load |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109036301A (en) * | 2018-07-06 | 2018-12-18 | 武汉精测电子集团股份有限公司 | A kind of distal end voltage compensating method compensated automatically based on hardware circuit |
| CN108646843A (en) * | 2018-08-06 | 2018-10-12 | 上海晟矽微电子股份有限公司 | Band-gap circuit and electronic equipment |
| CN114356007A (en) * | 2021-12-06 | 2022-04-15 | 武汉华中天经通视科技有限公司 | High-voltage high-power piezoelectric ceramic driving circuit |
| CN114356007B (en) * | 2021-12-06 | 2024-03-05 | 武汉华中天经通视科技有限公司 | High-voltage high-power piezoelectric ceramic driving circuit |
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| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170613 |
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| RJ01 | Rejection of invention patent application after publication |