CN106843023B - A kind of electric power data acquisition system based on FPGA - Google Patents
A kind of electric power data acquisition system based on FPGA Download PDFInfo
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- CN106843023B CN106843023B CN201510883570.4A CN201510883570A CN106843023B CN 106843023 B CN106843023 B CN 106843023B CN 201510883570 A CN201510883570 A CN 201510883570A CN 106843023 B CN106843023 B CN 106843023B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25314—Modular structure, modules
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Abstract
The present invention provides a kind of electric power data acquisition system based on FPGA, and the system comprises FPGA module, Analog Data Acquistion Module, network module, EEPROM module and switching value acquisition modules；The Analog Data Acquistion Module is for sending the FPGA module to after handling analog input signal；The switching value acquisition module is for sending the FPGA module to after handling on-off model；The FPGA module is for handling the analog input signal and the on-off model；The EEPROM module is used to store the configuration information of the network module, and the network module is for realizing system and extraneous transmission data.The present invention uses FPGA for master devices, substantially increase the speed of data acquisition and the precision of A/D conversion, the system has the characteristics that design is simple, at low cost, low in energy consumption and small in size, and live modification can be carried out according to different requirements, increases the success rate and flexibility of system design.
Description
Technical field
The present invention relates to a kind of electric power data acquisition systems, and in particular to a kind of electric power data acquisition system based on FPGA
System.
Background technique
China's rapid development of economy has driven every profession and trade to the wilderness demand of electric power, and therefore, there is an urgent need to supply electric power
The management of science should be carried out, basic link of the electric power data acquisition system as power supply and demand management plays an important role, electricity
The development of Force system made higher requirement the accuracy, real-time and reliability of electric power data acquisition system.
Traditional design method is to be converted using MCU or DSP by the A/D that software control data acquires, in this way will be frequent
The operation of interruption system, thus the data operation ability of attenuation systems, the speed of data acquisition is also restrained.With MCU and DSP
It compares, FPGA has a clear superiority in terms of Multi-Channel Parallel Acquisition.Single-chip microcontroller is influenced by instruction cycle and processing speed, difficult
It is controlled with the array formed to multiple channels, A/D, and its highway width is limited, for multi-channel data acquisition, is existed
The insufficient bottleneck of data bandwidth.According to multiple single-chip microcontroller parallel forms, then system complex, power consumption height, volume are caused again
It is big to wait fatal defects.Although the data acquisition of higher speed may be implemented in DSP, but while its speed improves, also increase and be
The various functions of the hardware cost of system, especially DSP need the operation by software to realize, time loss is in entire sampling
Between middle proportion it is bigger than normal, therefore its speed and inefficient for executing.
Summary of the invention
In order to overcome the above-mentioned deficiencies of the prior art, the present invention provides a kind of electric power data acquisition system based on FPGA,
The present invention increases the success rate and flexibility of system design, and have low in energy consumption, small in size etc. excellent by introducing FPGA module
Point.
In order to achieve the above-mentioned object of the invention, the present invention adopts the following technical scheme that:
A kind of electric power data acquisition system based on FPGA, the system comprises FPGA modules, analog data collection mould
Block, network module, EEPROM module and switching value acquisition module；The Analog Data Acquistion Module is for believing simulation input
Number processing after send the FPGA module to；The switching value acquisition module is described for sending to after handling on-off model
FPGA module；The FPGA module is for handling the analog input signal and the on-off model；The EEPROM module
For storing the configuration information of the network module, the network module is for realizing system and extraneous transmission data.
Preferably, the acquisition system further includes GPS module, and the GPS module is used for acquisition time information, provides serial ports
Pulse per second (PPS) and 10ms pulse.
Preferably, the Analog Data Acquistion Module is used to use 4 16 8 channel motor synchronizing analog converters, and
Integrated simulation inputs clamping protection, second order frequency overlapped-resistable filter, tracking hold amplifier, 16 Charge scaling successive approximations
ADC kernel, digital filter, 2.5V reference voltage source and buffering, high speed serialization and parallel interface.
Preferably, the network module has been internally integrated ICP/IP protocol stack, ethernet mac layer and PHY layer, supports 8
Independent Socket communication, transmission/reception buffer area of internal 128K byte quickly carries out data exchange, under Transmission Control Protocol, net
Network rate is up to 80Mbps.
Preferably, the FPGA module includes Data correction module, time control module, AD control module, acquisition measurement
Module, SDU group packet module, PDU group packet module, data migration module, ethernet control module and EEPROM control module, it is described
AD control module is for obtaining the analog input signal；The Data correction module is used for using correction factor to the simulation
Input signal obtains final analogue data after being corrected；The acquisition measurement module is for acquiring the on-off model；
The SDU group packet module is used for temporal information, the final analogue data and the switching value for providing the GPS module
Signal forms Service Data Unit SDU；Multiple SDU are formed a protocol Data Unit PDU by the PDU group packet module；
The data migration module is used to the PDU data packet content and data byte length being respectively written into content First Input First Output
Data FIFO and byte length First Input First Output Size FIFO；The ethernet control module is for obtaining network configuration letter
Cease simultaneously the PDU data is sent by network interface, the time control module sampled by counter controls AD and
The SDU data packet is sent to the timing of module；The EEPROM control module is used to read the configuration of the EEPROM module
Information and write command to the EEPROM module.
Preferably, the AD control module includes starting control module, for being configured according to different sample frequencys, to AD
Chip sends sampling marker pulse；Delay control module delays controlling for data, by collected data simultaneously, passes through delay
Control, allows it to be staggered in time；S2P module is used to AD sampled data carrying out serial-to-parallel 16 bit map.
Preferably, the acquisition measurement module includes frequency test module, according to 4 drive test frequency signals, passes through counter control
The Counter Value of 4 32bit is packaged and is written in the SDU data by frequency input signal processed；I/O channel signal control module,
For inputting the on-off model by the channel DI, exported by the channel DO.
Preferably, the EEPROM control module include EEPROM interface control module, EEPROM Data write. module and
EEPROM data read module, when EEPROM interface control module FPGA module and the EEPROM module interface
Module；The EEPROM Data write. module write enable effective when, by write order, write address and write data and pass through serial mode
It is written in the EEPROM module；When reading to enable effective, the EEPROM is written by serial mode in read command, read address
In module；The EEPROM data read module, for reading out AD correction factor and the net from the EEPROM module
The configuration information of network module.
Compared with prior art, the beneficial effects of the present invention are:
The present invention uses FPGA for master devices, substantially increases the speed of data acquisition and the precision of A/D conversion, this is
System has the characteristics that design is simple, at low cost, low in energy consumption and small in size, and live modification can be carried out according to different requirements, is increased
The big success rate and flexibility of system design.
Detailed description of the invention
Fig. 1 is a kind of structure chart of electric power data acquisition system based on FPGA provided by the invention
Fig. 2 is the structure chart of FPGA module in electric power data acquisition system provided by the invention
Specific embodiment
The present invention is described in further detail below in conjunction with the accompanying drawings.
As shown in Figure 1, a kind of electric power data acquisition system based on FPGA, including FPGA module, analog data collection
Module, network module, EEPROM module, switching value acquisition module and GPS module.
This system is using FPGA as core, and analog input signal is handled by Analog Data Acquistion Module, by digital signal
It exports to FPGA；Output is to FPGA after the on-off model of input is handled by switching value acquisition module.To acquisition in FPGA
Analog signal and on-off model handled, using GPS module acquisition time information, EEPROM module is used to store network
The configuration information of module realizes system and extraneous transmission data eventually by network interface.
1, FPGA module
As shown in Fig. 2, FPGA module includes: Data correction module, time control module, AD control module, acquisition measurement
Module, SDU group packet module, PDU group packet module, data migration module, ethernet control module and EEPROM control module.Data
Correction module obtains after analogue data is corrected AD control module using correction factor and obtains final analogue data.SDU
Group packet module forms the on-off model that the temporal information that GPS is provided, final analogue data and acquisition measurement module obtain
Service Data Unit (SDU).SDU data packet group at protocol Data Unit (PDU), is shifted mould by data by PDU group packet module
Block is by PDU data packet through giving ethernet control module.Ethernet control module obtains network configuration from EEPROM control module
Information, and PDU data is sent by network interface.
1.1, AD control module
This module is the control module of A/D chip, including starting control module, delay control module and S2P module.It realizes
Major function be: configured according to different sample frequency, send sampling marker pulse to A/D chip；AD sampled data is read,
And make serial-to-parallel 16 bit map；Data delay controlling, will simultaneously collected data, by delay control, allow they
It is staggered on time；The AD sampled data of non-natural sequence is converted into the AD sampling of natural order (ascending according to channel number)
Data.
1.2, measurement module is acquired
The module includes frequency test module and I/O channel signal control module.Frequency measuring block major function is basis
4 drive test frequency signals measure frequency input signal by counter controls, and the Counter Value of 4 32bit is packaged write-in SDU number
In；I/O channel signal control module major function is that the switching value data of input is inputted by the channel DI, is written into SDU number
According to being transmitted in packet；Host computer sends output switching value data and completes output switching value data output by the channel DO.
1.3, SDU group packet module
The module major function is to establish the pack arrangement of SDU data.SDU group packet module is measured from AD control module, acquisition
Module and GPS module obtain following data:
1) AD sampled data: AD sampled data, most 32 tunnels；
2) input switch amount: most 16 tunnels；
3) frequency counting: most 4 tunnels；
4) GPS time information: year, month, day, hour, min, second.
These data are continuously transmitted by 16 bit data bus.In fact, the module does not need to understand data content,
Control field is added after data only need to be received, by AD sampled data, switching value and frequency count data are merged into one
Continuous data block establishes complete SDU.Then SDU head file, data structure description field and GPS time information are added.
1.4, PDU group packet module
This module major function is to establish PDU.In order to improve efficiency of transmission, multiple SDU are formed into a PDU, PDU will make
It is transmitted for the load of IP network.The data of PDU specifically include that head file, serial number, length, SDU quantity, SDU length, PDU
Type.
Host computer can pass through the data structure of configuration change SDU at any time.It is so possible in a PDU comprising more
The different SDU of kind structure.Obviously, in this way for build on parsing PDU be it is unfavorable, realize difficulty it is larger.So being answered in design
This is avoided such happen.Guarantee that SDU integrality makes when configuration change until the counter of SDU is zero again first
Configuration take-effective.Guarantee PDU consistency, after parameter change, the SDU historical data of caching is packaged by next SDU when arriving
PDU.Next PDU is packaged according to the SDU that new parameter generates.
1.5, data migration module
This module major function is the First Input First Output (FIFO) called in IP core (IP kernel), according to PDU number
According to content design Data FIFO, Size FIFO is designed according to PDU data byte length；By generating corresponding FIFO write request
PDU data packet content and data byte length are respectively written into Data FIFO and Size FIFO by signal；According to network module
It sends data to need, generates corresponding FIFO read request in ethernet control module to read PDU data bag data and byte long
Degree.In this way design from practical Transmission Control Protocol send data packet messages angle say, can solve during sending datagram due to
Wait packet loss problem caused by acknowledgement character response overlong time.
1.6, ethernet control module
The initialization of network module is completed when the major function of the module, three steps of initialization: host interface setting,
The network information setting and inside TX/RX memory distribution, in the mif file of ROM it is middle configuration related register address with
Data.
Chip selection signal makes can control by writing enabled and reading in code, when write enable effective when, the address of register is written
And data；When reading to enable effective, the address of corresponding register is read.Due to the particularity of network module read-write sequence, writing
In operating process, piece selects CS that must at least continue 50ns low level.And after the completion of a write operation, it is necessary to select CS signal to set piece
High level continues at least 28ns, then carries out write operation next time or read operation again；During read operation, piece selects CS necessary
At least continue 65ns low level.And after the completion of a read operation, it is necessary to select CS signal to set high level piece and continue at least 28ns, so
Carry out write operation next time or read operation again afterwards.
1.7, EEPROM control module
The module includes EEPROM interface control module, EEPROM Data write. module and EEPROM reading data mould
Block.Wherein EEPROM interface control module is the interface module of FPGA and EEPROM module, the major function of realization be from
AD correction factor and the configuration information of W5300 are read out in EEPROM, are supplied to other modules and are used.Concrete function is as follows:
1) work clock, the chip selection signal of EEPROM are generated；
2) the busy Busy signal of EEPROM state is generated, control is written and read by Busy signal designation；
3) write enable effective when, by write order, write address and write data pass through serial mode be written EEPROM in；
4) when reading to enable effective, read command, read address are written in EEPROM by serial mode.
1.8, Data correction module
The module major function is that AD sampled data does operation with corresponding AD correction factor, and the data after correction are write
Enter in SDU data packet.The AD sampled data and correction factor of 16bit are subjected to data Bits Expanding first, are changed into 17bit；
Then suitable correction calculation parameter is selected, AD sampled data and correction factor are done into subtraction processing, after operation
Data value: a high position is 0, then according to positive correction parameter correction；A high position is 1, then according to negative correction parameter correction.School will finally be completed
In AD sampled data write-in SDU data packet after just.
1.9, time control module
This module is sampled by counter controls AD and SDU packet sending module timing.When network module reception is upper
When machine data are completed, AD sampled point count value is locked, and start to count sample counter, when count value reaches certain value
Afterwards, it generates AD sampling enable signal and gives AD_inf module；Regular hour delay is done according to AD sampling, is opened after AD starts sampling
Begin to count transmitting counter, after reaching regulation delay count value, generates and send enable signal, and carry out SDU data group packet.
2, Analog Data Acquistion Module
This module uses 4 A/D chips, realizes that 32 circuit-switched datas acquire function.A/D chip is a kind of 16 8 channel motor synchronizings
Analog-digital converter, on piece integrated simulation input clamping protection, second order frequency overlapped-resistable filter, tracking hold amplifier, 16 charges
Reallocation SAR ADC kernel, digital filter, 2.5V reference voltage source and buffering, high speed serialization and parallel interface.
AD7606 is powered using 5V single supply, it is no longer necessary to negative and positive dual power, and support the bipolar signal of really ± 10V or ± 5V
It is defeated.All channels can be sampled with the rate for being up to 200kSPS, while input terminal clamp protection circuits can be born most
The up to voltage of ± 16.5V.Have many advantages, such as that cost performance is high, precision is high, low energy consumption, conversion speed is fast, is particularly suitable for relay
Protect the measurement of data.
3, network module
In order to more intuitively monitor electric power data acquisition, system needs collected data to upload to control centre
PC, while also facilitating computer networking shared data.The inside modules are integrated with ICP/IP protocol stack, the ether of high mature
Network MAC layer and PHY layer etc. support 8 independent Socket communications, and transmission/reception buffer area of internal 128K byte can be quick
Data exchange is carried out, under Transmission Control Protocol, network rate highest can achieve 80Mbps.The module supports 8/16 data
Bus can be used parallel mode connected directly or indirectly and be attached.It is greatly reduced hardware interface design and
The workload of network programming, and the remote data communication system of reliable and stable operation may be implemented.
4, EEPROM module
EEPROM module selects the 25AA640 of Microchip company, which is 64K, using SPI universal serial bus
Transmit data, maximum clock frequency 1MHz.Wherein correction factor when storage AD sampling corrects adc data for FPGA.
5, on-off value data acquisition module
Since the IO voltage of FPGA is 3.3V, so on-off model, which need to carry out voltage via voltage conversion chip, converts it
It just can connect to FPGA afterwards.This system use 2 SN74ALVC164245 and 1 SN74AVC4T245PW chips realize 5V and
The voltage of 3.3V is converted, and realizes 16 input and output of way switch and 4 road frequency countings.
6, GPS module
GPS module as can arrangement, main function be temporal information is provided.GPS provides serial ports pulse per second (PPS) or 10ms
Pulse, FPGA safeguard that the markers of higher precision, resolution ratio are 10us accordingly, and precision is 1us.
Finally it should be noted that: the above embodiments are merely illustrative of the technical scheme of the present invention and are not intended to be limiting thereof, to the greatest extent
Invention is explained in detail referring to above-described embodiment for pipe, it should be understood by those ordinary skilled in the art that: still
It can be with modifications or equivalent substitutions are made to specific embodiments of the invention, and without departing from any of spirit and scope of the invention
Modification or equivalent replacement, are intended to be within the scope of the claims of the invention.
Claims (7)
1. a kind of electric power data acquisition system based on FPGA, which is characterized in that the system comprises FPGA modules, analog quantity number
According to acquisition module, network module, EEPROM module and switching value acquisition module；The FPGA module is adopted with the analog data
It is to be bi-directionally connected between collection module, the network module, the EEPROM module and the switching value acquisition module；The simulation
Amount data acquisition module is for sending the FPGA module to after handling analog input signal；The switching value acquisition module is used
Send the FPGA module to after handling on-off model；The FPGA module for handle the analog input signal and
The on-off model；The EEPROM module is used to store the configuration information of the network module, and the network module is used for
Realization system and extraneous transmission data；
The Analog Data Acquistion Module uses 4 16 8 channel motor synchronizing analog converters, and integrated simulation input clamp
Protection, second order frequency overlapped-resistable filter, tracking hold amplifier, 16 Charge scaling SAR ADC kernels, digital filterings
Device, 2.5V reference voltage source and buffering, high speed serialization and parallel interface.
2. acquisition system according to claim 1, which is characterized in that the acquisition system further includes GPS module, the GPS
Module is used for acquisition time information, provides serial ports pulse per second (PPS) or 10ms pulse.
3. acquisition system according to claim 1, which is characterized in that the network module has been internally integrated ICP/IP protocol
Stack, ethernet mac layer and PHY layer, support 8 independent Socket communications, and transmission/reception buffer area of internal 128K byte is fast
Speed carries out data exchange, and under Transmission Control Protocol, network rate is up to 80Mbps.
4. acquisition system according to claim 2, which is characterized in that the FPGA module includes Data correction module, time
Control module, AD control module, acquisition measurement module, SDU group packet module, PDU group packet module, data migration module, Ethernet
Control module and EEPROM control module, the AD control module is for obtaining the analog input signal；The Data correction
Module is for obtaining final analogue data after being corrected using correction factor to the analog input signal；The acquisition is surveyed
Amount module is for acquiring the on-off model；The SDU group packet module be used for the GPS module is provided temporal information,
The final analogue data and the on-off model form Service Data Unit SDU；The PDU group packet module is by multiple institutes
It states Service Data Unit SDU and forms a protocol Data Unit PDU；The data migration module is used for the protocol data list
The packet content and data byte length of first PDU is respectively written into content First Input First Output Data FIFO and byte length is first
Enter first dequeue Size FIFO；The ethernet control module is for obtaining network configuration information and passing through the PDU data
Network interface is sent, and the time control module is sampled by counter controls AD and the Service Data Unit SDU
Data packet is sent to the timing of module；The EEPROM control module is used to read the configuration information of the EEPROM module and writes
Enter order to the EEPROM module.
5. the acquisition system according to claim 4, which is characterized in that the AD control module includes starting control module, prolongs
Slow control module, S2P module；The starting control module, for being adopted to A/D chip transmission according to different sample frequency configurations
Sample marker pulse；The delay control module delays controlling for data, and collected data simultaneously are controlled by delay,
It is allowed to be staggered in time；The S2P module is used to AD sampled data carrying out serial-to-parallel 16 bit map.
6. acquisition system according to claim 5, which is characterized in that the acquisition measurement module include frequency test module,
I/O channel signal control module；Frequency test module is according to 4 drive test frequency signals, by counter controls frequency input signal, by 4
The Counter Value of a 32bit is packaged in the data that the Service Data Unit SDU is written；I/O channel signal control module, is used for
The on-off model is inputted by the channel DI, is exported by the channel DO.
7. acquisition system according to claim 5, which is characterized in that the EEPROM control module includes EEPROM interface control
Molding block, EEPROM Data write. module and EEPROM data read module, the EEPROM interface control module is described
The interface module of FPGA module and the EEPROM module；The EEPROM Data write. module write enable effective when, will write
It order, write address and writes data and is written in the EEPROM module by serial mode；Read enable effective when, by read command,
Read address is written in the EEPROM module by serial mode；The EEPROM data read module is used for from described
The configuration information of AD correction factor and the network module is read out in EEPROM module.
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| CN109521719B (en) * | 2019-01-14 | 2023-09-26 | 深圳灿态信息技术有限公司 | Intelligent collector |
| CN109782209A (en) * | 2019-03-11 | 2019-05-21 | 上海精密计量测试研究所 | Pulse power calibration factor calibration method |
| CN111722031A (en) * | 2020-05-13 | 2020-09-29 | 广州市扬新技术研究有限责任公司 | Direct current traction protection tester device based on FPGA |
| CN113742268B (en) * | 2021-09-14 | 2023-12-08 | 北京坤驰科技有限公司 | High-speed pulse acquisition system based on Ethernet optical fiber |
| CN114019850B (en) * | 2021-10-18 | 2024-07-12 | 中国舰船研究设计中心 | Ship auxiliary equipment IO signal modularization processing device |
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| CN101350036B (en) * | 2008-08-26 | 2010-09-15 | 天津理工大学 | High speed real-time data acquisition system |
| CN102253295B (en) * | 2011-06-03 | 2014-01-08 | 安徽继远电网技术有限责任公司 | High-speed data acquiring and digital signal processing board based on FPGA (Field Programmable Gate Array) |
| CN203054841U (en) * | 2012-12-20 | 2013-07-10 | 北汽福田汽车股份有限公司 | Data collection and transmission device |
| CN103389670A (en) * | 2013-07-31 | 2013-11-13 | 成都电业局双流供电局 | Data acquisition and power monitoring device for transformer station |
| CN104570855A (en) * | 2014-12-18 | 2015-04-29 | 文曲 | FPGA-based data acquisition system and method |
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