CN108241137A - A kind of elementary error of combining unit tester is traced to the source device - Google Patents
A kind of elementary error of combining unit tester is traced to the source device Download PDFInfo
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- CN108241137A CN108241137A CN201711362080.5A CN201711362080A CN108241137A CN 108241137 A CN108241137 A CN 108241137A CN 201711362080 A CN201711362080 A CN 201711362080A CN 108241137 A CN108241137 A CN 108241137A
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- 238000005070 sampling Methods 0.000 claims abstract description 25
- 230000001360 synchronised effect Effects 0.000 claims description 14
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 241001274660 Modulus Species 0.000 claims description 2
- 230000003321 amplification Effects 0.000 claims description 2
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 2
- 230000003287 optical effect Effects 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 20
- 238000012360 testing method Methods 0.000 abstract description 8
- 238000001514 detection method Methods 0.000 abstract description 6
- 230000005611 electricity Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
- G01R35/02—Testing or calibrating of apparatus covered by the other groups of this subclass of auxiliary devices, e.g. of instrument transformers according to prescribed transformation ratio, phase angle, or wattage rating
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Abstract
It traces to the source device the invention discloses a kind of elementary error of combining unit tester, feature is to include host computer, analog sampling module, the first synchronization module and the first network interface module, and analog sampling module includes current transformer module, voltage transformer module, A/D modular converters, the first relay module, the first FPGA module and the first STM32 microcontrollers；Advantage is when combining data detection unit testing instrument, value signal, the second sampling value signal and IEC61850 message signals are sampled by receive first be compared analyzing and processing by the first STM32 microcontrollers and host computer, so as to fulfill the Error Tracing ＆ process to being detected combining unit tester, single unit system is simple in structure, occupied space is smaller, at low cost and detection process is quick and convenient, and testing result precision is higher.
Description
Technical field
The present invention relates to a kind of electrotechnical instrument and meter detection device, especially a kind of elementary error of combining unit tester
It traces to the source device.
Background technology
Various regions power supply unit takes the links such as the type selecting of electronic mutual inductor and combining unit, examination, periodic detection
Measure or means have not yet been reached that perfect, comprehensively and accurately degree, some are replaced with relay protection tester, some uses divide row instrument
The method of device combination, it is few using the electronic mutual inductor of profession and combining unit tester.
Electronic mutual inductor and combining unit are examined using the electronic mutual inductor and combining unit tester of profession
During survey, testing result is more accurate, however each net, saves net company's DianKeYuan to the calibrating of such tester also without authority and complete
Method, the method for each standard of generally use combination, complicated integral structure, occupied space is more, and cost is higher, and tests
Journey is cumbersome, and precision sends difficult；It with the Integral calibrating apparatus of error of measurement method is core that national grid measurement centre, which is, uses rectangular co-ordinate
The equipment of the system calibration polar coordinate system of method, amplitude and phase there are error, to the Error Tracing ＆ process of calibrating installation compared with
For trouble.
Invention content
The technical problems to be solved by the invention be to provide it is a kind of it is simple in structure, occupied space is smaller, at low cost and error
The elementary error of process of tracing to the source combining unit tester easily and fast is traced to the source device.
Technical solution is used by the present invention solves above-mentioned technical problem：A kind of elementary error of combining unit tester
It traces to the source device, including host computer, analog sampling module, the first synchronization module and the first network interface module, the analog sampling mould
Block include current transformer module, voltage transformer module, A/D modular converters, the first relay module, the first FPGA module and
First STM32 microcontrollers, the host computer are connect with the first STM32 microcontrollers, the first STM32 microcontrollers
It is connect with first FPGA module by FSMC buses, the input terminal and outer synchronous signal of first synchronization module
Input terminal connects, and the output terminal of first synchronization module and the synchronous signal input end of first FPGA module connect
It connects, the input terminal of the current transformer module is connect respectively with outside by the three-phase current input terminal of checking device, described
The input terminal of voltage transformer module is connect respectively with outside by the three-phase voltage input terminal of checking device, the first FPGA moulds
Block sends first voltage switching command signal and the first current switching command signal, institute respectively to first relay module
The first relay module stated is used for the voltage transformer module according to the control of first voltage switching command signal to described
A/D modular converters send first voltage signal, first relay module be used for according to the first current switching instruct believe
Number control current transformer module sends second voltage signal, the A/D moduluss of conversion to the A/D modular converters
The output terminal of block is connected with the A/D control ports of first FPGA module, and the A/D modular converters send and receive
The corresponding first sampling value signal of first voltage signal to first FPGA module, the A/D modular converters are sent
Corresponding with the second voltage signal received second samples value signal to first FPGA module, first network interface
The input terminal of module is connect with outside by the IEC61850 message signals output terminals of checking device, first network interface module it is defeated
Outlet is connect with the digital signal input end of first FPGA module.
Further include three-phase program-controlled source module, the second synchronization module and the second network interface module, the three-phase program-controlled source module
Including the 2nd STM32 microcontrollers, the second FPGA module, D/A modular converters, three the first power amplifier modules of tunnel, three tunnels second
Power amplifier module, booster module, current lifting device module and the second relay module, the 2nd STM32 microcontrollers with
Second FPGA module is connected by FSMC buses, the D/A control output ends of second FPGA module mouthful with it is described
D/A modular converters input terminal connection, second FPGA module is according to pre-set configuration parameter to the D/A
Modular converter sends configuration signal, and the D/A modular converters send corresponding voltage respectively according to the configuration signal received
The second power amplifier module described in the first power amplifier module and three tunnels described in signal to three tunnels, described in three tunnels
Three-phase voltage input port of the voltage output port of one power amplifier module respectively with the booster module is connect, and three
The current output terminal mouth of the second power amplifier module described in road inputs respectively with the three-phase current of the current lifting device module
Port connects, and second FPGA module sends second voltage switching command signal respectively to second relay module
With the second current switching command signal, second relay module is according to the control of second voltage switching command signal
Booster module sends three-phase voltage signal to the voltage transformer module, and second relay module is according to second
The current switching command signal control current lifting device module sends three-phase current signal to the current transformer module, institute
The input terminal for the second synchronization module stated is connect with the synchronous signal output end of second FPGA module, and described second is same
The output terminal of step module is connect with the input terminal of first synchronization module, the input terminal of second network interface module and institute
The second FPGA module stated IEC61850 message signals output terminal connection, the output terminal of second network interface module with it is described
The first network interface module input terminal connection.When above structure is used to examine and determine passive combining unit tester, in three-phase program-controlled
Standard three-phase voltage signal, standard three-phase current signal and IEC61850 message signals are set in source module, by three-phase program-controlled source
The standard three-phase voltage signal, standard three-phase current signal and IEC61850 message signals of setting are respectively sent to be detected by module
Then passive combining unit tester and analog sampling module are observed and are shown on the software of passive combining unit tester is detected
Ratio difference and phase difference, compared with the ratio difference and phase difference shown on the related software that is set on host computer, from
And realize the Error Tracing ＆ process to being detected combining unit tester, wherein, itself synchronised clock side may be used in synchronizing signal
Formula can also use external synchronization clock mode, when using itself synchronised clock mode, the method for synchronization of analog sampling module
The method of synchronization for synchronism output B codes/PPS, and tested passive combining unit tester is to receive light B codes/PPS；If using
During external synchronization clock mode, analog sampling module and be detected the method for synchronization of passive combining unit tester for receive light B codes/
PPS。
First network interface module includes the first power grid mouth and the first smooth network interface, and the first power grid mouth is used for institute
External the first electric signal based on IEC61850 messages inputted by checking device of the first FPGA module transmission stated, described first
Light network interface is used to send external the first light based on IEC61850 messages inputted by checking device to first FPGA module
Signal.
Compared with prior art, the advantage of the invention is that when combining data detection unit testing instrument, by being detected combining unit
The three-phase current input terminal of tester inputs three-phase current signal respectively to the input terminal of current transformer module, is merged by tested
The input terminal of three-phase voltage input terminal to the voltage transformer module of unit testing instrument inputs three-phase voltage signal respectively, by first
Synchronization module receives the synchronizing signal of outer synchronous signal input terminal input and is sent to the first FPGA module, the first FPGA module
First voltage switching command signal is sent to the first relay module according to the synchronizing signal received and the first current switching refers to
Signal is enabled, the first relay module controls voltage transformer module to A/D modular converters according to first voltage switching command signal
First voltage signal is sent, the first relay module controls current transformer module to A/ according to the first current switching command signal
D modular converters send second voltage signal, and A/D modular converters send corresponding first according to the first voltage signal received and adopt
Sample value signal to the first FPGA module, A/D modular converters sends corresponding second sampling according to the second voltage signal received
Receive first sampling value signal and second are sampled value signal by value signal to the first FPGA module, then by the first FPGA module
The first STM32 microcontrollers are respectively sent to, tested combining unit tester is sent out by the first network interface module to the first FPGA module
IEC61850 message signals are sent, it is mono- that the IEC61850 message signals received are sent to the first STM32 by the first FPGA module
Piece machine, finally by the first STM32 microcontrollers and host computer by receive first sample value signal, the second sampling value signal and
IEC61850 message signals are compared analyzing and processing, so as to fulfill to be detected combining unit tester Error Tracing ＆ process,
Single unit system is simple in structure, occupied space is smaller, at low cost and detection process is quick and convenient, and testing result precision is higher.
Description of the drawings
Fig. 1 is the structural principle block diagram of embodiment one；
Fig. 2 is the part-structure functional block diagram of embodiment two.
Specific embodiment
The present invention is described in further detail below in conjunction with attached drawing embodiment.
Embodiment one：A kind of elementary error of combining unit tester is traced to the source device, including host computer 1, analog sampling mould
Block, the first synchronization module 2 and the first network interface module 3, analog sampling module include current transformer module 41, voltage transformer mould
Block 42, A/D modular converters 43, the first relay module 44, the first FPGA module 45 and the first STM32 microcontrollers 46, host computer 1
It being connect with the first STM32 microcontrollers 46, the first STM32 microcontrollers 46 are connect with the first FPGA module 45 by FSMC buses, the
The input terminal of one synchronization module 2 is connect with outer synchronous signal input terminal, the output terminal and the first FPGA moulds of the first synchronization module 2
The synchronous signal input end connection of block 45, the input terminal of current transformer module 41 is respectively with outside by the three-phase electricity of checking device 5
Input terminal connection is flowed, the input terminal of voltage transformer module 42 is connect respectively with outside by the three-phase voltage input terminal of checking device 5,
First FPGA module 45 sends first voltage switching command signal respectively to the first relay module 44 and the first current switching refers to
Signal is enabled, the first relay module 44 is used to control voltage transformer module 42 to A/D according to first voltage switching command signal
Modular converter 43 sends first voltage signal, and the first relay module 44 is used to control electricity according to the first current switching command signal
Current transformer module 41 sends second voltage signal, the output terminal of A/D modular converters 43 and the first FPGA to A/D modular converters 43
The A/D control ports of module 45 are connected, corresponding first sampling of the first voltage signal that A/D modular converters 43 send and receive
To the first FPGA module 45, the second voltage signal corresponding second that A/D modular converters 43 send and receive samples value signal
Value signal is to the first FPGA module 45, and the input terminal of the first network interface module 3 and outside are by the IEC61850 message signals of checking device 5
Output terminal connects, and the output terminal of the first network interface module 3 is connect with the digital signal input end of the first FPGA module 45.
When using that structure examines and determine active combining unit tester as described in embodiment one, first tested active
On combining unit tester set three phase sources export three-phase voltage value and three-phase electricity flow valuve, set measured number packet amplitude and
Phase, the three-phase voltage value and three-phase electricity flow valuve of tested active combining unit tester output are respectively from current transformer module 41
It is accessed with voltage transformer module 42, the first sampling value signal and first is exported after 43 analog-to-digital conversion of A/D modular converters and is adopted
Sample value signal samples the receive first sampling value signal and second to the first FPGA module 45, then by the first FPGA module 45
Value signal is respectively sent to the first STM32 microcontrollers 46, and tested combining unit tester passes through the first network interface module 3 to first
FPGA module 45 sends corresponding with measured number packet IEC61850 message signals, will be received by the first FPGA module 45
IEC61850 message signals are sent to the first STM32 microcontrollers 46, will finally be connect with host computer 1 by the first STM32 microcontrollers 46
The first sampling value signal, the second sampling value signal and the IEC61850 message signals received are compared analyzing and processing, observe
The ratio difference shown on the software of active combining unit tester and phase difference are detected, it is related soft to being set on host computer 1
The ratio difference and phase difference shown on part is compared, so as to fulfill to be detected combining unit tester Error Tracing ＆ process,
Wherein, the method for synchronization of the first synchronization module 2 and tested active combining unit tester is receives light B codes/PPS.
Embodiment two：Rest part is identical with embodiment one, the difference is that further including three-phase program-controlled source module,
Two synchronization modules 6 and the second network interface module 7, three-phase program-controlled source module include the 2nd STM32 microcontrollers 81, the second FPGA module
82nd, D/A modular converters 83, three tunnel the first power amplifier modules 84, three the second power amplifier modules of tunnel 85, booster module
86th, 87 and second relay module 88 of current lifting device module, the 2nd STM32 microcontrollers 81 and the second FPGA module 82 are total by FSMC
Line connects, and the D/A control output ends mouthful of the second FPGA module 82 are connect with the input terminal of D/A modular converters 83, the 2nd FPGA moulds
Block 82 sends configuration signal according to pre-set configuration parameter to D/A modular converters 83, and D/A modular converters 83 are according to receiving
Configuration signal send corresponding voltage signal respectively to three tunnel the first power amplifier modules 84 and three the second power amplifications of tunnel
Device module 85, the voltage output port of three the first power amplifier modules of tunnel 84 are defeated with the three-phase voltage of booster module 86 respectively
Inbound port connects, the current output terminal mouths of three the second power amplifier modules of tunnel 85 three-phase current with current lifting device module 87 respectively
Input port connects, and the second FPGA module 82 sends second voltage switching command signal and the to the second relay module 88 respectively
Two current switching command signals, the second relay module 88 control booster module 86 to send out according to second voltage switching command signal
Sending three-phase voltage signal, second relay module 88 is controlled according to the second current switching command signal to voltage transformer module 42
Current lifting device module 87 sends three-phase current signal to current transformer module 41, the input terminal and second of the second synchronization module 6
The input terminal of the synchronous signal output end connection of FPGA module 82, the output terminal of the second synchronization module 6 and the first synchronization module 2 connects
It connects, the input terminal of the second network interface module 7 is connect with the IEC61850 message signals output terminals of the second FPGA module 82, the second network interface
The output terminal of module 7 is connect with the input terminal of the first network interface module 3.
When using the passive combining unit tester of structure calibrating as described in embodiment two, set in three-phase program-controlled source module
Standard three-phase voltage signal, standard three-phase current signal and IEC61850 message signals are put, will be set by three-phase program-controlled source module
Standard three-phase voltage signal, standard three-phase current signal and IEC61850 message signals be respectively sent to it is tested it is passive merge it is single
First tester and analog sampling module, then observe on the software of passive combining unit tester is detected the ratio difference that shows and
Phase difference is compared with the ratio difference and phase difference shown on the related software that is set on host computer 1, so as to fulfill to quilt
The Error Tracing ＆ process of combining unit tester is examined, wherein, itself synchronised clock mode may be used in synchronizing signal, can also adopt
With external synchronization clock mode, when using itself synchronised clock mode, the method for synchronization of analog sampling module is synchronism output B
Code/PPS, and the method for synchronization of passive combining unit tester is detected to receive light B codes/PPS；If using external synchronization clock
During mode, analog sampling module and the method for synchronization for being detected passive combining unit tester are reception light B codes/PPS.
It is traced to the source device using the elementary error of the combining unit tester of structure described in above example, compatible electronic formula is mutual
The calibrating of sensor tester and combining unit tester, while but also as common electronic transducer calibration instrument and merge single
First tester tests electronic mutual inductor or combining unit.
Claims (3)
- The device 1. a kind of elementary error of combining unit tester is traced to the source, it is characterised in that including host computer, analog sampling module, First synchronization module and the first network interface module, the analog sampling module include current transformer module, voltage transformer mould Block, A/D modular converters, the first relay module, the first FPGA module and the first STM32 microcontrollers, the host computer and institute The first STM32 microcontrollers connection stated, the first STM32 microcontrollers pass through FSMC buses with first FPGA module Connection, the input terminal of first synchronization module are connect with outer synchronous signal input terminal, first synchronization module Output terminal is connect with the synchronous signal input end of first FPGA module, the input terminal point of the current transformer module Do not connect with outside by the three-phase current input terminal of checking device, the input terminal of the voltage transformer module respectively with external quilt The three-phase voltage input terminal connection of checking device, first FPGA module send the respectively to first relay module One voltage switching command signal and the first current switching command signal, first relay module are used for according to first voltage The switching command signal control voltage transformer module sends first voltage signal to the A/D modular converters, described The first relay module be used for the current transformer module according to the control of the first current switching command signal to described A/D modular converters send second voltage signal, the output terminal of the A/D modular converters and the A/ of first FPGA module D control ports are connected, the corresponding first sampling value signal of the first voltage signal that the A/D modular converters send and receive To first FPGA module, the second voltage signal corresponding second that the A/D modular converters send and receive is adopted Sample value signal is to first FPGA module, and the input terminal of first network interface module is with external by checking device IEC61850 message signals output terminal connects, the output terminal of first network interface module and the number of first FPGA module Word signal input part connects.
- The device 2. a kind of elementary error of combining unit tester according to claim 1 is traced to the source, it is characterised in that also wrap Three-phase program-controlled source module, the second synchronization module and the second network interface module are included, the three-phase program-controlled source module includes the 2nd STM32 Microcontroller, the second FPGA module, D/A modular converters, three the first power amplifier modules of tunnel, three tunnel the second power amplifier moulds Block, booster module, current lifting device module and the second relay module, the 2nd STM32 microcontrollers and described second FPGA module is connected by FSMC buses, D/A control output ends mouthful and the D/A moduluss of conversion of second FPGA module The input terminal connection of block, second FPGA module are sent out according to pre-set configuration parameter to the D/A modular converters Delivery confidence number, the D/A modular converters send corresponding voltage signal to three tunnels respectively according to the configuration signal received The second power amplifier module described in first power amplifier module and three tunnels, the first power amplification described in three tunnels Three-phase voltage input port of the voltage output port of device module respectively with the booster module is connect, and described in three tunnels Three-phase current input port of the current output terminal mouth of two power amplifier modules respectively with the current lifting device module is connect, institute The second FPGA module stated sends second voltage switching command signal and the second electric current respectively to second relay module Switching command signal, second relay module is according to the second voltage switching command signal control booster module Three-phase voltage signal is sent to the voltage transformer module, second relay module refers to according to the second current switching It is same to the current transformer module, described second that the current lifting device module for enabling signal control described sends three-phase current signal Step module input terminal connect with the synchronous signal output end of second FPGA module, second synchronization module it is defeated Outlet is connect with the input terminal of first synchronization module, the input terminal of second network interface module and described second The IEC61850 message signals output terminal connection of FPGA module, the output terminal of second network interface module and first net The input terminal connection of mouth mold block.
- The device 3. a kind of elementary error of combining unit tester according to claim 1 is traced to the source, it is characterised in that described The first network interface module include the first power grid mouth and the first smooth network interface, the first power grid mouth is used for the first FPGA Module sends external the first electric signal based on IEC61850 messages inputted by checking device, the described first smooth network interface be used for First FPGA module sends external the first optical signal based on IEC61850 messages inputted by checking device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711362080.5A CN108241137B (en) | 2017-12-18 | 2017-12-18 | Basic error traceability device of merging unit tester |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711362080.5A CN108241137B (en) | 2017-12-18 | 2017-12-18 | Basic error traceability device of merging unit tester |
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| Publication Number | Publication Date |
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| CN108241137A true CN108241137A (en) | 2018-07-03 |
| CN108241137B CN108241137B (en) | 2023-11-03 |
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| CN201711362080.5A Active CN108241137B (en) | 2017-12-18 | 2017-12-18 | Basic error traceability device of merging unit tester |
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| CN112363104A (en) * | 2020-12-07 | 2021-02-12 | 海南电网有限责任公司 | Online calibrator for electric energy meter |
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| Publication number | Publication date |
|---|---|
| CN108241137B (en) | 2023-11-03 |
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