CN106815627B - Semiconductor memory device and adapter - Google Patents

Abstract

An embodiment of the invention provides a semiconductor storage device and an adapter having a wireless antenna which can restrain the rise of the manufacturing cost and ensure enough communication performance. A semiconductor memory device according to one embodiment includes: the antenna comprises a first substrate, a nonvolatile memory, a memory controller, a first interface terminal, a first antenna and a communication controller. The first antenna is connected to the first substrate, and at least a part of the first antenna is located outside the first substrate when the first surface is viewed in plan, and at least a remaining part of the first antenna is located on the first substrate. The communication controller is configured to communicate with a second external device via the first antenna.

Description

Semiconductor memory device and adapter

This application claims priority to prior applications of Japanese patent application 2015-233522 (application date: 2015, 11, 30) and Japanese patent application 2016-100705 (application date: 2016, 5, 19). This application includes the entire contents of the prior application by reference to the prior application.

Technical Field

The present embodiment relates to a semiconductor storage device and an adapter.

Background

Antennas for communicating with external devices may be mounted in various devices. For example, antennas such as dipole antennas, loop antennas, and dielectric antennas are mounted on the device.

However, the antenna is mounted on the device, which may increase the manufacturing cost of the device.

Disclosure of Invention

Embodiments of the invention provide: a semiconductor memory device and an adapter having a wireless antenna which can secure sufficient communication performance while suppressing an increase in manufacturing cost.

A semiconductor memory device according to one embodiment includes: the antenna comprises a first substrate, a nonvolatile memory, a memory controller, a first interface terminal, a first antenna and a communication controller. The first substrate has a first surface and a second surface located on an opposite side of the first surface. The nonvolatile memory is mounted on the first surface. The memory controller is mounted on the first substrate, and is configured to: controlling the non-volatile memory. The first interface terminal is mounted on the first substrate and electrically connectable to a first external device. The first antenna is connected to the first substrate, and at least a part of the first antenna is located outside the first substrate when the first surface is viewed from above, and at least a remaining part of the first antenna is located on the first substrate. The communication controller is configured to: communicating with a second external device via the first antenna.

Drawings

Fig. 1 is a perspective view showing an SD card according to a first embodiment.

Fig. 2 is a block diagram showing an example of the configuration of a system including the SD card of the first embodiment.

Fig. 3 is a plan view of the SD card of the first embodiment with the top cover removed.

Fig. 4 is a sectional view of the SD card of the first embodiment taken along line F4-F4 of fig. 3.

Fig. 5 is a plan view of the SD card according to the second embodiment with the top cover removed.

Fig. 6 is a plan view showing the first substrate of the second embodiment with the sealing resin removed.

Fig. 7 is a bottom view of the first substrate according to the second embodiment.

Fig. 8 is a cross-sectional view schematically showing a part of the first substrate of the second embodiment along the line F8-F8 in fig. 6.

Fig. 9 is a cross-sectional view schematically showing a part of the first substrate of the second embodiment along the line F9-F9 in fig. 6.

Fig. 10 is a plan view showing a part of the first substrate of the second embodiment.

Fig. 11 is a plan view showing a part of the first substrate in one step of the manufacturing steps of the second embodiment.

Fig. 12 is a plan view of an SD card according to a modification of the second embodiment, with a top cover removed.

Fig. 13 is a plan view showing an SD card according to the third embodiment.

Fig. 14 is a plan view showing the first substrate according to the fourth embodiment.

Fig. 15 is a plan view showing a part of the first substrate according to the fourth embodiment.

Fig. 16 is a plan view showing a part of the first substrate in one step of the manufacturing process of the fourth embodiment.

Fig. 17 is a plan view showing a first substrate according to a modification of the fourth embodiment.

Fig. 18 is a plan view showing a part of a first substrate according to a modification of the fourth embodiment.

Fig. 19 is a plan view showing a part of the first substrate in one step of the manufacturing process of the modification of the fourth embodiment.

Fig. 20 is a bottom view of the SD card according to the fifth embodiment, with the bottom cover omitted.

Fig. 21 is a plan view showing an SD card according to the sixth embodiment.

Detailed Description

The semiconductor memory device and the adapter according to the embodiments will be described in detail below with reference to the drawings. The present invention is not limited to these embodiments.

In addition, a plurality of expressions may be written in the description of the constituent elements and/or the elements according to the embodiment. The constituent elements and the description thereof do not affect the use of other expressions not described. Further, the components and descriptions that do not describe a plurality of expressions do not affect the use of other expressions.

(first embodiment)

The first embodiment is explained below with reference to fig. 1 to 4. Fig. 1 is a perspective view showing an SD card 11 according to the first embodiment. The SD card 11 is one example of a semiconductor storage device. The semiconductor memory device may be, for example, a multimedia card or other device such as a USB flash memory. The semiconductor memory device may include a device or system having a semiconductor chip, and may include a wireless communication device such as a portable telephone.

As shown in the drawings, in the present specification, an X axis, a Y axis, and a Z axis are defined. The X, Y and Z axes are orthogonal to each other. The X-axis is defined along the width of SD card 11. The Y-axis is defined along the length of SD card 11. The Z-axis is defined along the thickness of the SD card 11.

A wireless communication technology is applied to the SD card 11 of the present embodiment. For example, Near Field Communication (NFC) using a frequency of 13.56MHz is applied to the SD card 11. Other wireless communication technologies may also be applied to the SD card 11.

The SD card 11 to which NFC is applied induces current in the wireless antenna by electromagnetic induction. Therefore, as described below, the SD card 11 has a radio antenna formed in a shape that can be called a coil shape, a spiral shape, or a spiral shape, for example.

Fig. 2 is a block diagram showing an example of the configuration of a system including the SD card 11 of the first embodiment. As shown in fig. 2, the SD card 11 is electrically connected to the host device 12. The SD card 11 is configured to wirelessly communicate with the wireless communication host device 13. The host device 12 is one example of a first external device. The wireless communication host apparatus 13 is one example of a second external apparatus. The host device 12 and the wireless communication host device 13 are, for example, a personal computer, a portable computer, a smart phone, a mobile phone, a server, a smart card, or other devices.

The SD card 11 has: an interface (I/F) terminal 22, a wireless antenna 23, a communication controller 24, a flash memory (flash memory) 25, a memory controller 26, and a capacitor 27. The I/F terminal 22 is one example of a first interface terminal. Flash memory 25 is one example of a non-volatile memory.

The communication controller 24 controls communication of the SD card 11 and the host device 12 and communication of the SD card 11 and the wireless communication host device 13. The communication controller 24 has a storage unit 24a and a voltage detector 24 b. The storage unit 24a may be an electronic component independent of the communication controller 24. In this case, the communication controller 24 is connected to the storage unit 24 a.

The communication controller 24 and the memory controller 26 may also be included in one electronic component. Further, for example, a plurality of electronic components, wirings, and programs may constitute the communication controller 24 and the memory controller 26. That is, the communication controller 24 and the memory controller 26 may be constituted by one electric element, a plurality of electric elements, or one or a plurality of electric elements and programs, respectively.

When the SD card 11 is electrically connected to the host device 12, the SD card 11 operates by power supplied from the host device 12. For example, the SD card 11 is written with data by the host device 12, or is read with data by the host device 12.

The SD card 11 can transmit and receive data to and from the wireless communication host apparatus 13 without being connected to other apparatuses such as the host apparatus 12 and the wireless communication host apparatus 13 and without being supplied with power from the other apparatuses. For example, the SD card 11 can transmit and receive data to and from the wireless communication host device 13 by using power generated (induced) by electromagnetic induction of the wireless antenna 23. The SD card 11 performs communication using NFC at a frequency of about 13.56MHz, for example, and transmits or receives data to and from the wireless communication host device 13. In this way, the SD card 11 can operate without receiving power supply from the host device 12.

The SD card 11 of the present embodiment transmits and receives data to and from the host device 12 along the SD interface. The SD card 11 may use another interface to transmit and receive data with respect to the host device 12. The SD card 11 transmits and receives data to and from the wireless communication host device 13 along the NFC interface. The SD card 11 may use another wireless communication interface to transmit and receive data to and from the wireless communication host device 13. The host device 12 and the wireless communication host device 13 may be the same device.

As shown in fig. 1, the SD card 11 also has a housing 31. The case 31 is made of, for example, a synthetic resin which is a non-magnetic and insulating material. The housing 31 may be made of other materials.

The housing 31 is formed in a substantially quadrangular box shape. The housing 31 may be formed in other shapes. The housing 31 has: a bottom cover 32, a top cover 33, and a lock switch 34. The bottom cover 32 is one example of a first cover. The top cover 33 is an example of a second cover.

Fig. 3 is a plan view of the SD card 11 according to the first embodiment with the top cover 33 removed. Fig. 3 shows a part of each of the communication controller 24, the flash memory 25, and the memory controller 26 as being missing. Fig. 3 shows the outline of the communication controller 24, flash memory 25, and memory controller 26 in the absence of a part by two-dot chain lines.

As shown in fig. 3, the SD card 11 further has a first substrate 41 and an antenna module 42. The housing 31 houses the first substrate 41, the antenna module 42, the communication controller 24, the flash memory 25, and the memory controller 26.

The communication controller 24, the flash memory 25, and the memory controller 26 are mounted on the first substrate 41. The antenna module 42 has a second substrate 45 and a first antenna pattern 46. In the first embodiment, the wireless antenna 23 of fig. 2 has a first antenna pattern 46. The first antenna pattern 46 is an example of a first antenna.

The SD card 11 is formed in a substantially quadrangular card shape and has four end portions 11a, 11b, 11c, 11 d. For convenience of explanation, the four ends 11a to 11d of the SD card 11 are referred to as a front end 11a, a rear end 11b, a left end 11c, and a right end 11d, respectively. The front end 11a, the rear end 11b, the left end 11c, and the right end 11d are names that are referred to based on the positions in fig. 3, and are not intended to limit the orientation and other features of the ends 11a, 11b, 11c, and 11 d.

The front end portion 11a is one end portion of the SD card 11 in the direction along the Y axis. The rear end portion 11b is the other end portion of the SD card 11 in the direction along the Y axis, and is located on the opposite side of the front end portion 11 a. The front end portion 11a and the rear end portion 11b extend in the direction along the X axis.

The left end portion 11c is one end portion of the SD card 11 in the direction along the X axis. The right end portion 11d is the other end portion of the SD card 11 in the direction along the X axis, and is located on the opposite side of the left end portion 11 c. The left end portion 11c and the right end portion 11d extend in the direction along the Y axis.

Fig. 4 is a sectional view of the SD card 11 of the first embodiment taken along line F4-F4 in fig. 3. As shown in fig. 4, the bottom cover 32 has a bottom surface 51 and a first inner surface 52. The bottom surface 51 is formed on one surface of the housing 31 exposed to the outside. The first inner surface 52 is located on the opposite side of the bottom surface 51.

In the bottom cover 32, a first recess 55, a second recess 56, and a plurality of terminal holes 57 are provided. Fig. 4 shows one of the plurality of terminal holes 57. The first and second recesses 55, 56 may be referred to as a recess, a receiving portion, or a fitting portion, respectively, for example. The first concave portion 55 and the second concave portion 56 are respectively provided on the first inner surface 52. In other words, the first and second recesses 55 and 56 are recessed portions from the first inner surface 52.

The first recess 55 and the second recess 56 are arranged so as to partially overlap in the Y-axis direction. The first recess 55 is closer to the distal end portion 11a than the second recess 56. Specifically, the end of the first recess 55 in the positive direction along the Y axis (the direction indicated by the arrow on the Y axis) is closer to the distal end 11a than the end of the second recess 56 in the positive direction along the Y axis.

In the first recess 55, the first substrate 41 is housed. A part of the first substrate 41 is located outside the first concave portion 55 in the thickness direction (direction along the Z axis) of the first substrate 41. In other words, the depth of the first recess 55 is shallower than the thickness of the first substrate 41. The depth of the first recess 55 may be larger than the thickness of the first substrate 41. In the second recess 56, the antenna module 42 is housed. A portion of the antenna module 42 may also be located outside of the second recess 56.

A plurality of terminal holes 57 are provided in the first recess 55. The plurality of terminal holes 57 are adjacent to the front end portion 11a and are arranged in the direction along the X axis. The plurality of terminal holes 57 extend from the bottom surface 51 through the bottom cover 32 across the first recess 55 of the first inner surface 52. In other words, the plurality of terminal holes 57 are opened in the first recess 55, respectively.

The top cover 33 is mounted on the bottom cover 32. The top cover 33 covers the first substrate 41 received in the first recess 55 and the antenna module 42 received in the second recess 56.

The top cover 33 has a top surface 61 and a second inner surface 62. The top surface 61 is formed on one surface of the housing 31 exposed to the outside. The top surface 61 is located on the opposite side of the bottom surface 51 if the housing 31 is explained. The second inner face 62 is located on the opposite side of the top face 61 if the top cover 33 is explained.

In the top cover 33, a third recess 65 is provided. The third recess 65 is provided in the second inner surface 62. By attaching the top cover 33 to the bottom cover 32, a part of the first substrate 41 located outside the first recess 55 is received in the third recess 65. The first concave portion 55 and the third concave portion 65 hold the first substrate 41 and restrict the movement of the first substrate 41.

The first substrate 41 is, for example, a Printed Circuit Board (PCB). The first substrate 41 may be another substrate such as a Flexible Printed Circuit (FPC). The first substrate 41 has a first surface 41a, a second surface 41b, and an end surface 41 c.

The first face 41a is formed substantially flat and faces the top cover 33. The second surface 41b is formed substantially flat and is located on the opposite side of the first surface 41 a. The second face 41b faces the bottom cover 32. The end face 41c connects an end edge of the first face 41a and an end edge of the second face 41 b.

As shown in fig. 3, the communication controller 24, the flash memory 25, and the memory controller 26 are mounted on the first surface 41a of the first substrate 41. At least one of the communication controller 24, the flash memory 25, and the memory controller 26 may be mounted on another portion of the first substrate 41. The communication controller 24 may be provided in another location such as the second substrate 45.

The first substrate 41 is formed in a substantially quadrangular plate shape. The first substrate 41 may be formed in other shapes. The length of the first substrate 41 in the direction along the Y axis is shorter than half the length of the housing 31 in the direction along the Y axis. The size of the first substrate 41 is not limited thereto, and for example, the length of the first substrate 41 in the direction along the Y axis may also be longer than half the length of the housing 31 in the direction along the Y axis.

As shown in fig. 4, the plurality of I/F terminals 22 are provided on the second surface 41b of the first substrate 41. Fig. 4 shows one of the I/F terminals 22. The plurality of I/F terminals 22 are adjacent to the front end portion 11a of the SD card 11 and are arranged in the direction along the X axis. The I/F terminals 22 are exposed to the outside of the housing 31 through the terminal holes 57 of the bottom cover 32.

The I/F terminal 22 of the present embodiment is an SD interface terminal and ensures electrical connection to the host device 12. In other words, the I/F terminal 22 can be electrically connected to the host device 12.

The second substrate 45 of the antenna module 42 is an FPC. Therefore, the second substrate 45 is thinner and more flexible than the first substrate 41. The second substrate 45 may be another substrate such as a PCB.

The second substrate 45 has a connection face 45 a. The attachment face 45a faces the top cover 33. A part of the connection surface 45a of the second substrate 45 faces a part of the second surface 41b of the first substrate 41. That is, when the first surface 41a is viewed in a plan view as shown in fig. 3, a part of the first substrate 41 overlaps a part of the second substrate 45.

The second substrate 45 is formed in a substantially square film shape. Therefore, the number of second substrates 45 cut from one large substrate can become larger. The second substrate 45 may be formed in other shapes.

The length of the second substrate 45 in the direction along the Y axis is longer than the length of the first substrate 41 in the direction along the Y axis. The size of the second substrate 45 is not limited thereto, and for example, the length of the second substrate 45 in the direction along the Y axis may be shorter than the length of the first substrate 41 in the direction along the Y axis. Further, the length of the second substrate 45 in the direction along the X axis is shorter than the length of the first substrate 41 in the direction along the X axis. The size of the second substrate 45 is not limited thereto, and for example, the length of the second substrate 45 in the direction along the X axis may be longer than the length of the first substrate 41 in the direction along the X axis.

The first antenna pattern 46 is mounted on the second substrate 45. The first antenna pattern 46 of the present embodiment is a wiring pattern formed on the second substrate 45. The first antenna pattern 46 may be formed of other materials such as insulated copper wires. The first antenna pattern 46 included in the wireless antenna 23 is a loop antenna formed in a coil shape. In the present embodiment, the first antenna pattern 46 is formed in a substantially quadrangular ring shape. The first antenna pattern 46 may have another shape such as a circular ring shape.

The first antenna pattern 46 as a loop antenna is formed of a conductor (wiring pattern) extending so as to surround an inner region of the first antenna pattern 46. In the first antenna pattern 46, the conductor may surround the inner region of the first antenna pattern 46, or may be wound to be shorter than one turn. In other words, the inside area of the first antenna pattern 46 and the outside area of the first antenna pattern 46 may also communicate. The conductor may also be wound in multiple turns. By applying a voltage to the end of the conductor, the first antenna pattern 46 generates a magnetic flux through the inside of the first antenna pattern 46. Further, a voltage is generated at the conductor by the magnetic flux passing through the inside of the first antenna pattern 46. Thus, the first antenna pattern 46 communicates with an external device by electromagnetic induction.

The second substrate 45 includes a first portion P1, a second portion P2, and a third portion P3. The first to third portions P1-P3, respectively, may also be referred to as regions or areas, for example.

The first portion P1 is a part of the second substrate 45 on which the first antenna pattern 46 is mounted. In detail, the first portion P1 is a portion of the second substrate 45 that overlaps the first antenna pattern 46 when the connection surface 45a of the second substrate 45 is viewed in plan as shown in fig. 3.

The second portion P2 is a portion of the second substrate 45 surrounded by the first portion P1. The third portion P3 is a portion of the second substrate 45 surrounding the first portion P1. In other words, the third portion P3 is located between the first portion P1 and the end 45b of the second substrate 45. The first portion P1 is located between the second portion P2 and the third portion P3.

As shown by the broken lines in fig. 3, on the second surface 41b of the first substrate 41, two first pads (pads) 71 and two second pads 72 are provided. The two first pads 71 are one example of a plurality of first pads, and may also be referred to as, for example, a pattern, a land, a conductor, or a metal portion. The two second pads 72 are each an example of a second pad, and may also be referred to as a pattern, a bonding region, a conductor, or a metal portion, for example.

As shown in fig. 2, a circuit C is provided on the first substrate 41. The circuit C comprises: the I/F terminal 22, the communication controller 24, the flash memory 25, the memory controller 26, the two first pads 71 of fig. 3, and various wiring and electronic components provided on the first substrate 41. That is, the circuit C is a portion provided on the first substrate 41 and through which a current supplied from the outside or induced inside the SD card 11 flows, for example.

As described above, the two first pads 71 of fig. 3 are included in the circuit C. On the other hand, the two second pads 72 are electrically independent from the circuit C, respectively. That is, when a current flows through the circuit C, no current flows through each of the second pads 72. Further, the second pad 72 may be connected to a ground line.

The first antenna pattern 46 of the antenna module 42 has two third lands 75. Further, the second substrate 45 has two fourth pads 76. The third and fourth pads 75, 76 are indicated by dashed lines in fig. 3. The two third pads 75 are an example of a plurality of third pads, and may also be referred to as a pattern, a bonding region, a conductor, or a metal portion, for example. The two fourth pads 76 are each an example of a fourth pad, and may also be referred to as a pattern, a bonding region, a conductor, or a metal portion, for example.

The two third pads 75 are two terminals of the first antenna pattern 46. In other words, one third pad 75 is provided at one end portion of the first antenna pattern 46. Another third pad 75 is provided at the other end portion of the first antenna pattern 46.

The two fourth pads 76 are electrically independent from the first antenna patterns 46, respectively. For example, when a current flows in the first antenna pattern 46, no current flows in each fourth pad 76. Further, the fourth pad 76 may be connected to the ground line.

One third pad 75 and one fourth pad 76 are respectively provided to the second portion P2 of the second substrate 45. Another third pad 75 and another fourth pad 76 are respectively provided to the third portion P3 of the second substrate 45. In this way, at least one of the two third pads 75 and the two fourth pads 76 is disposed in the second portion P2, and at least one of the two third pads 75 and the two fourth pads 76 is disposed in the third portion P3. The two third pads 75 and the two fourth pads 76 may be provided in the second portion P2 or the third portion P3.

The third pads 75 and the fourth pads 76 are provided on the connection surface 45a of the second substrate 45. The two third pads 75 are soldered to the corresponding first pads 71 of the first substrate 41 by solder 78 shown in fig. 4, respectively. The two fourth pads 76 are soldered to the corresponding second pads 72 of the first substrate 41 by solder 78, respectively.

The first antenna pattern 46 is electrically connected to the circuit C of the first substrate 41 by soldering the third pad 75 to the first pad 71. The first antenna pattern 46 is electrically connected to the communication controller 24, for example. On the other hand, the second pad 72 and the fourth pad 76, which are soldered to each other, are electrically independent from the circuit C and the first antenna pattern 46.

The antenna module 42 is mounted on the first substrate 41 by soldering the third and fourth lands 75 and 76 to the first and second lands 71 and 72, respectively. The third pads 75 are fixed to the corresponding first pads 71 by solder 78. The fourth pads 76 are fixed to the corresponding second pads 72 by solder 78.

When the first surface 41a of the first substrate 41 is viewed in plan as shown in fig. 3, a part of the first antenna pattern 46 overlaps the first substrate 41. When the first surface 41a is viewed in plan, a part of the first portion P1, a part of the second portion P2, and a part of the third portion P3 of the second substrate 45 overlap the first substrate 41, respectively.

When the first surface 41a of the first substrate 41 is viewed in plan as shown in fig. 3, a part of the inner side 46a of the first antenna pattern 46 is positioned outside the first substrate 41. In other words, when the first surface 41a is viewed in a plan view, a part of the inner side 46a of the first antenna pattern 46 does not overlap with the first substrate 41. The inner side 46a of the first antenna pattern 46 is a region surrounded by the annular first antenna pattern 46. The inner side 46a may also be empty. Additionally, objects may also be present on the interior side 46 a. When the first surface 41a of the first substrate 41 is viewed in plan, a part of the first antenna pattern 46 is also located outside the first substrate 41.

According to another expression, when the first surface 41a of the first substrate 41 is viewed in plan as shown in fig. 3, a part of the second portion P2 of the second substrate 45 is located outside the first substrate 41. When the first surface 41a is viewed in plan as shown in fig. 3, the inner side 46a of the first antenna pattern 46 substantially coincides with the second portion P2. The inner side 46a of the first antenna pattern 46 may be different from the second portion P2.

As shown in fig. 4, a portion of the inner side 46a of the first antenna pattern 46 located outside the first substrate 41 faces the bottom cover 32 and the top cover 33 in the direction along the Z-axis. In other words, a part of the inner side 46a of the first antenna pattern 46 located outside the first substrate 41 overlaps the bottom cover 32 and the top cover 33 made of resin in the direction along the Z axis.

As shown in fig. 3, a plurality of connection pads 81 are provided on the first surface 41a of the first substrate 41. Each of the plurality of connection pads 81 is an example of a connection pad, and may also be referred to as a pattern, a bonding region, a conductor, or a metal portion, for example. For each of the plurality of connection pads 81, the terminal of the corresponding communication controller 24, flash memory 25, or memory controller 26 is electrically connected by, for example, soldering. The connection pads 81 may be provided on the second surface 41 b.

The first leads 82 extend from the plurality of connection pads 81, respectively. The first lead 82 is covered with, for example, a first solder resist 83 of the first substrate 41. The first solder resist 83 forms at least a part of the first surface 41a of the first substrate 41. For the sake of explanation, the first lead 82 is indicated by a two-dot chain line in fig. 3.

The first leads 82 extend from the corresponding connection pads 81 toward the end surface 41c of the first substrate 41. In other words, the first lead 82 extends toward the edge of the first surface 41a of the first substrate 41. The first lead 82 may also have a plurality of bent portions. The end of the first lead 82 is spaced apart from the edge of the first surface 41 a.

In the first solder resist 83, a plurality of first openings 84 are provided. The first opening 84 is, for example, a notch extending from an end edge of the first surface 41a of the first substrate 41. The first opening 84 may be a hole.

When first surface 41a of first board 41 is viewed in plan as shown in fig. 3, the end of first lead 82 substantially overlaps the edge of first solder resist 83 where first opening 84 is formed. The end of the first lead 82 may be disposed at another position. The first opening 84 is used in the case of etching back (etch back) the first wire 82.

As shown in fig. 4, the sealing resin 86 covers the first surface 41a of the first substrate 41, the communication controller 24, the flash memory 25, and the memory controller 26. The sealing resin 86 is, for example, a synthetic resin, and is closely attached to the first surface 41a of the first substrate 41, the communication controller 24, the flash memory 25, and the memory controller 26. The sealing resin 86 covers the first opening 84 of the first solder resist 83. Fig. 3 shows the first substrate 41 without the sealing resin 86.

In the SD card 11 described above, the wireless antenna 23 (first antenna pattern 46) in fig. 2 generates a current or a voltage by electromagnetic induction when receiving a radio wave transmitted from the wireless communication host device 13. The wireless antenna 23 supplies the generated power to the communication controller 24.

The wireless antenna 23 of the present embodiment is set in accordance with a predetermined frequency or frequency band corresponding to NFC. Since the first antenna pattern 46 and a part of the inner side 46a of the wireless antenna 23 overlap the first substrate 41 in the direction along the Z axis, the frequency or the frequency band of the radio wave received by the first antenna pattern 46 may be shifted. The frequency or frequency band of the electric wave is adjusted by, for example, the capacitor 27.

The wireless antenna 23 transmits data received from the wireless communication host device 13 to the communication controller 24. The wireless antenna 23 transmits data received from the communication controller 24 to the wireless communication master unit 13.

The communication controller 24 can communicate with the wireless communication host device 13 via the wireless antenna 23. The communication controller 24 controls NFC using the wireless antenna 23 with respect to the wireless communication host device 13.

The communication controller 24 can be operated by the electric power generated in the wireless antenna 23 by the electromagnetic induction. The communication controller 24 receives a signal or data represented by a current or voltage generated in the wireless antenna 23 based on the radio wave from the wireless communication host device 13, and operates in accordance with the signal or data. For example, the communication controller 24 receives data from the wireless communication host device 13 via the wireless antenna 23 at a predetermined frequency corresponding to NFC during operation, and writes the data in the storage unit 24 a. Further, the communication controller 24 reads data written in the storage section 24a during operation, and transmits the data to the wireless communication host apparatus 13 via the wireless antenna 23. More specifically, the communication controller 24 is capable of performing communication realized by NFC when receiving a signal of a predetermined frequency corresponding to NFC via the wireless antenna 23.

When writing to the flash memory 25, the communication controller 24 transmits data received from the host device 12 via the I/F terminal 22 to the memory controller 26. When reading the flash memory 25, the communication controller 24 transmits data received from the memory controller 26 to the host device 12 via the I/F terminal 22.

In the case where the SD card 11 is electrically connected to the host device 12, for example, sufficient power is supplied to the communication controller 24. In this case, the communication controller 24 can write data received with NFC from the wireless communication host device 13 via the wireless antenna 23 into the flash memory 25 via the memory controller 26.

When sufficient power is supplied to the communication controller 24, the communication controller 24 may read data written to the flash memory 25 via the memory controller 26 to generate data and write the data to the storage section 24 a.

In the case where sufficient power is supplied to the communication controller 24, the communication controller 24 may read out a part or all of the data written into the flash memory 25 via the memory controller 26, and transmit the read-out data to the wireless communication host device 13 via the wireless antenna 23.

The storage unit 24a is a low power consumption memory operable by the power generated by the wireless antenna 23. The storage unit 24a is, for example, a nonvolatile memory. The storage unit 24a stores data based on control performed by the communication controller 24 or the memory controller 26. The storage unit 24a may be a memory for temporarily storing data. The storage unit 24a is, for example, an EEPROM (Electrically Erasable Programmable Read-Only Memory). The storage unit 24a may be another memory.

As described above, the communication controller 24 and the storage unit 24a can be operated by electric power induced in the wireless antenna 23 by radio waves from the wireless communication host apparatus 13. However, the communication controller 24 and the storage unit 24a may be operated by power supplied from the host device 12 when power is supplied from the host device 12 to the SD card 11.

The voltage detector 24b monitors the voltage supplied from the wireless antenna 23 to the communication controller 24, and continues to output a reset signal for communication by NFC until the voltage becomes a predetermined value. This can suppress abnormal activation and abnormal operation of communication by NFC.

The flash memory 25 is, for example, a NAND type flash memory. The nonvolatile Memory is not limited to the NAND flash Memory, and may be other nonvolatile memories such as a NOR flash Memory, a Magnetoresistive Memory (MRAM), a Phase Change Memory (PRAM), a resistance Change Memory (ReRAM), or a Ferroelectric Memory (FeRAM).

The memory controller 26 controls writing and reading of data to and from the flash memory 25. More specifically, when receiving a write command and data from the host device 12 via the I/F terminal 22 and the communication controller 24, the memory controller 26 writes the data into the flash memory 25. When receiving a read command from the host device 12 via the I/F terminal 22 and the communication controller 24, the memory controller 26 reads data from the flash memory 25 and transmits the data to the host device 12 via the communication controller 24 and the I/F terminal 22.

When the SD card 11 is electrically connected to the host device 12, for example, sufficient power is supplied to the memory controller 26. In this case, the memory controller 26 can write data received from the wireless communication host device 13 via the wireless antenna 23 and the communication controller 24 into the flash memory 25. If sufficient power is supplied to the memory controller 26, the memory controller 26 can transmit the data read from the flash memory 25 to the wireless communication host device 13 via the communication controller 24 and the wireless antenna 23.

The flash memory 25 and the memory controller 26 operate using power supplied from the host device 12.

The capacitor 27 has two terminals, for example. One terminal is electrically connected to one end of the wireless antenna 23. The other terminal is electrically connected to the other end of the wireless antenna 23.

The capacitor 27 adjusts the frequency of the current or voltage generated at the wireless antenna 23. More specifically, the capacitor 27 adjusts the shift in frequency of NFC generated by the first antenna pattern 46 and a part of the inner side 46a of the wireless antenna 23 overlapping with the first substrate 41 in the direction along the Z axis.

The data may be, for example, data transmitted and received between the wireless communication host device 13 and the SD card 11 along the NFC interface, characteristic data of data written in the flash memory 25, characteristic data received from the wireless communication host device 13 via the wireless antenna 23 by the communication controller 24, characteristic data relating to the flash memory 25, or characteristic data relating to the SD card 11. More specifically, the data may be, for example: a part (for example, first or last) of the image data written in the flash memory 25, thumbnail data, management information of the data written in the flash memory 25, a storage capacity of the flash memory 25, a remaining capacity of the flash memory 25, a name of a file written in the flash memory 25, a generation time of the data, shooting time data in the case where the data is image data, and the number of files written in the flash memory 25.

In the present embodiment, the write command and data from the host device 12 are received first by the communication controller 24 and then by the memory controller 26. This is because, first, the communication controller 24 determines whether the write instruction and the data are received from the host apparatus 12 or the wireless communication host apparatus 13, and switches the operation according to the determination result.

As described above, the SD card 11 transmits and receives data to and from the wireless communication host device 13 using power generated by electromagnetic induction of the wireless antenna 23. Specifically, in NFC, magnetic flux passes through the inner side 46a of the first antenna pattern 46 of the wireless antenna 23, thereby generating power at the first antenna pattern 46, and the communication controller 24 receives a signal or data represented by a current or voltage generated at the first antenna pattern 46. Further, the communication controller 24 generates a magnetic flux passing through the inner side 46a of the first antenna pattern 46 of the wireless antenna 23 to transmit data to the wireless communication host apparatus 13.

As shown in fig. 3, when the first surface 41a of the first substrate 41 is viewed in plan, a part of the inner side 46a of the first antenna pattern 46 is located outside the first substrate 41. Therefore, the magnetic flux passing through the inner side 46a of the first antenna pattern 46 can be suppressed from being influenced by the first substrate 41 and the communication controller 24, the flash memory 25, and the memory controller 26 mounted on the first substrate 41.

In the SD card 11 according to the first embodiment, the first antenna pattern 46 provided in the antenna module 42 is connected to the first substrate 41. In general, a loop antenna such as the first antenna pattern 46 is cheaper than a chip antenna. Therefore, for example, an increase in the manufacturing cost of the SD card 11 can be suppressed as compared with a case where a chip antenna is mounted on the first substrate 41 instead of the first antenna pattern 46. The range in which the first antenna pattern 46 as a loop antenna generates magnetic flux is larger than the range in which the chip antenna generates magnetic flux. Therefore, a large area in which communication by NFC can be performed can be ensured. When the first surface 41a is viewed in a plan view, at least a part of the first antenna pattern 46 is located outside the first substrate 41. This can suppress the influence of the magnetic flux generated by the first antenna pattern 46 on the electronic components such as the flash memory 25 mounted on the first substrate 41 and the pattern of the first substrate 41. Further, the first substrate 41 as a PCB can be miniaturized, and an increase in the manufacturing cost of the SD card 11 can be suppressed.

When the first surface 41a is viewed in a plan view, at least a part of the first antenna pattern 46 is located outside the first substrate 41. This can suppress the influence of the magnetic flux passing through the inner side 46a of the first antenna pattern 46 on the electronic components such as the flash memory 25 mounted on the first substrate 41 and the pattern of the first substrate 41.

The SD card 11 has a second substrate 45 different from the first substrate 41 on which the first antenna pattern 46 is mounted. Thus, the antenna module 42 having the first antenna pattern 46 mounted on the second substrate 45 can be manufactured in advance separately from the first substrate 41. By mounting the antenna module 42 on the first substrate 41, the first antenna pattern 46 can be easily connected to the first substrate 41.

The first antenna pattern 46 is electrically connected to the circuit C by soldering the plurality of third pads 75 to the plurality of first pads 71. Further, the fourth pads 76 of the second substrate 45 are soldered to the second pads 72 provided on the first substrate 41. Thereby, for example, the antenna module 42 can be more firmly mounted on the first substrate 41 than in the case where only the third land 75 is soldered to the first land 71. Further, even if the dimensional accuracy of the portions of the first substrate 41 and the antenna module 42, such as the first and second concave portions 55 and 56, is reduced, the electrical connection between the first substrate 41 and the first antenna pattern 46 can be ensured.

At least one of the plurality of third pads 75 and fourth pads 76 is disposed in the second portion P2, and at least another one of the plurality of third pads 75 and fourth pads 76 is disposed in the third portion P3. This can prevent the second substrate 45 from being detached from the first substrate 41, and also prevent the plurality of first pads 71 from being detached from the plurality of third pads 75.

The second substrate 45 is thinner than the first substrate 41. Thus, when the first antenna pattern 46 mounted on the second substrate 45 overlaps the first substrate 41, the SD card 11 can be prevented from becoming thick.

In general, the influence of the magnetic flux on the first antenna pattern 46 due to the overlapping of the first antenna pattern 46 and the first substrate 41 is smaller than the influence of the magnetic flux on the first antenna pattern 46 due to the overlapping of the inner side 46a of the first antenna pattern 46 and the first substrate 41. In the present embodiment, at least a part of the first antenna pattern 46 overlaps the first substrate 41 (is positioned on the first substrate 41) when the first surface 41a is viewed in a plan view. Therefore, when the first antenna pattern 46 and the inner side 46a of the first antenna pattern 46 are increased in size, the influence of the magnetic flux on the first antenna pattern 46 due to the first substrate 41 can be suppressed.

The bottom cover 32 is provided with a first recess 55 for accommodating the first substrate 41, an antenna module 42, and a second recess 56 for accommodating the first antenna pattern 46 mounted on the antenna module 42. Accordingly, by housing the first substrate 41 and the first antenna pattern 46 in the first and second recesses 55 and 56, the first substrate 41 and the first antenna pattern 46 can be easily positioned with respect to the housing 31.

(second embodiment)

Next, a second embodiment will be described with reference to fig. 5 to 11. In the following description of the embodiments, the components having the same functions as those of the components already described may be denoted by the same reference numerals as those of the components already described, and the description thereof may be omitted. Note that the plurality of components denoted by the same reference numerals are not limited to having the same functions and properties, and may have different functions and properties according to the respective embodiments.

Fig. 5 is a plan view of the SD card 11 according to the second embodiment with the top cover 33 removed. Similarly to the first embodiment, the first surface 41a of the first substrate 41, the communication controller 24, the flash memory 25, the memory controller 26, the first solder resist 83, and the first opening 84 are covered with a sealing resin 86. The sealing resin 86 of the second embodiment is one example of a covering member.

Fig. 6 is a plan view of the first substrate 41 according to the second embodiment, with the sealing resin 86 removed. Fig. 7 is a bottom view of the first substrate 41 according to the second embodiment. Fig. 8 is a cross-sectional view schematically showing a part of the first substrate 41 of the second embodiment along the line F8-F8 in fig. 6.

As shown in fig. 8, first substrate 41 includes first solder resist 83, base substrate 91, and second solder resist 92. The base substrate 91 may also be referred to as a base material, for example. The first substrate 41 may have more layers than those shown in fig. 8.

The base substrate 91 is an insulating plate made of paper or glass cloth covered with synthetic resin, for example. The base substrate 91 may be made of other materials. The base substrate 91 has a first forming surface 91a and a second forming surface 91 b. The first formation surface 91a is an example of a formation surface.

The first forming surface 91a is a substantially flat surface facing the top cover 33. The first formation surface 91a forms a part of the first surface 41a of the first substrate 41. The first formation surface 91a is covered with the first solder resist 83. The first solder resist 83 of the second embodiment is an example of a solder resist. The first solder resist 83 forms a part of the first surface 41a of the first substrate 41.

The second forming surface 91b is a substantially flat surface facing the bottom cover 32. The second forming surface 91b is located on the opposite side of the first forming surface 91 a. The second formation surface 91b forms a part of the second surface 41b of the first substrate 41. The second formation surface 91b is covered with a second solder resist 92. The second solder resist 92 forms a part of the second surface 41b of the first substrate 41.

As shown in fig. 6, the first substrate 41 of the second embodiment has a second antenna pattern 101. The second antenna pattern 101 is an example of a second antenna. The second antenna pattern 101 has: a first graphic 101a, a second graphic 101b, and a third graphic 101 c. The second pattern 101b is an example of the first wiring. The first pattern 101a and the third pattern 101c are examples of the second wiring.

The first pattern 101a and the third pattern 101c shown in fig. 7 are provided on the second forming surface 91b of the base substrate 91. In other words, the first pattern 101a and the third pattern 101c are mounted on the second surface 41b of the first substrate 41.

The second pattern 101b shown in fig. 6 is provided on the first formation surface 91a of the base substrate 91. In other words, the second pattern 101b is mounted on the first surface 41a of the first substrate 41.

As shown in fig. 7, one end of the first pattern 101a is electrically connected to one end of the second pattern 101b through a first via (via) 102. One end of the third pattern 101c is electrically connected to the other end of the second pattern 101b through the second via hole 103. Thus, the first to third patterns 101a, 101b, 101c form one continuous second antenna pattern 101. The second antenna pattern 101 extends adjacent to the end surface 41c of the first substrate 41. The second antenna pattern 101 extends adjacent to, for example, the right end portion 11d, the front end portion 11a, and the left end portion 11c of the SD card 11.

As shown in fig. 7, when the second surface 41b of the first substrate 41 is viewed in plan, at least a part of the second pattern 101b overlaps the I/F terminals 22. Similarly, when the first surface 41a of the first substrate 41 is viewed in plan, at least a part of the second pattern 101b overlaps the I/F terminals 22.

At the other end portion of the first pattern 101a, a fifth pad 105 is formed. At the other end of the third pattern 101c, a sixth pad 106 is formed. In other words, the fifth and sixth lands 105 and 106 are formed at both end portions of the second antenna pattern 101. The fifth and sixth pads 105 and 106 are disposed on the second surface 41b of the first substrate 41.

As shown in fig. 5, the first antenna pattern 46 of the antenna module 42 has: a first roll portion 46b and a second roll portion 46 c. The first and second coil portions 46b and 46c are portions of the first antenna pattern 46 formed in a coil shape.

The first antenna pattern 46 also has a seventh pad 107 and an eighth pad 108. The seventh pad 107 and the eighth pad 108 are provided on the connection surface 45a of the second substrate 45.

The seventh pad 107 is disposed at one end portion of the first roll portion 46b of the first antenna pattern 46. At the other end of the first roll portion 46b, a third land 75 is provided. The eighth pad 108 is disposed at one end portion of the second roll portion 46c of the first antenna pattern 46. At the other end of the second roll portion 46c, another third land 75 is provided.

As described above, the first antenna pattern 46 is constituted by a pattern formed in a coil shape. In the second embodiment, the pattern forming the first antenna pattern 46 is divided into the first roll portion 46b and the second roll portion 46 c.

The seventh pad 107 and the eighth pad 108 are disposed on the third portion P3 of the second substrate 45. At least one of the seventh pad 107 and the eighth pad 108 may be disposed in the second portion P2.

The seventh pads 107 of the second substrate 45 are soldered to the fifth pads 105 of the first substrate 41. Further, the eighth land 108 of the second substrate 45 is soldered to the sixth land 106 of the first substrate 41.

The first curl portion 46b of the first antenna pattern 46 is electrically connected to the first pattern 101a of the second antenna pattern 101 by soldering the seventh land 107 to the fifth land 105. Further, the eighth land 108 is soldered to the sixth land 106, whereby the second curl portion 46c of the first antenna pattern 46 and the third pattern 101c of the second antenna pattern 101 are electrically connected. In other words, the first antenna pattern 46 is electrically connected to the second antenna pattern 101.

The second antenna pattern 101 is connected to the first antenna pattern 46 to form a loop antenna 111 together with the first antenna pattern 46. That is, the loop antenna 111 has one third land 75, the first coil 46b, the seventh land 107, the fifth land 105, the first pattern 101a, the first via 102, the second pattern 101b, the second via 103, the third pattern 101c, the sixth land 106, the eighth land 108, the second coil 46c, and the other third land 75 electrically connected to each other. In the second embodiment, the wireless antenna 23 of fig. 2 has a loop antenna 111.

The loop antenna 111 is formed of conductors (the first antenna pattern 46 and the second antenna pattern 101) extending so as to surround an inner region of the loop antenna 111. In the loop antenna 111, the conductor may surround an inner region of the loop antenna 111, and may be wound shorter than one turn. In other words, the inner region of the loop antenna 111 and the outer region of the loop antenna 111 may also communicate. The conductor may be wound in multiple turns. By applying a voltage to the end of the conductor, the loop antenna 111 generates a magnetic flux passing through the inside of the loop antenna 111. Further, a voltage is generated in the conductor by the magnetic flux passing through the inside of the loop antenna 111. In this way, the loop antenna 111 communicates with an external device by electromagnetic induction.

As shown in fig. 6, the first substrate 41 has a plurality of first regions a1 and second regions a 2. The plurality of first regions a1 and second regions a2, respectively, may also be referred to as, for example, portions or ranges. The plurality of first and second regions a1 and a2 are respectively surrounded by the loop antenna 111.

Each of the plurality of first areas a1 is a part of the first substrate 41 that overlaps with at least one of the communication controller 24, the flash memory 25, and the memory controller 26 when the first surface 41a of the first substrate 41 is viewed in plan as shown in fig. 6.

The plurality of first regions a1 are surrounded by the second regions a2, respectively, and are spaced apart from the loop antenna 111. In other words, the communication controller 24, the flash memory 25, and the memory controller 26 are separated from the loop antenna 111. At least one of the communication controller 24, the flash memory 25, and the memory controller 26 may be adjacent to the loop antenna 111.

The second region a2 is a part of the first substrate 41 surrounded by the loop antenna 111 and separated from the plurality of first regions a1 when the first surface 41a is viewed in plan. In this way, a portion surrounded by the loop antenna 111 of the first substrate 41 is divided into a plurality of first regions a1 or second regions a 2. In a portion surrounded by the loop antenna 111 of the first substrate 41, another region different from the first and second regions a1 and a2 may be provided.

Fig. 9 is a cross-sectional view schematically showing a part of the first substrate 41 of the second embodiment along the line F9-F9 in fig. 6. As shown in fig. 9, a ground line 113 is provided on the first substrate 41. The ground line 113 may also be referred to as a ground pattern, a ground layer, or a conductor, for example. The ground line 113 is provided on the first formation surface 91a of the base substrate 91, for example. The ground line 113 may also be disposed on the second formation surface 91 b.

The ground lines 113 are respectively provided in the plurality of first areas a 1. In other words, the ground lines 113 are disposed outside the second area a 2. A part of the ground line 113 may be provided in the second region a 2. The ground line 113 may be provided in a portion of the first substrate 41 surrounding the loop antenna 111.

As shown in fig. 6, the first leads 82 extend from the plurality of connection pads 81, respectively. Fig. 6 shows the first lead 82 extending from the connection pad 81 partially omitted. Fig. 6 shows a part of each of the plurality of first leads 82 extending from the connection pad 81 hidden under the communication controller 24, the flash memory 25, and the memory controller 26.

The plurality of first leads 82 are provided on the first formation surface 91 a. Therefore, the first solder resist 83 covers the first lead 82. Fig. 6 shows the first lead 82 by a two-dot chain line for explanation.

Several first leads 82 extend from the corresponding connection pads 81 toward the second antenna pattern 101. The other first leads 82 extend toward the edge of the first surface 41a of the first substrate 41. The plurality of first leads 82 may have a plurality of bent portions, respectively.

Fig. 10 is a plan view showing a part of a first substrate 41 according to the second embodiment. As shown in fig. 10, the plurality of first leads 82 each have a first end 82 a. The first end portion 82a is an end portion of the first lead 82 extending from the connection pad 81. In other words, the first end 82a is located on the opposite side of the connection pad 81.

The first end portion 82a is separated from the other conductor including the second antenna pattern 101. Specifically, the first end 82a of the first lead 82 is separated from a conductive portion of a member or component different from the first lead 82. Therefore, the first lead 82 is electrically separated from the other electrical conductor different from the connection pad 81.

When first surface 41a of first substrate 41 is viewed in plan as shown in fig. 10, first end 82a substantially overlaps the edge of first solder resist 83 where first opening 84 is formed. The first end 82a may be disposed at other positions. The first opening 84 in the second embodiment is a hole. The first opening 84 may be a notch.

As shown in fig. 8, the first substrate 41 is mounted with wiring 114. The wiring 114 is one example of the first conductive pattern. The wiring 114 is provided on the first formation surface 91a of the base substrate 91, for example, and extends from the connection pad 81. In other words, the wiring 114 is connected to the connection pad 81.

The wiring 114 electrically connects the connection pad 81 and another conductor different from the connection pad 81. For example, the wiring 114 extending from the connection pad 81 on which the communication controller 24 is mounted electrically connects the connection pad 81 and the first pad 71. The wiring 114 extending from the connection pad 81 on which the flash memory 25 is mounted electrically connects the connection pad 81 and the connection pad 81 on which the memory controller 26 is mounted. The wiring 114 may connect the connection pad 81 and other electrical conductors such as the I/F terminal 22, the capacitor 27, other electronic components, or other terminals.

The second lead 115 extends from the second antenna pattern 101. The second lead 115 is provided on the first formation surface 91 a. Therefore, the first solder resist 83 covers the second lead 115. Fig. 10 shows the second lead 115 by a two-dot chain line for the sake of explanation.

The second lead 115 has a second end 115 a. The second end portion 115a is an end portion of the second lead 115 extending from the second antenna pattern 101. In other words, the second end portion 115a is located on the opposite side of the second antenna pattern 101.

The second end 115a is separated from the other conductor including the first end 82a of the first lead 82. Therefore, the second lead 115 is electrically separated from the other conductor different from the second antenna pattern 101. When first surface 41a of first substrate 41 is viewed in plan as shown in fig. 10, second end portion 115a substantially overlaps the edge of first solder resist 83 where first opening 84 is formed. The second end 115a may be disposed at another position.

The number of the first leads 82 is greater than the number of the second leads 115. At the edge of the first solder resist 83 where one first opening 84 is formed, the first end portions 82a of the plurality of first leads 82 and the second end portion 115a of one second lead 115 substantially overlap. As shown in fig. 10, when the first surface 41a of the first substrate 41 is viewed in plan, the first opening 84 overlaps a region between the first end 82a of the first lead 82 and the second end 115a of the second lead 115.

The third lead wire 116 also extends from the second antenna pattern 101. The third lead 116 is provided on the first formation surface 91 a. Therefore, the first solder resist 83 covers the third lead 116. Fig. 10 shows the third lead 116 by a two-dot chain line for explanation.

The third lead 116 is located between the second antenna pattern 101 and the end face 41c of the first substrate 41. The third lead 116 extends from the second antenna pattern 101 toward the end surface 41c of the first substrate 41. In other words, the third lead 116 extends from the second antenna pattern 101 to the edge of the first surface 41a of the first substrate 41.

The third lead 116 has a third end 116 a. The third end portion 116a is an end portion of the third lead wire 116 extending from the second antenna pattern 101. In other words, the third end portion 116a is located on the opposite side of the second antenna pattern 101.

In the first solder resist 83, a second opening 119 is provided. The second opening 119 is, for example, a notch extending from an end edge of the first surface 41a of the first substrate 41. The second opening 119 may also be a hole.

When the first surface 41a of the first substrate 41 is viewed in plan as shown in fig. 10, the third end portion 116a of the third lead 116 substantially overlaps the edge of the first solder resist 83 where the second opening 119 is formed. The third end 116a is separated from another conductor. Therefore, the third lead 116 is electrically separated from the other conductor different from the second antenna pattern 101. The third end portion 116a may be disposed at another position. The second opening 119 is covered with the sealing resin 86, similarly to the first opening 84.

As described above, in the present embodiment, the first to third leads 82, 115, and 116 are mounted on the first formation surface 91a of the first substrate 41. However, the first to third leads 82, 115, and 116 may be mounted on other portions such as the second formation surface 91 b.

As described above, the fifth land 105 and the sixth land 106 are formed at both end portions of the second antenna pattern 101. In other words, the fifth and sixth pads 105 and 106 are connected to the second antenna pattern 101, respectively.

The fifth pad 105 electrically connects the second antenna pattern 101 and the seventh pad 107. The sixth pads 106 electrically connect the second antenna pattern 101 and the eighth pads 108. As described above, the fifth and sixth lands 105 and 106 are an example of the second conductive pattern that electrically connects the second antenna pattern 101 and another conductor different from the second antenna pattern 101. The second conductive pattern is not limited to the fifth and sixth pads 105 and 106, and may be another conductive pattern.

A part of the method for manufacturing the first substrate 41 of the second embodiment will be described below. Note that the method for manufacturing the first substrate 41 is not limited to the following method, and other methods may be used.

Fig. 11 is a plan view showing a part of the first substrate 41 in one step of the manufacturing steps of the second embodiment. Before the plurality of connection pads 81 are formed on the first substrate 41, the first plated leads L1 and the second plated leads L2 shown in fig. 11 are provided on the first formation surface 91a of the base substrate 91.

The base substrate 91 provided with the first and second plating leads L1 and L2 is formed with a plurality of connection pads 81 and other plurality of pads by electrolytic plating. The first and second plated leads L1, L2 are provided, for example, as: for forming a plurality of connection pads 81 and other a plurality of pads by electrolytic plating.

The first plated leads L1 include the plurality of first leads 82 and second leads 115 described above. In other words, the plurality of first leads 82 and the second leads 115 connected to each other form the first plated lead L1.

The first plating lead line L1 extends from the second antenna pattern 101, has a plurality of bifurcated portions, and is connected to the plurality of connection pads 81. In other words, the connection pads 81 are formed by electrolytic plating at the plurality of ends of the first plating leads L1.

The second plated leads L2 include the third leads 116 described above. The second plated lead line L2 extends from the second antenna pattern 101 to the end face 41c of the first substrate 41. The second plating lead L2 is electrically connected to the connection pads 81 through the second antenna pattern 101 and the first plating lead L1. In other words, the second plated lead line L2 is equal in potential to each of the second antenna pattern 101, the first plated lead line L1, and the plurality of connection pads 81. The second plated lead line L2, the second antenna pattern 101, the first plated lead line L1, and the plurality of connection pads 81 may have different potentials.

When the connection pad 81 is formed by electrolytic plating, the second plating lead L2 is connected to a power supply. For example, before the plurality of first substrates 41 are cut out from one collective substrate, leads connected to the second plating leads L2 of each first substrate 41 are mounted on the collective substrate including the plurality of first substrates 41. The collective substrate is held by a jig connected to a power supply, and a voltage is applied to the second plating lead L2 through the lead. The connection pads 81 are formed by electrolytic plating by applying a voltage to the first plated lead L1 through the second plated lead L2 and the second antenna pattern 101. The aggregate substrate may also be referred to as a frame, tape, sheet, or aggregate.

A portion of the first plating leads L1 is exposed through the plurality of first openings 84. The first opening 84 exposes, for example, a portion (bifurcated portion) where the plurality of first leads 82 and the second lead 115 are connected. A portion of the second plating lead L2 is exposed through the second opening 119.

When the plurality of connection pads 81 are formed, a part of the first plating lead L1 and a part of the second plating lead L2 are removed by, for example, etch-back. The first plated lead L1 is divided into a plurality of first leads 82 and second leads 115 by being etched back through the first opening 84. The second plated lead L2 is etched back by passing through the second opening 119 to form the third lead 116. Thereby, the plurality of connection pads 81 are electrically separated from the second antenna pattern 101.

Next, the communication controller 24, the flash memory 25, and the memory controller 26 are electrically connected by soldering to the plurality of connection pads 81 that have been formed. The sealing resin 86 covers the first surface 41a of the first substrate 41, the communication controller 24, the flash memory 25, the memory controller 26, the first solder resist 83, the first opening 84, and the second opening 119. The first substrate 41 is manufactured as described above.

In the SD card 11 according to the second embodiment, the second antenna pattern 101 forming one loop antenna 111 together with the first antenna pattern 46 is mounted on the first substrate 41. Thus, compared to the case where the SD card 11 has only the first antenna pattern 46, the range in which the magnetic flux is generated from the first antenna pattern 46 and the second antenna pattern 101 is expanded in the direction along the X axis and the direction along the Y axis, and the range in which communication by the magnetic flux can be performed is expanded. Further, since the magnetic flux captured by the loop antenna 111 is larger than the magnetic flux captured by the first antenna pattern 46, the range in which communication can be performed by the magnetic flux is also enlarged in the direction along the Z axis. Thus, the range of communication enabled by the magnetic flux is expanded, and the communication characteristics of the SD card 11 are improved.

The second antenna pattern 101 includes a second pattern 101b mounted on the first formation surface 91a and first and third patterns 101a and 101c mounted on the second formation surface 91 b. Since a part of the second antenna pattern 101 is mounted on the second forming surface 91b, the range of the first surface 41a on which various electronic components such as the flash memory 25 can be mounted can be suppressed from decreasing.

The first substrate 41 has: a first region a1 on which electronic components such as a flash memory 25 are mounted and which is provided with a ground line 113, and a second region a2 separated from the first region a 1. By providing the second region a2, the influence of the magnetic flux generated by the communication controller 24, the flash memory 25, the memory controller 26, and the ground line 113 on the one loop antenna 111 formed by the first antenna pattern 46 and the second antenna pattern 101 is reduced.

The first lead 82 extends from a connection pad 81 to which an electronic component such as the flash memory 25 is connected. The first lead 82 is electrically separated from the other electrical conductors. On the other hand, the second lead 115 extends from the second antenna pattern 101. The second lead 115 is electrically separated from the other conductor. The first and second leads 82 and 115 are connected to each other in, for example, the manufacturing process of the SD card 11 to form a first plated lead L1. In this case, by applying a voltage to the first and second leads 82 and 115 through the second antenna pattern 101, the connection pad 81 can be formed at the end of the first lead 82 by electrolytic plating. After the connection pad 81 is formed, the first lead 82 and the second lead 115 are divided. In this way, on the first substrate 41 on which the second antenna pattern 101 is formed, it is possible to perform: the connection pad 81 is formed by electrolytic plating of the first and second leads 82 and 115.

The first solder resist 83 is provided with a first opening 84 that overlaps a region between the first end 82a of the first lead 82 and the second end 115a of the second lead 115 when the first formation surface 91a is viewed in plan. Thus, in the manufacturing process of the SD card 11, the first lead 82 and the second lead 115 connected to each other can be divided by, for example, etching back through the first opening 84.

The sealing resin 86 covers the flash memory 25, the memory controller 26, and the first opening 84 of the first solder resist 83. Thus, the sealing resin 86 protects the flash memory 25, the memory controller 26, and the first forming surface 91a, and can suppress damage to the flash memory 25, the memory controller 26, and the first forming surface 91 a.

Between the second antenna pattern 101 and the end face 41c of the first substrate 41, the third lead 116 extends from the second antenna pattern 101. The third lead 116 is electrically separated from the other electrical conductors. The third lead 116 can be connected to a power supply, for example, in the manufacturing process of the SD card 11. Therefore, the connection pad 81 is formed by electrolytic plating by applying a voltage to the first lead 82 through the third lead 116, the second antenna pattern 101, and the second lead 115. After the connection pads 81 are formed, the third leads 116 are separated from the leads of the collective substrate. In this way, on the first substrate 41 on which the second antenna pattern 101 is formed, it is possible to perform: the connection pad 81 is formed by electrolytic plating of the first and second leads 82 and 115.

The number of the plurality of first leads 82 is greater than the number of the plurality of second leads 115. The plurality of first leads 82 are connected to a corresponding one of the second leads 115, for example, in the manufacturing process of the SD card 11. The plurality of first leads 82 having first ends 82a separated from the other conductor and the second leads 115 having second ends 115a separated from the other conductor are formed by removing the portions where the plurality of first leads 82 and the second leads 115 are connected, for example, by etching back. Thus, the number of second leads 115 corresponding to the number of first leads 82 does not need to be provided, and an increase in the number of second leads 115 can be suppressed. Therefore, the presence of the conductor at the inner side of the second antenna pattern 101 can be reduced, and the influence on the magnetic flux of one loop antenna 111 formed by the first antenna pattern 46 and the second antenna pattern 101 can be suppressed.

Next, a modification of the second embodiment will be described with reference to fig. 12. Fig. 12 is a plan view of the SD card 11 according to a modification of the second embodiment, with the top cover 33 removed.

As shown in fig. 12, the end surface 41c of the first substrate 41 includes a front end surface 41ca, a rear end surface 41cb, a left end surface 41cc, and a right end surface 41 cd. The front end surface 41ca, the rear end surface 41cb, the left end surface 41cc, and the right end surface 41cd are referred to based on the positions in fig. 12, and the directions and other features of the end surfaces 41ca, 41cb, 41cc, and 41cd are not limited.

The front end face 41ca is one end face of the first substrate 41 in the direction along the Y axis. The I/F terminal 22 is adjacent to the front end face 41 ca. The rear end face 41cb is the other end face of the first substrate 41 in the direction along the Y axis, and is located on the opposite side of the front end face 41 ca. The front end surface 41ca and the rear end surface 41cb extend in the direction along the X axis.

The left end face 41cc is one end face of the first substrate 41 in the direction along the X axis. The right end face 41cd is the other end face of the first substrate 41 in the direction along the X axis, and is located on the opposite side of the left end face 41 cc. The left end surface 41cc and the right end surface 41cd extend in the direction along the Y axis.

The second antenna pattern 101 extends adjacent to the front end surface 41ca, a part of the rear end surface 41cb, the left end surface 41cc, and the right end surface 41cd of the first substrate 41. The second antenna pattern 101 is open at a portion adjacent to the rear end face 41cb of the end face 41 c. In other words, the inner region of the second antenna pattern 101 and the outer region of the second antenna pattern 101 communicate with each other at a portion adjacent to the rear end face 41cb of the end face 41 c. The shape of the second antenna pattern 101 is not limited to this.

In the modification of the second embodiment, the plurality of first leads 82 extend from the connection pads 81 toward the rear end surface 41cb of the first substrate 41, respectively. In other words, the first lead 82 extends in a direction away from the front end face 41ca adjacent to the I/F terminal 22.

When the first surface 41a of the first substrate 41 is viewed in plan as shown in fig. 12, the first end 82a of the first lead 82 substantially overlaps the rear end surface 41 cb. That is, the first lead 82 extends from the connection pad 81 to the rear end face 41 cb. The first end portion 82a is separated from the other conductor including the second antenna pattern 101.

On the extension lines of several first lead lines 82 extending from the connection pads 81, there are sometimes second antenna patterns 101. In this case, the first lead 82 has at least one bent portion and extends on a path that does not cross the second antenna pattern 101. In other words, the first lead 82 extends so as to avoid the second antenna pattern 101 and is separated from the second antenna pattern 101.

In the modification of the second embodiment, all the first leads 82 do not cross the second antenna pattern 101 and extend from the connection pads 81 to the rear end face 41 cb. The first lead 82 is electrically separated from other electrical conductors different from the connection pad 81.

At least one connection pad 81 is located closer to any one of the front end surface 41ca, the left end surface 41cc, and the right end surface 41cd than the rear end surface 41 cb. That is, the first lead 82 extends from the connection pad 81 not to the front end face 41ca, the left end face 41cc, or the right end face 41cd, which is the closest end face 41c, but to the rear end face 41 cb.

In the modification of the second embodiment, the first opening 84 is not provided in the first solder resist 83. Although the first opening 84 may be provided in the first solder resist 83, as described above, the first end 82a of the first lead 82 overlaps the rear end surface 41cb when the first surface 41a is viewed in plan.

The rear end face 41cb of the first substrate 41 faces the antenna module 42 having the first antenna pattern 46. When the first surface 41a is viewed in plan, at least a part of the rear end surface 41cb overlaps the antenna block 42.

The second antenna pattern 101 is connected to the first antenna pattern 46. In order to make the inner region of the second antenna pattern 101 larger, the second antenna pattern 101 extends adjacent to the front end face 41ca, the left end face 41cc, and the right end face 41cd, which are separated from the first antenna pattern 46. Therefore, the first lead 82 extends from the connection pad 81 to the rear end surface 41cb, so that the first lead 82 is easily arranged on a path away from the second antenna pattern 101. The first lead 82 may extend from the connection pad 81 to the distal end surface 41ca, the left end surface 41cc, or the right end surface 41 cd.

A part of the first lead 82 overlaps the inner side 46a of the first antenna pattern 46 when the first surface 41a is viewed in plan. The first lead 82 is thinner than the conductor forming the first antenna pattern 46. Therefore, the first lead 82 can be suppressed from affecting the magnetic flux of the first antenna pattern 46.

In the SD card 11 according to the modification of the second embodiment, all the first leads 82 are separated from the second antenna pattern 101 and extend from the connection pads 81 to the end surface 41c of the first substrate 41. Accordingly, it is not necessary to electrically separate the first lead 82 and the second antenna pattern 101 by etching back, and an increase in the manufacturing process and manufacturing cost of the SD card 11 can be suppressed.

(third embodiment)

The third embodiment is explained below with reference to fig. 13. Fig. 13 is a plan view showing an SD card 11 according to the third embodiment. As shown in fig. 13, the SD card 11 of the third embodiment has a micro SD card 131 and an adapter (adapter) 132. The micro SD card 131 mounted on the adapter 132 is used as a full-size SD card 11.

The micro SD card 131 is an example of a semiconductor device, and may also be referred to as, for example, a device, a module, a unit, a medium, and a component. The semiconductor device may be other devices such as a mini SD card or a USB flash memory.

The micro SD card 131 includes: a first substrate 41, a plurality of I/F terminals 22, a communication controller 24, a flash memory 25, and a memory controller 26. The I/F terminal 22 of the third embodiment is a micro SD interface terminal.

The micro SD card 131 is electrically connected to the host device 12 as a single body, and can be written with data by the host device 12 or read with data by the host device 12.

The micro SD card 131 has two first connection terminals 135. The first connection terminal 135 is provided on the second surface 41b of the first substrate 41, similarly to the I/F terminal 22. The two first connection terminals 135 are adjacent to the plurality of I/F terminals 22, for example. The first connection terminal 135 may be disposed at other positions.

The two first connection terminals 135 are electrically connected to the communication controller 24, for example. The two first connection terminals 135 are exposed to the outside through, for example, openings, respectively. The first connection terminal 135 may be included in the I/F terminal 22.

The adapter 132 is an adapter for causing the micro SD card to function as a reader/writer for a full-size SD card. The adapter may also be: an adapter for use, for example, in making a small SD card function as a reader/writer for a full-size SD card; an adapter for making an SD card, a mini SD card, or a mini SD card function as a USB connector; an adapter for using the a terminal of USB as a connector of another USB standard such as type C; and the like.

The adapter 132 has: a case (case)141, a plurality of full-size I/F terminals 142, a loop antenna 143, and two second connection terminals 144. The full-size I/F terminal 142 is one example of the second interface terminal. The loop antenna 143 is an example of a first antenna and an antenna.

The cassette part 141 is made of, for example, a synthetic resin which is a non-magnetic and insulating material. The box portion 141 may be made of other materials. The box portion 141 is formed in a substantially rectangular box shape.

The full-size I/F terminal 142 is an SD interface terminal. The full-size I/F terminal 142 is provided at one end of the box portion 141 in the Y-axis direction. The plurality of full-size I/F terminals 142 are arranged in a direction along the X-axis. The full-size I/F terminal 142 is exposed outside the box portion 141.

The cartridge 141 is provided with an insertion port 141 a. The insertion port 141a is open at the other end of the box portion 141 in the direction along the Y axis. The micro SD card 131 is detachably attached to the adapter 132 by being inserted into the insertion port 141 a.

By inserting the micro SD card 131 into the insertion port 141a, the plurality of I/F terminals 22 of the micro SD card 131 are electrically connected to the corresponding full-size I/F terminals 142. The I/F terminal 22 can be electrically connected to the host device 12 via the full-size I/F terminal 142.

The loop antenna 143 is housed in the box portion 141. The loop antenna 143 is formed in a shape that may be referred to as a coil, a spiral, or a spiral, for example. In the present embodiment, the loop antenna 143 is formed of a copper wire wound in a coil shape. A copper wire wound in a coil shape is one example of a wound conductor. The loop antenna 143 may be, for example, a pattern formed on a substrate.

The box portion 141 includes an outer frame region 151 and an inner region 152. The outer frame region 151 is a frame-shaped portion adjacent to the peripheral end 141b of the box portion 141. The inner region 152 is surrounded by the outer frame region 151.

The loop antenna 143 is disposed in the outer frame region 151 of the box portion 141. In other words, the loop antenna 143 extends along the peripheral end portion 141b of the box portion 141. Further, the configuration of the loop antenna 143 is not limited thereto.

The two second connection terminals 144 are provided inside the insertion port 141 a. The two second connection terminals 144 are two terminals of the loop antenna 143. A second connection terminal 144 is electrically connected to one end of the loop antenna 143. The other second connection terminal 144 is electrically connected to the other end of the loop antenna 143.

By inserting the micro SD card 131 into the insertion port 141a, the two first connection terminals 135 of the micro SD card 131 are electrically connected to the corresponding second connection terminals 144, respectively. Thus, the communication controller 24 is electrically connected to the loop antenna 143 through the first and second connection terminals 135 and 144.

The communication controller 24 of the third embodiment communicates with the wireless communication host device 13 via the loop antenna 143 instead of via the first antenna pattern 46 of the first embodiment. That is, in the third embodiment, the wireless antenna 23 of fig. 2 has the loop antenna 143.

The first antenna pattern 46 of the adapter 132 transmits data received from the wireless communication host device 13 to the communication controller 24 of the micro SD card 131. Further, the first antenna pattern 46 of the adapter 132 transmits data received from the communication controller 24 of the micro SD card 131 to the wireless communication host device 13.

Fig. 13 shows the micro SD card 131 inserted into the insertion port 141a by a two-dot chain line. When the first surface 41a of the first substrate 41 is viewed in plan as shown in fig. 13, a part of the inner side 143a of the loop antenna 143 is located outside the micro SD card 131. The inner side 143a of the loop antenna 143 is a region surrounded by the loop antenna 143. In addition, when the first surface 41a is viewed in a plan view, a part of the loop antenna 143 is located outside the first substrate 41.

In the SD card 11 of the third embodiment, a micro SD card 131 having a first substrate 41 is mounted on an adapter 132 having a loop antenna 143. Thus, even if the micro SD card 131 is small, the micro SD card 131 can communicate with the wireless communication host device 13 via the loop antenna 143 of the adapter 132.

The loop antenna 143 is formed of a wound copper wire. This can suppress an increase in the manufacturing cost of the SD card 11, compared to a case where the loop antenna 143 is formed by a pattern on a substrate, for example.

(fourth embodiment)

A fourth embodiment will be described below with reference to fig. 14 to 16. Fig. 14 is a plan view showing the first substrate 41 according to the fourth embodiment. As shown in fig. 14, in the fourth embodiment, a first antenna pattern 46 is mounted on a first substrate 41. In the fourth embodiment, the wireless antenna 23 of fig. 2 has a first antenna pattern 46.

Fig. 15 is a plan view showing a part of a first substrate 41 according to the fourth embodiment. As shown in fig. 14 and 15, the first substrate 41 of the fourth embodiment is provided with a plurality of connection pads 81, a plurality of first leads 82, a first solder resist 83, a second lead 115, and a third lead 116, as in the second embodiment. In the first solder resist 83, a plurality of first openings 84 and second openings 119 are provided.

The second lead 115 extends from the first antenna pattern 46 instead of from the second antenna pattern 101 of the second embodiment. The third lead 116 also extends from the first antenna pattern 46.

Fig. 16 is a plan view showing a part of the first substrate 41 in one step of the manufacturing process of the fourth embodiment. As shown in fig. 16, before the plurality of connection pads 81 are formed on the first substrate 41, the first plated leads L1 and the second plated leads L2 are provided on the first formation surface 91a of the base substrate 91.

The first plated leads L1 include a plurality of first leads 82 and second leads 115. The first plating lead L1 extends from the first antenna pattern 46, has a plurality of bifurcated portions, and is connected with the plurality of connection pads 81. In other words, the connection pad 81 is formed by electrolytic plating at the end of the first plating lead L1.

The second plated leads L2 include a third lead 116. The second plated lead L2 extends from the first antenna pattern 46 to the end face 41c of the first substrate 41. The second plating lead L2 is electrically connected to the plurality of connection pads 81 through the first antenna pattern 46 and the first plating lead L1.

When the connection pad 81 is formed by electrolytic plating, the second plating lead L2 is connected to a power supply. After the plurality of connection pads 81 are formed, a part of the first plating lead L1 and a part of the second plating lead L2 are removed by, for example, etch-back. The first plated lead L1 is etched back through the first opening 84 to be divided into a plurality of first leads 82 and second leads 115. The second plated lead L2 is etched back through the second opening 119 to form the third lead 116. Thereby, the plurality of connection pads 81 are electrically separated from the first antenna pattern 46.

In the SD card 11 of the fourth embodiment, the first lead 82 extends from the connection pad 81 to which an electronic component such as the flash memory 25 is connected. The 1 st lead 82 is electrically separated from the other electrical conductors. On the other hand, the second lead 115 extends from the first antenna pattern 46. The second lead 115 is electrically separated from the other conductor. The first and second leads 82 and 115 are connected, for example, in the manufacturing process of the SD card 11, and the first plated lead L1 is formed. In this case, by applying a voltage to the first and second leads 82 and 115 through the first antenna pattern 46, the connection pad 81 can be formed by electrolytic plating on the end portion of the first lead 82. After the connection pad 81 is formed, the first lead 82 and the second lead 115 are divided. In this way, the connection pad 81 can be formed by electrolytic plating of the first and second leads 82 and 115 on the first substrate 41 on which the first antenna pattern 46 is formed. Therefore, the first antenna pattern 46, which is not a chip antenna but a loop antenna, can be provided on the first substrate 41, and an increase in the manufacturing cost of the SD card 11 can be suppressed.

Next, a modification of the fourth embodiment will be described with reference to fig. 17 to 19. Fig. 17 is a plan view showing a first substrate 41 according to a modification of the fourth embodiment. As shown in fig. 17, in the modification of the fourth embodiment, a plurality of connection pads 81, a plurality of first leads 82, a first solder resist 83, a plurality of second leads 115, a plurality of third leads 116, and a plurality of fourth leads 161 are provided on a first substrate 41. The first solder resist 83 is provided with a plurality of first openings 84, a plurality of second openings 119, and a plurality of third openings 162.

Fig. 17 shows the plurality of first leads 82, the plurality of second leads 115, the plurality of third leads 116, and the plurality of fourth leads 161 by solid lines, and the plurality of first openings 84, the plurality of second openings 119, and the plurality of third openings 162 by two-dot chain lines for explanation.

Fig. 18 is a plan view showing a part of a first substrate 41 according to a modification of the fourth embodiment. In a modification of the fourth embodiment, the first antenna pattern 46 is wound a plurality of times. Therefore, as shown in fig. 18, in the region adjacent to the end surface 41c of the first substrate 41, the extended portion 46d of the first antenna pattern 46 and the other extended portion 46d extend substantially in parallel with a gap therebetween. The extended portion 46d of the first antenna pattern 46 is a portion of the first antenna pattern 46 extending along the adjacent end face 41 c.

The fourth lead 161 is provided on the first formation surface 91 a. Therefore, the first solder resist 83 covers the fourth lead 161. The plurality of fourth leads 161 extend from the extension portion 46d of the first antenna pattern 46 to the adjacent other extension portions 46 d. For example, a fourth lead 161 extends from one extension 46d to the other extension 46d adjacent to the extension 46d and farther from flash memory 25 than the extension 46 d. That is, the fourth lead 161 is located between the adjacent two extension portions 46d, 46d of the first antenna pattern 46.

The fourth lead lines 161 each have a fourth end portion 161 a. The fourth end 161a is an end of the fourth lead 161 extending from the first antenna pattern 46. In other words, the fourth end 161a is located on the opposite side of the first antenna pattern 46.

The fourth end 161a is separated from the other conductor including the other extension 46d of the first antenna pattern 46. Therefore, the fourth lead 161 is electrically separated from other electrical conductor different from the extension portion 46d of the first antenna pattern 46. In other words, the fourth lead 161 does not connect the extension portion 46d of the first antenna pattern 46 to the other extension portions 46d on the way of the first antenna pattern 46 wound a plurality of times.

The third opening 162 is a hole provided in the first solder resist 83. The third opening 162 is located between the adjacent two extension portions 46d, 46d of the first antenna pattern 46 in the region adjacent to the end surface 41c of the first substrate 41. The third opening 162 exits from the adjacent two extensions 46d, 46d of the first antenna pattern 46.

When first surface 41a of first substrate 41 is viewed in plan, fourth end portion 161a of fourth lead 161 substantially overlaps the edge of first solder resist 83 where third opening 162 is formed. The fourth end 161a may be disposed at another position.

The fourth end portions 161a of the plurality of fourth leads 161 extending from one extension portion 46d of the first antenna pattern 46 substantially overlap with the edge of the first solder resist 83 forming one third opening 162. The fourth end portions 161a of the plurality of fourth leads 161 extending from the other extending portions 46d of the first antenna pattern 46 substantially overlap the edge of the first solder resist 83 forming the third opening 162.

The fourth end 161a of the fourth lead 161 extending from one extension portion 46d of the first antenna pattern 46 is opposite to the fourth end 161a of the fourth lead 161 extending from the other extension portion 46d of the first antenna pattern 46. The fourth lead 161 extending from one extension portion 46d of the first antenna pattern 46 is positioned on an extension line of the fourth lead 161 extending from the other extension portion 46d of the first antenna pattern 46.

The corresponding first lead 82, second lead 115, third lead 116 and fourth leads 161 are located on the extension line of each other. The arrangement of the first lead 82, the second lead 115, the third lead 116, and the fourth lead 161 is not limited to this.

Fig. 19 is a plan view showing a part of the first substrate 41 in one step of the manufacturing process of the modification of the fourth embodiment. As shown in fig. 19, a plurality of plated leads L are provided on the first formation surface 91a of the base substrate 91 before the step of forming the plurality of connection pads 81 on the first substrate 41. The plating lead L is provided, for example, to form a plurality of connection pads 81 and other plurality of pads by electrolytic plating.

The plurality of plating leads L includes a first lead 82, a second lead 115, a third lead 116, and a plurality of fourth leads 161, respectively. The plated leads L extend from the connection pads 81 to the end face 41c of the first substrate 41. In other words, the connection pad 81 is formed by electrolytic plating on the end of the plated lead L.

The plurality of plated leads L linearly extend from one of the connection pads 81 to the end surface 41c of the first substrate 41. The plurality of plated leads L may be bent or joined (branched).

The plurality of plated leads L intersect the plurality of extensions 46d of the first antenna pattern 46. In other words, the plurality of plated leads L electrically connect the extension portion 46d of the first antenna pattern 46 and the other extension portions 46 d. Further, for example, in the case where the flash memory 25 and/or the memory controller 26 are wired using a wire bonding technique, a part of the first antenna pattern 46 may be formed using a bonding wire and separated from the plating wire L.

Before the plurality of first substrates 41 are cut out from one collective substrate, the plurality of plated leads L are connected to leads of the collective substrate including the plurality of first substrates 41. That is, the plurality of plated leads L connect the leads of the aggregate substrate to the inner side 46a of the first antenna pattern 46. When the connection pad 81 is formed by electrolytic plating, the plated lead L is connected to a power supply.

When the plurality of connection pads 81 are formed, a part of the plated leads L is removed by, for example, etch-back. The plated lead L is etched back through the first opening 84, the second opening 119, and the plurality of third openings 162, and is divided into a first lead 82, a second lead 115, a third lead 116, and a plurality of fourth leads 161.

The plurality of connection pads 81 are electrically separated from the first antenna pattern 46 by etching back the plated leads L. Further, the extension portion 46d of the first antenna pattern 46 is electrically separated from the other extension portions 46 d.

In the SD card 11 of the modification of the fourth embodiment, the first lead 82 extends from the connection pad 81, and the second lead 115 extends from the first antenna pattern 46. The third lead 116 extends from the first antenna pattern 46 toward the end surface 41c of the first substrate 41, and the fourth lead 161 extends from the extending portion 46d of the first antenna pattern 46 toward the other extending portion 46 d. The first to fourth leads 82, 115, 116, 161 are electrically separated from the other conductors, respectively. The first to fourth leads 82, 115, 116, 161 are connected, for example, in the manufacturing process of the SD card 11 to form plated leads L. In this case, by applying a voltage to the plated lead L intersecting the first antenna pattern 46, the connection pad 81 can be formed by electrolytic plating at the end of the first lead 82. After the connection pad 81 is formed, the first to fourth leads 82, 115, 116, 161 are divided. In this way, the connection pads 81 can be formed by electrolytic plating of the first to fourth leads 82, 115, 116, 161 on the first substrate 41 on which the first antenna pattern 46 is formed.

In the step of forming the connection pad 81, a voltage is applied to each of the plurality of plated leads L extending linearly. Therefore, the distance from the power source to the end of the first lead 82 of each plated lead L is easily made uniform. Further, the distance from the end surface 41c of the first substrate 41 to the end portion of the first lead 82 of each plated lead L is easily made uniform. Therefore, the power supply is stable, and the plurality of connection pads 81 are easily and uniformly formed by electrolytic plating.

(fifth embodiment)

The fifth embodiment is explained below with reference to fig. 20. Fig. 20 is a bottom view of the SD card 11 according to the fifth embodiment, with the bottom cover 32 omitted. In fig. 20, the first substrate 41 is indicated by a two-dot chain line.

As shown in fig. 20, in the fifth embodiment, the first antenna pattern 46 is mounted on the top cover 33. In the fifth embodiment, the wireless antenna 23 of fig. 2 has a first antenna pattern 46.

In the fifth embodiment, the first antenna pattern 46 is buried inside the top cover 33. In other words, the first antenna pattern 46 is located between the top surface 61 and the second inner face 62 of the top cover 33. The first antenna pattern 46 may be provided on the second inner surface 62 of the top cover 33 or the bottom cover 32, for example. The first antenna pattern 46 may be a conductive pattern formed by various methods such as printing, or may be a conductor such as a copper wire.

First terminals 171 are provided at both ends of the first antenna pattern 46. The first terminal 171 protrudes from the third recess 65 of the second inner surface 62 of the top cover 33, for example. The first terminal 171 overlaps the first substrate 41 when the second surface 41b of the first substrate 41 is viewed in a plan view as shown in fig. 20.

Two second terminals 172 are provided on the first surface 41a of the first substrate 41. The second terminal 172 is opposite to the first terminal 171. For example, the second terminal 172 is electrically connected to the first terminal 171 via a conductive spring. The second terminal 172 may be in direct contact with the first terminal 171 or may be connected by solder. Thereby, the circuit C of the first substrate 41 and the first antenna pattern 46 are electrically connected.

In the SD card 11 of the fifth embodiment, the first antenna pattern 46 is provided on the top cover 33 of the housing 31. This can suppress a decrease in the degree of freedom of the wiring on the first substrate 41. Further, by providing the first antenna pattern 46 in the case 31 of the SD card 11, the increase in the number of components of the SD card 11 can be suppressed, and the increase in the manufacturing cost of the SD card 11 can be suppressed.

The first terminals 171 of the first antenna pattern 46 and the second terminals 172 of the first substrate 41 are electrically connected by, for example, springs. Thus, even if the first antenna pattern 46 and the first substrate 41 move relatively, damage to the connection portion between the first antenna pattern 46 and the first substrate 41 can be suppressed.

(sixth embodiment)

The sixth embodiment will be described with reference to fig. 21. Fig. 21 is a plan view showing an SD card 11 according to the sixth embodiment. As shown in fig. 21, a label 181 is attached to the top surface 61 of the top cover 33.

The label 181 is a sheet attached to the housing 31. The label 181 describes, for example, the specification, memory capacity, insertion direction, and description of the SD card 11. Note that the label 181 is not limited to this. The label 181 is attached to, for example, a recess 183 provided in the top surface 61. Also, a portion of the label 181 may be located outside the recess 183.

In the sixth embodiment, the first antenna pattern 46 is mounted on the tab 181. In the sixth embodiment, the wireless antenna 23 of fig. 2 has a first antenna pattern 46.

In the sixth embodiment, the first antenna pattern 46 is embedded inside the label 181. The first antenna pattern 46 may be provided on the adhesive surface of the label 181 attached to the top cover 33, for example. The adhesive surface is a surface of the label 181 to which an adhesive is applied. The first antenna pattern 46 may be a conductive pattern formed by various methods such as printing, or may be a conductor such as a copper wire.

At both end portions of the first antenna pattern 46, third terminals 185 are provided. The third terminal 185 is provided on the adhesive surface of the label 181, for example. The third terminal 185 overlaps the first substrate 41 when the top surface 61 of the top cover 33 is viewed in plan as shown in fig. 21.

Two through electrodes 187 are provided on the top cover 33. The penetrating electrode 187 is formed of a conductive body and penetrates the top cover 33. The through electrode 187 protrudes from the top surface 61 and protrudes from the second inner face 62. The third terminal 185 of the first antenna pattern 46 is opposite to the through electrode 187. The third terminal 185 is in contact with the through electrode 187 and is electrically connected to the through electrode 187.

The third terminal 185 is brought into contact with the through electrode 187 by attaching the label 181 to the recess 183 of the top cover 33. That is, the recess 183 is used for positioning the third terminal 185 and the penetrating electrode 187.

Two fourth terminals 189 are provided on the first surface 41a of the first substrate 41. The fourth terminal 189 is opposite to the through electrode 187. For example, the fourth terminal 189 is electrically connected to the penetrating electrode 187 via a conductive spring. The fourth terminal 189 may be in direct contact with the through electrode 187, or may be connected by soldering.

The through electrode 187 is interposed between the third terminal 185 of the first antenna pattern 46 and the fourth terminal 189 of the first substrate 41. Thereby, the third terminal 185 is electrically connected to the fourth terminal 189 through the penetrating electrode 187, and the circuit C of the first substrate 41 and the first antenna pattern 46 are electrically connected.

In the SD card 11 of the sixth embodiment, the first antenna pattern 46 is provided on the label 181. This can suppress a decrease in the degree of freedom of the wiring of the first substrate 41. Further, by providing the first antenna pattern 46 on the label 181 of the SD card 11, the increase in the number of components of the SD card 11 can be suppressed, and the increase in the manufacturing cost of the SD card 11 can be suppressed.

The label 181 is adhered to the top surface 61 of the top cover 33 protruding through the electrode 187. This can suppress relative movement between the tag 181 on which the first antenna pattern 46 is mounted and the through electrode 187, and can suppress damage to the connection portion between the first antenna pattern 46 and the first substrate 41.

The label 181 may be attached to other portions of the housing 31, not limited to the top surface 61 of the top cover 33. For example, the label 181 may also be attached to the second interior face 62 of the top cover 33. In this case, the third terminal 185 and the fourth terminal 189 can be electrically connected without passing through the penetrating electrode 187.

The first antenna pattern 46 may be mounted on a sheet having no adhesive surface, not limited to the label 181. In this case, for example, the sheet is sandwiched between the label 181 not having the first antenna pattern 46 and the top cover 33. This makes it possible to attach the sheet having no adhesive surface to the housing 31.

According to at least one embodiment described above, when the first surface of the first substrate is viewed in plan, at least a part of the first antenna is located outside the first substrate, and at least a remaining part is located on the first substrate. This can suppress an increase in the manufacturing cost of the semiconductor memory device.

While several embodiments of the invention have been described, these embodiments are merely illustrative and are not intended to limit the scope of the invention. These new embodiments may be implemented in other various ways, and various omissions, substitutions, and changes may be made without departing from the scope of the invention. These embodiments and/or modifications thereof are included in the scope and/or gist of the invention, and are also included in the invention described in the claims and the equivalent scope thereof.

Claims (18)

1. A semiconductor memory device, wherein,

the disclosed device is provided with:

a first substrate having a first surface and a second surface located on an opposite side of the first surface;

a nonvolatile memory mounted on the first surface;

a memory controller mounted on the first substrate, the memory controller configured to: controlling the non-volatile memory;

a first interface terminal mounted on the first substrate and electrically connectable to a first external device;

a first antenna connected to the first substrate, at least a part of which is located outside the first substrate and at least a remaining part of which is located on the first substrate when the first surface is viewed in plan;

a second substrate on which the first antenna is mounted; and

a communication controller configured to: communicate with a second external device via the first antenna,

the second substrate is a flexible printed circuit board.

2. The semiconductor memory device according to claim 1,

the first antenna generates a voltage based on a radio wave from the second external device,

the communication controller is operable with the generated voltage.

3. The semiconductor storage device according to claim 1 or 2,

further provided with:

a circuit mounted on the first substrate, the circuit including the nonvolatile memory, the memory controller, the first interface terminal, and a plurality of first pads; and

a second pad mounted on the first substrate and electrically independent from the circuit,

the first antenna has a plurality of third pads soldered to the plurality of first pads,

the second substrate has a fourth pad electrically independent from the circuit and soldered to the second pad.

4. The semiconductor memory device according to claim 3,

the second substrate has a first portion on which the first antenna is mounted, a second portion surrounded by the first portion, and a third portion surrounding the first portion,

at least one of the plurality of third pads and the fourth pads is disposed on the second portion, and at least another one of the plurality of third pads and the fourth pads is disposed on the third portion.

5. The semiconductor storage device according to claim 1 or 2,

the second substrate is thinner than the first substrate.

6. The semiconductor storage device according to claim 1 or 2,

when the first surface is viewed in plan, at least a part of the inside of the first antenna is located outside the first substrate.

7. The semiconductor storage device according to claim 1 or 2,

the antenna device further includes a second antenna mounted on the first substrate, connected to the first antenna, and forming one antenna together with the first antenna.

8. The semiconductor memory device according to claim 7,

the first interface terminal is mounted on the second surface,

the second antenna has a first wiring mounted on the first surface and a second wiring mounted on the second surface and connected to the first wiring,

at least a part of the first wiring overlaps the first interface terminal when the first surface is viewed in a plan view.

9. The semiconductor memory device according to claim 7,

further comprises a ground line provided on the first substrate,

the first substrate has at least one first region and at least one second region,

the at least one first region is surrounded by the one antenna formed by the first antenna and the second antenna, overlaps at least one of the nonvolatile memory and the memory controller when the first surface is viewed in plan, and is provided with the ground line,

the at least one second region is surrounded by the one antenna formed by the first antenna and the second antenna, and is separated from the first region when the first surface is viewed in plan.

10. The semiconductor memory device according to claim 7,

further provided with:

a connection pad mounted on the first substrate and electrically connected to any one of the nonvolatile memory, the memory controller, and the communication controller;

a first conductive pattern mounted on the first substrate, connected to the connection pad, and electrically connecting the connection pad to another conductor different from the connection pad;

a second conductive pattern mounted on the first substrate, connected to the second antenna, and electrically connecting the second antenna to another conductor different from the second antenna;

a first lead mounted on the first substrate, extending from the connection pad, and electrically separated from another conductor different from the connection pad; and

a second lead extending from the second antenna and electrically separated from other electrical conductors different from the second antenna.

11. The semiconductor memory device according to claim 10,

the first lead has a first end portion on an opposite side of the connection pad,

the second lead has a second end portion on an opposite side of the second antenna,

the first substrate has: a formation surface on which the first lead and the second lead are provided; and a solder resist covering the formation surface, the first lead and the second lead,

the solder resist is provided with an opening that overlaps, when the first surface is viewed in plan, a region between the first end of the first lead and the second end of the second lead.

12. The semiconductor memory device according to claim 11,

the first substrate further has a covering member that covers the nonvolatile memory, the memory controller, the solder resist, and the opening.

13. The semiconductor memory device according to claim 10,

further comprises a third lead mounted on the first substrate,

the first substrate has an end face connecting an end edge of the first surface and an end edge of the second surface,

the third lead extends from the second antenna between the second antenna and the end surface of the first substrate, and is electrically separated from another conductor.

14. The semiconductor memory device according to claim 10,

a plurality of the connection pads and a plurality of the first leads are also provided,

the number of the first leads is larger than that of the second leads.

15. The semiconductor storage device according to claim 1 or 2,

further comprises a case which houses the first substrate and the first antenna and has a first cover and a second cover,

the first cover is provided with a first recess for accommodating the first substrate and a second recess for accommodating the first antenna,

the second cover is mounted to the first cover and covers the first substrate and the first antenna.

16. The semiconductor memory device according to claim 1,

further provided with:

an adapter having the first antenna and a second interface terminal; and

a semiconductor device having the first substrate and detachably mounted to the adapter,

the first interface terminal is electrically connectable to the first external device via the second interface terminal.

17. The semiconductor memory device according to claim 16,

the first antenna is formed of a coiled conductor.

18. An adapter, wherein,

the disclosed device is provided with:

a box part provided with an insertion opening;

an antenna housed in the case portion;

a substrate on which the antenna is mounted; and

a plurality of second connection terminals provided inside the insertion port, connected to the antenna, and configured to: a semiconductor device inserted into the insertion opening and electrically connected to a plurality of first connection terminals provided in the semiconductor device, the semiconductor device being configured to: communicate with an external device via the antenna,

wherein at least a part of the antenna is located outside the semiconductor device in a plan view in a state where the plurality of first connection terminals of the semiconductor device are electrically connected to the plurality of second connection terminals of the adapter,

the substrate is a flexible printed circuit board.

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