CN106803519A - 一种vdmos器件截止环结构 - Google Patents

一种vdmos器件截止环结构 Download PDF

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CN106803519A
CN106803519A CN201710157319.9A CN201710157319A CN106803519A CN 106803519 A CN106803519 A CN 106803519A CN 201710157319 A CN201710157319 A CN 201710157319A CN 106803519 A CN106803519 A CN 106803519A
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陈晓伦
徐永斌
沈晓东
许柏松
叶新民
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XINSUN CO Ltd
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    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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Abstract

本发明涉及一种VDMOS器件截止环结构，它包括作为衬底的高阻掺杂区；在高阻掺杂区上形成有Field氧化层；在Field氧化层上刻蚀形成AA窗口；在AA窗口区域内的高阻掺杂区上形成Gate氧化层；在Gate氧化层上覆盖有GatePoly层，GatePoly层的左侧延伸到AA窗口左侧Field氧化层上，GatePoly层的右侧只覆盖AA窗口一部分；AA窗口未覆盖Poly的区域形成与高阻掺杂区相反掺杂类型的Body掺杂区；在Body掺杂区上形成与其相反掺杂类型的Source掺杂区；在Field氧化层及Poly表面上覆盖有BPSG+USG；在GatePoly层及Source掺杂区上刻蚀氧化层形成Cont孔；在Cont孔上覆盖Metal层，并且Metal层左侧延伸到Field氧化层上。本发明的截止环结构不需要任何额外的工艺流程，避免了常规截止环结构需要增加一次光刻工艺才能实现的弊端。

Description

一种VDMOS器件截止环结构
技术领域
本发明涉及一种新型的VDMOS器件截止环结构，应用在集成电路或分立器件制造技术领域。
背景技术
VDMOS是垂直双扩散金属-氧化物半导体场效应晶体管的简称，本发明所述的VDMOS是基于硅制造工艺。在芯片制造过程以及后期的芯片封装中，芯片表面的氧化物容易产生或者引入表面电荷（包括固定电荷及可动电荷），当其数量达到一定程度时，就有可能在硅表面感应出载流子，硅表面会发生积累、耗尽、反型三种情形之一。对于反型即会在有源区与划片槽之间形成表面导电沟道，严重影响器件的性能甚至造成芯片失效。而从实际的芯片制造经验看，硅表面的反型导致形成表面导电沟道的现象非常普遍、常见，表面导电沟道的存在不可忽视。截止环的设计就是截断有源区与划片槽之间形成的表面导电沟道，解决沟道漏电问题。传统的截止环的结构如图1所示，在有源区与划片槽之间的高阻区掺杂形成同型的高浓度低阻区，这样由于掺杂浓度较高，氧化物内的电荷数量不足以造成硅表面反型。VDMOS是同窗口掺杂P型、N型的杂质，利用结深差在表面形成MOS器件的沟道。这样，为了形成截止环结构的高浓度掺杂区，就必须增加一次光刻工艺，在掺杂Body掺杂区杂质时，需要用光刻胶对截止环的掺杂窗口进行掩蔽，这样在Source掺杂区掺杂时就形成了独立的高浓度掺杂区。如果不在掺杂Body掺杂区杂质时增加一次光刻用光刻胶对截止环掺杂窗口进行掩蔽，那在Source掺杂区外还包围着结深较深的Body掺杂区，且与Source区的杂质类型相异，该环形成了天然的反型通道，就不能起到沟道截止的作用（参见图2）。即对于VDMOS器件而言，为了形成一般的截止环结构，需要额外增加一次光刻工艺，造成芯片制造成本额外增加。
发明内容
本发明所要解决的技术问题是针对上述现有技术提供一种新型的VDMOS截止环结构设计，在不额外增加光刻次数的前提下，达到与常规截止环结构相同的截断有源区与划片槽之间表面导电沟道的目的。
本发明解决上述问题所采用的技术方案为：一种VDMOS器件截止环结构，它包括作为衬底的高阻掺杂区；在所述的高阻掺杂区上形成有Field氧化层；在所述的Field氧化层上刻蚀形成AA窗口；在所述AA窗口区域内的高阻掺杂区上形成Gate氧化层，Gate氧化层只覆盖部分AA窗口区域内的高阻掺杂区；在所述的Gate氧化层上覆盖有GatePoly层，GatePoly层的左侧延伸到AA窗口左侧Field氧化层上，GatePoly层的右侧只覆盖AA窗口一部分；所述AA窗口未覆盖GatePoly层的区域形成与高阻掺杂区相反掺杂类型的Body掺杂区；在所述Body掺杂区上形成与其相反掺杂类型的Source掺杂区；在所述的Field氧化层及GatePoly层表面上覆盖有BPSG+USG层；在所述的GatePoly层及Source掺杂区上刻蚀氧化层形成Cont孔；在所述的Cont孔上覆盖Metal层，并且Metal层左侧延伸到Field氧化层上。
与现有技术相比，本发明的优点在于：
本发明的截止环结构与标准的VDMOS晶胞工艺流程相同，不需要任何额外的工艺流程，避免了常规截止环结构需要增加一次光刻工艺才能实现的弊端，同时适用于大部分类型的MOS器件。
附图说明
图1为VDMOS增加一次光刻形成的常规截止环剖面结构图。
图2为VDMOS不增加一次光刻形成的“截止环”剖面结构图。
图3为本发明的新型截止环剖面结构图。
具体实施方式
以下结合实施例对本发明作进一步详细描述。
本发明涉及一种VDMOS器件截止环结构，它包括作为衬底的高阻掺杂区1；在所述的高阻掺杂区上形成有Field（场氧）氧化层2；在所述的Field氧化层2上刻蚀形成AA（有源）窗口3（与有源区同步形成）；在所述的AA窗口3区域内的高阻掺杂区1上形成Gate（栅氧）氧化层4,（与有源区晶胞的Gate氧化层同步形成），Gate（栅氧）氧化层4只覆盖部分AA窗口3区域内的高阻掺杂区1；在所述的Gate氧化层4上覆盖有GatePoly（栅极多晶硅）层5，GatePoly层5的左侧延伸到AA窗口3左侧Field氧化层2上，GatePoly层5的右侧只覆盖AA窗口3一部分；所述AA窗口3未覆盖GatePoly层5的区域形成与高阻掺杂区1相反掺杂类型的Body（体）掺杂区6（与有源区晶胞的Body掺杂区同步形成）；在所述Body掺杂区6上（相同掺杂窗口）形成与其相反掺杂类型的Source（源）掺杂区7（与有源区晶胞的Source掺杂区同步形成）；在所述的Field氧化层2及GatePoly层5表面上覆盖有BPSG（硼磷硅玻璃）+USG（纯二氧化硅）层8；在所述的GatePoly层5及Source掺杂区7上刻蚀氧化层形成Cont（引线）孔9；在所述的Cont孔9上覆盖Metal（金属）层10，以使得Gate Poly与Source掺杂区实现短接，并且Metal层10左侧延伸到Field氧化层2上。上述所述结构的剖面图参见图3，对应的其左侧未示意结构为VDMOS芯片有源区，右侧未示意结构为划片槽。
本发明的截止环结构实现截断表面导电沟道的原理：
众所周知，PN结存在内建电势差，并且其内建电势差大小由其N、P型杂质掺杂浓度（所述掺杂浓度均为净掺杂浓度）决定，掺杂杂质浓度差越高，内建电势越大，并且N型一侧的内建电势为正，P型一侧的内建电势为负。在本发明中，高阻掺杂区与Body掺杂区与Source掺杂区三者形成了NPN或者PNP的结构，高阻掺杂区与Source掺杂区同型，而与Body掺杂区异型，并且掺杂浓度大小依次为Source掺杂区≫Body掺杂区≫高阻掺杂区。显而易见的，由于掺杂浓度Source掺杂区≫高阻掺杂区，因此在Source与Body形成的内建电势大于高阻掺杂区与Body形成的内建电势，两者的电势差一般在0.2V~0.3V。本发明的Source掺杂区与GatePoly与Metal短接为等电势，这样由于Gate氧化层较薄，在Gate氧化层下方的高阻掺杂区表面就会因前述的电势差感应出与高阻掺杂区同型的载流子，增加了其表面的掺杂浓度，这样就避免了此高阻掺杂区的表面反型。另外，GatePoly与Metal短接为等电势，在两者之间的氧化层存在的电荷影响将会被屏蔽，并且外界可能存在的电荷沾污也能够被GatePoly与Metal短接结构所阻挡，因此在Gate氧化层区域的高阻掺杂区表面难以再因氧化层内的积累电荷感应出载流子。在上述的两种机理作用下，在Gate氧化层区域的高阻掺杂区表面，难以再出现反型的情形，表面的反型导电沟道被截断。
除上述实施例外，本发明还包括有其他实施方式，凡采用等同变换或者等效替换方式形成的技术方案，均应落入本发明权利要求的保护范围之内。

Claims (1)

1.一种VDMOS器件截止环结构，它包括作为衬底的高阻掺杂区（1）；在所述的高阻掺杂区（1）上形成有Field氧化层（2）；在所述的Field氧化层（2）上刻蚀形成AA窗口（3）；在所述AA窗口（3）区域内的高阻掺杂区（1）上形成Gate氧化层（4），Gate氧化层（4）只覆盖部分AA窗口（3）区域内的高阻掺杂区（1）；在所述的Gate氧化层（4）上覆盖有GatePoly层（5），GatePoly层（5）的左侧延伸到AA窗口（3）左侧Field氧化层（2）上，GatePoly层（5）的右侧只覆盖AA窗口（3）一部分；所述AA窗口（3）未覆盖GatePoly层（5）的区域形成与高阻掺杂区（1）相反掺杂类型的Body掺杂区（6）；在所述Body掺杂区（6）上形成与其相反掺杂类型的Source掺杂区（7）；在所述的Field氧化层（2）及GatePoly层（5）表面上覆盖有BPSG+USG层（8）；在所述的GatePoly层（5）及Source掺杂区（7）上刻蚀氧化层形成Cont孔（9）；在所述的Cont孔（9）上覆盖Metal层（10），并且Metal层（10）左侧延伸到Field氧化层上。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4633292A (en) * 1982-05-28 1986-12-30 Siemens Aktiengesellschaft Semiconductor component with planar structure
US6104060A (en) * 1996-02-20 2000-08-15 Megamos Corporation Cost savings for manufacturing planar MOSFET devices achieved by implementing an improved device structure and fabrication process eliminating passivation layer and/or field plate
CN206610814U (zh) * 2017-03-16 2017-11-03 江阴新顺微电子有限公司 一种vdmos器件截止环结构

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4633292A (en) * 1982-05-28 1986-12-30 Siemens Aktiengesellschaft Semiconductor component with planar structure
US6104060A (en) * 1996-02-20 2000-08-15 Megamos Corporation Cost savings for manufacturing planar MOSFET devices achieved by implementing an improved device structure and fabrication process eliminating passivation layer and/or field plate
CN206610814U (zh) * 2017-03-16 2017-11-03 江阴新顺微电子有限公司 一种vdmos器件截止环结构

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