CN106796917B - The manufacturing method of semiconductor device and semiconductor device - Google Patents

The manufacturing method of semiconductor device and semiconductor device Download PDF

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Publication number
CN106796917B
CN106796917B CN201680002320.8A CN201680002320A CN106796917B CN 106796917 B CN106796917 B CN 106796917B CN 201680002320 A CN201680002320 A CN 201680002320A CN 106796917 B CN106796917 B CN 106796917B
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semiconductor region
semiconductor
region
type
diffusion region
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CN106796917A (en
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丰田善昭
片仓英明
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract

The p for running through substrate face side in the depth direction is provided in circuit portion‑Type base area (21) and the p for surrounding MOSFET (20) surrounding+Type diffusion region (24).With the p in the protection element portion in circuit portion same substrate, in substrate face side‑The inside of type diffusion region (31) is selectively provided with p++Type contact zone (32), n+Type diffusion region (33) and p+Type diffusion region (34).p+Type diffusion region (34) is in p‑The periphery of type diffusion region (31) and in the depth direction run through p‑Type diffusion region (31).n+Type source region (22), p+Type diffusion region (24), p++Type contact zone (32) and n+Type diffusion region (33) is connected to GND terminal.Substrate back is connected to VCC terminal.The rebound of the parasitic bipolar element (T1) in protection element portion starts the rebound of voltage (snap-back starting voltage) than the parasitic bipolar element (T2) of circuit portion, and to start voltage low.Hereby it is possible to realize the control of micromation, the raising of surge resistance and cost.

Description

The manufacturing method of semiconductor device and semiconductor device
Technical field
The present invention relates to the manufacturing methods of a kind of semiconductor device and semiconductor device.
Background technique
In the past, for the high reliability of power semiconductor, miniaturization and cost effective purpose, it is known that will indulge To the control of type power semiconductor and the longitudinal type power semiconductor, the lateral type semiconductor element of protection circuit Part be arranged on same semiconductor substrate (semiconductor chip) power semiconductor arrangement (referring for example to following patent documents 1, 2).About the structure of existing semiconductor device, by longitudinal type n-channel power MOSFET (the Metal Oxide of output stage Semiconductor Field Effect Transistor: Metal Oxide Semiconductor Field Effect Transistor) and control circuit The power semiconductor dress of same semiconductor substrate is arranged in lateral type CMOS (Complementary MOS: complementary type MOS) Example is set to be illustrated.Figure 13 is the sectional view for indicating the structure of existing semiconductor device.
Existing semiconductor device shown in Figure 13 is the longitudinal type n-channel power MOSFET that uses output stage as groove The vehicle-mounted high-pressure side type Power IC (Integrated Circuit: integrated circuit) of the longitudinal type MOSFET 110 of grid structure An example.As shown in figure 13, existing semiconductor device has output stage on n-type semiconductor substrate (semiconductor substrate) Portion, circuit portion and the protection element portion that them are protected from surge, n-type semiconductor substrate (semiconductor substrate) is in n+Type support N is laminated on the front of substrate 101-Made of type semiconductor layer 102.The longitudinal type of output stage is provided in output stage portion MOSFET 110.The lateral type CMOS etc. of control circuit is provided in circuit portion.It is only shown in circuit portion, is controlled constituting Transverse direction in the lateral type p-channel MOSFET and lateral type n-channel MOSFET of the complementary connection of the lateral type CMOS of circuit processed Type n-channel MOSFET 120.The longitudinal type diode 130 as protection element portion is provided in protection element portion.
In output stage portion, n+Type supporting substrate 101 and n-Type semiconductor layer 102 is sent out respectively as drain electrode layer and drift layer The effect of waving.It is connected to substrate back (n+The back side of type supporting substrate 101) drain electrode 109 (drain terminal) be connected with it is vehicle-mounted The power supply voltage terminal (hereinafter referred to as VCC terminal) of battery.In substrate face side (n-Type semiconductor layer 102 relative to n+Type The opposite side of 101 side of supporting substrate) it is provided with ground terminal (hereinafter referred to as GND terminal) and output terminal (hereinafter referred to as OUT Terminal).The n of longitudinal type MOSFET 110 is electrically connected in OUT terminal+Type source region 107 and p++Type diffusion region 108.Symbol 103 ~106 respectively indicate groove, gate insulating film, grid and the p-type base area of longitudinal type MOSFET 110.
The lateral type n-channel MOSFET 120 for constituting the lateral type CMOS of circuit portion is configured in p-The inside of type base area 121, The p-Type base area 121 is selectively disposed on the superficial layer of substrate face.In addition, in p-The inside of type base area 121, in p- N near the periphery of type base area 121, with lateral type n-channel MOSFET 120+Type source region 122 and n+Type drain region 123 is discretely set It is equipped with p+Type diffusion region 124.p+The depth and p of type diffusion region 124-The depth of type base area 121 is identical, or compares p-Type base area 121 Depth it is deep.P in figure 13 illustrates+The depth ratio p of type diffusion region 124-The situation of the depth depth of type base area 121.The p+Type diffusion Area 124, as preventing the p generated by the current potential for the wiring layer being layered in substrate face-The reversion of the reversion of type base area 121 Prevent layer from playing a role.
In p+The inside of type diffusion region 124, which is selectively provided with, to be become and the contact portion (being electrically connected with contact portion) of wiring layer p++Type contact zone 125.In figure 13 illustrates lateral type n-channel MOSFET 120 in control circuit CMOS inverter or Various inverter circuit (the inverter of ED (Enhancement/DepIetion) phase inverter, resistance load inverter etc. Example when circuit), lateral type n-channel MOSFET's 120 is connected to n+The source terminal and GND of type source region 122 Terminal electrical connection.P as back grid-Type base area 121 is also via p+Type diffusion region 124 and p++Type contact zone 125 and GND terminal Electrical connection.The grid of the expression of symbol 126 lateral type n-channel MOSFET 120.
N is connected in lateral type n-channel MOSFET 120+The drain terminal in type drain region 123 is connected with lateral type p-channel The circuit elements such as MOSFET or depletion type MOS FET, resistive element 111 constitute the various inverter circuits in control circuit.Electricity Circuit component 111 is connected to the n for being selectively disposed in the superficial layer of substrate face via power circuit 112+Type diffusion region 113. Power circuit 112 is made of high voltage bearing circuit element (not shown), receives the supply voltage current potential (VCC of n-type semiconductor substrate The current potential of terminal) and low potential is exported to circuit element 111, and to by lateral type n-channel MOSFET 120 and circuit element 111 The various inverter circuit supply line voltages of composition.This vehicle-mounted Power IC needs higher surge resistance.
ESD (Electro-Static Discharge: static discharge) etc. is applied between VCC terminal and GND terminal When high surge voltage, surge is successively from VCC terminal to n-Type semiconductor layer 102, power circuit 112, circuit element 111, transverse direction The intrusion of the path of type n-channel MOSFET 120 and GND terminal, and apply high voltage.In each constituting portion that these surges are invaded In, the size of circuit element 111 or lateral type n-channel MOSFET 120 are small, and the surge resistance of element monomer is low.For this purpose, It is parallel with surge current between VCC terminal and GND terminal and absorbs the longitudinal type diode 130 for using (surge protection use).Longitudinal type Diode 130 is selectively provided with p by the superficial layer in substrate face+The pn-junction of type diffusion region 131 is constituted.In order to make with Do not increase process when forming longitudinal type diode 130 in the identical n-type semiconductor substrate of lateral type n-channel MOSFET 120, together When formed longitudinal type diode 130 p+The p of type diffusion region 131 and lateral type n-channel MOSFET 120+Type diffusion region 124.
Snowslide occurs for longitudinal type diode 130, when being applied with surge voltage between VCC terminal and GND terminal to hit (Avalanche breakdown) is worn, electric current I101 is made to pass through p from VCC terminal side+Type diffusion region 131 and p++Type contact zone 132 Along the longitudinal flow towards GND terminal and absorb surge current.On the other hand, (lateral type n is provided with being set to circuit portion The region of channel mosfet 120) p+Type diffusion region 124 and n-It is also same as longitudinal type diode 130 between type semiconductor 102 Ground is formed with pn-junction.In the p+Type diffusion region 124 and n-Pn-junction between type semiconductor layer 102 also with longitudinal type diode 130 The applied voltage of same degree punctures.This be built-in in circuit portion it is multiple smaller than the pn-junction area of longitudinal type diode 130 Longitudinal type diode (hereinafter referred to as circuit portion diode) 127 is equal, and the circuit portion of larger area can will be accounted in Power IC A part as surge protection longitudinal type diode 130 use.Therefore, the longitudinal type two of surge protection can be expanded The effective pn-junction area of pole pipe 130.
(the maximum electricity of electric current breakdown does not occur for breakdown current (breakdown current) amount of longitudinal type diode 130 Flow valuve) it is becoming proportionately larger with pn-junction area.Therefore, circuit portion diode 127 is constituted by using a part of circuit portion, with The case where being separately formed longitudinal type diode 130 is compared, and can be improved the resistance to sparking of longitudinal type diode 130 itself, with this Meanwhile, it is capable to improve the surge resistance of Power IC.In addition, the pressure resistance of longitudinal type diode 130 increases with the rising of temperature. For this purpose, even if the lesser circuit portion diode 127 of pn-junction area that current convergence is constituted to a part using circuit portion, circuit The pressure resistance of portion's diode 127 increases with fever, and aggregation of the electric current to circuit portion diode 127 can be mitigated.Therefore, i.e., Make to be dispersed in circuit portion diode 127 in circuit portion, it is also difficult to the partial breakdown of circuit portion occur.
On the other hand, it is not limited in Power IC, oneself, which knows, protects usually using bipolar components substitution diode as surge The protection element of shield improves the technology of surge resistance.Use bipolar components as the protection element of surge protection When, the absorbability of surge current is improved by the rebound characteristic using bipolar components, thus improves the wave of protected element Gush resistance.Since the rebound characteristic of bipolar components depends on device architecture, propose to improve the characteristic with various The protection element of bipolar structure (for example, referring to following patent documents 3~12).In following patent documents 3, by setting with The semiconductor layer of the same model of the lower layer connection of the base of ambipolar ESD protection device expands ambipolar ESD protection device The base width of base improves the voltage patience of ambipolar ESD protection device itself.
In following patent documents 4, by make protection element base stage and base area contact site in the current collection of the base area Between the end and emitter region of pole side, to improve the holding voltage of protection element.In following patent documents 5, by that will touch Breakdown in hair element starts the bipolar action of protection element as triggering, improves ESD resistance and noise resisting ability.Following In patent document 6, using the composition for acting the thyristor of protection element as triggering the breakdown of bipolar transistor, make The holding voltage of trigger voltage and thyristor is independently adjusted.In following patent documents 7, in the n of protection element+Type source Recess portion is formed on the bottom of the body layer of the lower section of layer, keeps the rebound voltage of protection element lower than the rebound voltage of protected element.
In following patent documents 8, led by adjust the inside that the low concentration collector layer of protection element is arranged in second The interval of electric type layer and base layer, does not change holding voltage, only adjusts trigger voltage.In following patent documents 9, it is being divided Each region on the bottom surface of impurity diffusion zone or semiconductor layer that is respectively formed, pass through formed it is more common than semiconductor device Operation voltage is high, and the pressure-resistant low land of each element than constituting semiconductor device is set with two pole of pn-junction type of breakdown reverse voltage Pipe, inhibits the increase of chip area.In following patent documents 10, by making compared with the resistance when breakdown of transistor acts Resistance when the breakdown movement of diode is small, and makes the secondary breakdown current of diode compared with the secondary breakdown current of transistor Greatly, to improve ESD resistance and surge resistance.It is disclosed in following patent documents 11,12 and parasitic bipolar element is started The method that the voltage of rebound is controlled.
Existing technical literature
Patent document
Patent document 1: Japanese Unexamined Patent Publication 2002-359294 bulletin
Patent document 2: Japanese Unexamined Patent Publication 2000-91344 bulletin
Patent document 3: Japanese Unexamined Patent Publication 2006-93361 bulletin
Patent document 4: Japanese Unexamined Patent Publication 2009-64974 bulletin
Patent document 5: Japanese Unexamined Patent Publication 2011-18685 bulletin
Patent document 6: Japanese Unexamined Patent Publication 2012-38974 bulletin
Patent document 7: Japanese Unexamined Patent Publication 2012-94797 bulletin
Patent document 8: Japanese Unexamined Patent Publication 2012-99626 bulletin
Patent document 9: Japanese Unexamined Patent Publication 3-49257 bulletin
Patent document 10: Japanese Unexamined Patent Publication 2010-287909 bulletin
Patent document 11: Japanese Unexamined Patent Publication 2010-182727 bulletin
Patent document 12: Japanese Unexamined Patent Publication 2010-157642 bulletin
Summary of the invention
Technical problem
However, inventor etc. by furtheing investigate as a result, there is following new discovery repeatedly.In Power IC circuit portion It is formed with the n of lateral type n-channel MOSFET 120+Type source region 122, is formed with by n-Type semiconductor layer 102, p-121 He of type base area n+The longitudinal type parasitic bipolar element T102 that type source region 122 forms.Due to n+Type source region 122 is electrically connected to the GND of low potential side On terminal, if the electric current flowed in circuit portion along with the rising of surge voltage increases, circuit portion diode 127 is sent out Raw breakdown, electric current (hereinafter referred to as avalanche current) I102 is in p+It flows type diffusion region 124.A part of avalanche current I102 Electric current I102a flows into n+122 side of type source region and become base current, parasitic bipolar element T102 becomes on state and occurs back It jumps.
If parasitic bipolar element T102 knock-ons, the impedance of circuit portion sharply declines and current convergence is in transverse direction The n of type n-channel MOSFET 120+Type source region 122.Pass through the micromation of Power IC, the n of lateral type n-channel MOSFET 120+Type Source region 122 is formed with lesser occupied area, therefore breakdown potential flow is small.Due to n+The current convergence of type source region 122, with The contact portion 128, n of wiring layer+When type source region 122 is destroyed, start the electric current of rebound with parasitic bipolar element T102 I102a determines the surge resistance of entire Power IC.Therefore, even if expanding longitudinal type diode 130 or circuit portion diode 127 Occupied area improve the resistances to sparking of these longitudinal type diodes, can not effectively improve the surge electricity of entire Power IC Resistance.
In order to solve the problems, needing to make will not rebound occurs for the parasitic bipolar element T102 of circuit portion Puncture in circuit portion, or the parasitic bipolar element T102 of circuit portion is made not knock-on.Even if circuit portion Rebound, which occurs, for parasitic bipolar element T102 to puncture in circuit portion, then rated current or more is flowed in circuit portion Electric current I102a when, parasitic bipolar element T102 plays a role as protection element.In this way, if circuit portion can be made Parasitic bipolar element T102 plays a role as protection element, then with configuration longitudinal type diode 130 or two pole of circuit portion The case where pipe 127, is compared, and the absorbability of surge current can greatly improve, therefore is conducive to improve the surge electricity of entire Power IC Resistance.
However, if the micromation of circuit portion is in progress, the n of lateral type n-channel MOSFET 120+Type source region 122 Occupied area can reduce, and become n+Type source region 122 and the diameter of the contact hole of the contact portion 128 of wiring layer become smaller, and connect The breakdown current amount of contact hole becomes smaller.Thus, when the parasitic bipolar element T102 of circuit portion knock-ons, after rebound, electricity Stream focuses on n+The contact portion 128 of type source region 122 and wiring layer, contact hole is more easily damaged, the breakdown potential flow of circuit portion into One step reduces.That is, realize the micromation of circuit portion simultaneously and the increase of breakdown potential flow be it is relatively difficult, in posting for circuit portion Raw bipolar components T102 will not be in the composition that circuit portion punctures rebound occurs, it is difficult to improve and be miniaturized The surge resistance of Power IC.
Therefore, in order to improve the surge resistance of the Power IC being miniaturized, the parasitic bipolar member so that circuit portion is needed The mode that part T102 does not knock-on greatly improves the longitudinal type diode 130 or circuit portion diode 127 of protection element Surge absoption ability reduces electric current and concentrates to circuit portion.Above patent document is the bipolar components improved as protection element Rebound characteristic technology, do not record in view of Power IC circuit portion formed parasitic bipolar element rebound characteristic With the structure of the relationship of protection element, that is, longitudinal type diode characteristic.In addition, being improved in above patent document without recording The method of the surge resistance of the Power IC of circuit portion with rebound characteristic, and inhibit the side of the production cost of such Power IC Method.
In order to solve above-mentioned problems of the prior art, the purpose of the present invention is to provide one kind in same semiconductor Have circuit portion on substrate and protect the protection element of the circuit portion, can be realized micromation, and can be improved surge resistance Semiconductor device and semiconductor device manufacturing method.In addition, in order to solve above-mentioned problems of the prior art, this hair Bright is designed to provide a kind of guarantor for controlling cost and have circuit portion and the protection circuit portion on same semiconductor substrate The semiconductor device of protection element and the manufacturing method of semiconductor device.
Technical solution
In order to solve the above problems, reach the purpose of the present invention, semiconductor device of the invention has following feature.? The first semiconductor of the second conductive type is selectively provided on the superficial layer of first interarea of the semiconductor substrate of one conductivity type Area.The component structure of semiconductor element is provided in first semiconductor region.The component structure of the semiconductor element has There is the second semiconductor region of the first conductive type.To run through first semiconductor region in the depth direction, led with described the first half It is dense that the mode of more than depth in body area depth and the component structure of the encirclement semiconductor element is selectively provided with impurity Spend the third semiconductor region of the second conductive type higher than the impurity concentration of first semiconductor region.With with first semiconductor The mode of area's separation is selectively provided with the of the second conductive type on the superficial layer of the first interarea of the semiconductor substrate Four semiconductor regions.The 5th semiconductor region of the first conductive type is selectively provided in the inside of the 4th semiconductor region.? Run through the 4th semiconductor region on depth direction, and is set with the depth-selectiveness more than depth of 4th semiconductor region It is equipped with the 6th semiconductor region of the impurity concentration the second conductive type higher than the impurity concentration of the 4th semiconductor region.First electrode It is electrically connected to second semiconductor region, the third semiconductor region, the 4th semiconductor region and the 5th semiconductor region. Second electrode is connected to the second interarea of the semiconductor substrate.
In addition, in order to solve the above problems, reaching the purpose of the present invention, semiconductor device of the invention has following special Sign.The first of the second conductive type is selectively provided on the superficial layer of the first interarea of the semiconductor substrate of the first conductive type Semiconductor region.The component structure of semiconductor element is provided in first semiconductor region.The element of the semiconductor element Structure has the second semiconductor region of the first conductive type.Described in a manner of surrounding the component structure of the semiconductor element Impurity concentration second conduction higher than the impurity concentration of first semiconductor region is selectively provided with inside semiconductor area The third semiconductor region of type.In the table of the first interarea of the semiconductor substrate in a manner of being separated with first semiconductor region The 4th semiconductor region of the second conductive type is selectively provided in surface layer.The inside of the 4th semiconductor region selectively It is provided with the 5th semiconductor region of the first conductive type.Impurity concentration is selectively provided in the inside of the 4th semiconductor region 6th semiconductor region of the second conductive type higher than the impurity concentration of the 4th semiconductor region.First electrode is electrically connected to described Second semiconductor region, the third semiconductor region, the 4th semiconductor region and the 5th semiconductor region.Second electrode connection To the second interarea of the semiconductor substrate.
In addition, semiconductor device of the invention is characterized in that, in the present invention as stated above, the semiconductor device is also equipped with 7th semiconductor region of the 7th semiconductor region of two conductivity types, the second conductive type is selectively located at the 4th semiconductor region Inside, and impurity concentration is higher than the impurity concentration of the 4th semiconductor region；The first electrode is led via the described 7th half Body area is electrically connected to the 4th semiconductor region；The 5th semiconductor region configuration is in the 6th semiconductor region and the described 7th Between semiconductor region.
In addition, in above-mentioned invention, also there is following feature for semiconductor device of the invention.The described 4th The inside of semiconductor region is selectively provided with impurity concentration second conduction higher than the impurity concentration of the 4th semiconductor region 7th semiconductor region of type；The first electrode is electrically connected to the 4th semiconductor region via the 7th semiconductor region； 7th semiconductor region is configured in a manner of separating with the 6th semiconductor region；5th semiconductor region is selectively The inside of 6th semiconductor region is set.
In addition, in the present invention as stated above, also there is following feature for semiconductor device of the invention.The described 6th half The inside of conductor region is selectively provided with the impurity concentration the second conductive type higher than the impurity concentration of the 6th semiconductor region The 7th semiconductor region.The first electrode is electrically connected to the 4th semiconductor region via the 7th semiconductor region.Institute State the inside that the 5th semiconductor region is selectively disposed in the 6th semiconductor region.
In addition, in the present invention as stated above, also there is following feature for semiconductor device of the invention.The described 6th half What the inside of conductor region was selectively provided with the impurity concentration the second conductive type higher than the 6th semiconductor region the 7th half leads Body area.The first electrode is electrically connected to the 4th semiconductor region via the 7th semiconductor region.Described 5th half leads Body area is configured in a manner of separating with the 6th semiconductor region.
In addition, semiconductor device of the invention is characterized in that, in above-mentioned invention, the 5th semiconductor region is to wrap The mode enclosed around the 7th semiconductor region configures.
In addition, in the present invention as stated above, also there is following feature for semiconductor device of the invention.Described 5th half leads Body area is configured in the mode surrounded around the 7th semiconductor region.6th semiconductor region is led with surrounding the described 5th half Mode around body area configures.
In addition, semiconductor device of the invention is characterized in that, in above-mentioned invention, the 6th semiconductor region is to wrap The mode enclosed around the 7th semiconductor region configures.
In addition, semiconductor device of the invention is characterized in that, in above-mentioned invention, the 6th semiconductor region is to wrap The mode enclosed around the 5th semiconductor region configures.
In addition, semiconductor device of the invention is characterized in that, in the present invention as stated above, that is, the 6th semiconductor region tool There are impurity concentration identical with the third semiconductor region and depth.
In addition, semiconductor device of the invention is characterized in that, in the present invention as stated above, the 4th semiconductor region have with The identical impurity concentration of first semiconductor region and depth.
In addition, in order to solve the above problems, reaching the purpose of the present invention, semiconductor device of the invention has following special Sign.The first of the second conductive type is selectively provided on the superficial layer of the first interarea of the semiconductor substrate of the first conductive type Semiconductor region.The component structure of semiconductor element is provided in first semiconductor region.The element of the semiconductor element Structure has the second semiconductor region of the first conductive type.To run through first semiconductor region in the depth direction, with described the The mode of more than depth in semiconductor area depth and the component structure of the encirclement semiconductor element is selectively provided with The third semiconductor region of the impurity concentration the second conductive type higher than the impurity concentration of first semiconductor region.With with described first The mode of semiconductor region separation is selectively provided with the second conduction on the superficial layer of the first interarea of the semiconductor substrate 4th semiconductor region of type.The 5th semiconductor of the first conductive type is selectively provided in the inside of the 4th semiconductor region Area.The first electrode is electrically connected to second semiconductor region, the third semiconductor region, the 4th semiconductor region and institute State the 5th semiconductor region.Second electrode is connected to the second interarea of the semiconductor substrate.
In addition, semiconductor device of the invention is characterized in that, in above-mentioned invention, also there is following feature.Institute The inside for stating the 4th semiconductor region is selectively provided with higher than the impurity concentration of the 4th semiconductor region of impurity concentration 6th semiconductor region of two conductivity types.The first electrode is electrically connected to the described 4th half and leads via the 6th semiconductor region Body area.5th semiconductor region is configured in the mode surrounded around the 6th semiconductor region.
In addition, semiconductor device of the invention is characterized in that, in the present invention as stated above, so that by the 5th semiconductor Area, the 4th semiconductor region and the semiconductor substrate composition parasitic bipolar element or by the 5th semiconductor The voltage that the parasitic bipolar element in area, the 6th semiconductor region and semiconductor substrate composition starts rebound is lower than by institute The parasitic bipolar element for stating the second semiconductor region, first semiconductor region and semiconductor substrate composition starts rebound The mode of voltage is set until the 6th semiconductor region to the 4th semiconductor region and the contact portion of the first electrode Distance.
In addition, semiconductor device of the invention is characterized in that, in the present invention as stated above, so that by the 5th semiconductor Area, the 4th semiconductor region and the semiconductor substrate composition parasitic bipolar element or by the 5th semiconductor The voltage that the parasitic bipolar element in area, the 6th semiconductor region and semiconductor substrate composition starts rebound is lower than by institute The parasitic bipolar element for stating the second semiconductor region, first semiconductor region and semiconductor substrate composition starts rebound The mode of voltage sets the distance until the 6th semiconductor region to the 7th semiconductor region.
In addition, semiconductor device of the invention is characterized in that, in the present invention as stated above, so that by the 5th semiconductor The voltage that the parasitic bipolar element in area, the 4th semiconductor region and semiconductor substrate composition starts rebound is lower than by institute The parasitic bipolar element for stating the second semiconductor region, first semiconductor region and semiconductor substrate composition starts rebound The mode of voltage sets the distance until the 6th semiconductor region to the 5th semiconductor region.
In addition, semiconductor device of the invention is characterized in that, in the present invention as stated above, so that by the 5th semiconductor The voltage that the parasitic bipolar element in area, the 4th semiconductor region and semiconductor substrate composition starts rebound is lower than by institute The parasitic bipolar element for stating the second semiconductor region, first semiconductor region and semiconductor substrate composition starts rebound The mode of voltage sets from the corner part of the 4th semiconductor region to the 4th semiconductor region with the first electrode and connects Distance until contact portion.
In addition, semiconductor device of the invention is characterized in that, in the present invention as stated above, so that by the 5th semiconductor The voltage that the parasitic bipolar element in area, the 4th semiconductor region and semiconductor substrate composition starts rebound is lower than by institute The parasitic bipolar element for stating the second semiconductor region, first semiconductor region and semiconductor substrate composition starts rebound The mode of voltage sets the distance until the corner part to the 6th semiconductor region of the 4th semiconductor region.
In addition, semiconductor device of the invention is characterized in that, in the present invention as stated above, so that by the 5th semiconductor Area, the 4th semiconductor region and the semiconductor substrate composition parasitic bipolar element or by the 5th semiconductor The voltage that the parasitic bipolar element in area, the 6th semiconductor region and semiconductor substrate composition starts rebound is lower than by institute The parasitic bipolar element for stating the second semiconductor region, first semiconductor region and semiconductor substrate composition starts rebound The mode of voltage sets the impurity concentration of the 4th semiconductor region.
In addition, semiconductor device of the invention is characterized in that, in the present invention as stated above, by second semiconductor region, The 8th semiconductor region, gate insulating film and the grid of one conductivity type constitute the component structure of the semiconductor element.Described 8th Semiconductor region is selectively disposed in the inside of first semiconductor region in a manner of separating with second semiconductor region.Institute State grid via the gate insulating film be arranged in first semiconductor region be sandwiched in second semiconductor region with it is described On the surface of part between 8th semiconductor region.
In addition, semiconductor device of the invention is characterized in that, in above-mentioned invention, the semiconductor device is provided with First semiconductor region and the 4th semiconductor region formed by the same process.
In addition, semiconductor device of the invention is characterized in that, in above-mentioned invention, the semiconductor device is provided with The third semiconductor region and the 6th semiconductor region formed by the same process.
In addition, semiconductor device of the invention is characterized in that, in above-mentioned invention, the semiconductor device is provided with Second semiconductor region and the 5th semiconductor region formed by the same process.
In addition, semiconductor device of the invention is characterized in that, in above-mentioned invention, the semiconductor device is provided with The third semiconductor region and the 4th semiconductor region formed by the same process.
In addition, semiconductor device of the invention is characterized in that, in above-mentioned invention, also have to cover the described 5th The 9th semiconductor region between the 4th semiconductor region and the 5th semiconductor region is arranged in the mode of semiconductor region.
In addition, semiconductor device of the invention is characterized in that, and in above-mentioned invention, the of the 9th semiconductor region One conductive-type impurity concentration is higher than the first conductive type impurity concentration of the 4th semiconductor region.
In addition, semiconductor device of the invention is characterized in that, and in above-mentioned invention, the of the 9th semiconductor region Two conductive-type impurity concentration are higher than the second conductive type impurity concentration of the 4th semiconductor region.
In addition, semiconductor device of the invention is characterized in that, in above-mentioned invention, the 4th semiconductor region is institute State a part of third semiconductor region.
In addition, semiconductor device of the invention is characterized in that, in above-mentioned invention, above-mentioned semiconductor device is also equipped with The tenth semiconductor region~12 semiconductor regions of the second conductive type.Tenth semiconductor region with first semiconductor region and The mode of the 4th semiconductor region separation is selectively disposed on the superficial layer of the first interarea of the semiconductor substrate. The tenth semiconductor region is run through in the tenth semiconductor area in the depth direction, with the depth of the tenth semiconductor region with On depth be selectively set.12nd semiconductor region is selectively located at the surface in the tenth semiconductor area Layer.The impurity concentration of 12nd semiconductor region is higher than the impurity concentration in the tenth semiconductor area.Also, by described half The breakdown voltage ratio for the first diode that conductor substrate and the third semiconductor region are constituted is by the semiconductor substrate and described The breakdown voltage for the second diode that tenth semiconductor area is constituted is high.
In addition, semiconductor device of the invention is characterized in that, in above-mentioned invention, the of the semiconductor substrate On the surface of one interarea, the distance between the semiconductor substrate and the 6th semiconductor region are than the semiconductor substrate and institute It is big to state the distance between the tenth semiconductor area.
In addition, in order to solve the above problems, reaching the purpose of the present invention, for the manufacturer of semiconductor device of the invention Method has following feature in above-mentioned semiconductor device.By the injection of same impurity and impurity diffusion processing, carry out with mutual Isolated mode be formed selectively on the superficial layer of the first interarea of the semiconductor substrate first semiconductor region and The process of 4th semiconductor region.By the injection of same impurity and impurity diffusion processing, carry out in first semiconductor region Inside be formed selectively second semiconductor region, and be formed selectively institute in the inside of the 4th semiconductor region The process for stating the 5th semiconductor region.By the injection of same impurity and impurity diffusion processing, carry out being optionally formed in depth side The third semiconductor region of first semiconductor region is extended upward through, and is optionally formed on depth direction through institute The process for stating the 6th semiconductor region of the 4th semiconductor region.
According to foregoing invention, two pole of longitudinal type for the circuit portion being made of third semiconductor region and semiconductor substrate can be made Work of the operating resistance of pipe than the longitudinal type diode in the protection element portion being made of the 6th semiconductor region and semiconductor substrate Resistance is higher.Accordingly, when applying surge voltage, surge current can be absorbed by protection element portion.For this purpose, even if by micro- The diameter that type becomes the contact hole at the second semiconductor region of circuit portion and the joint portion of first electrode becomes smaller, and is also able to suppress Surge current focuses on the second semiconductor region and the joint portion of first electrode of circuit portion.Therefore, it can be improved entire semiconductor The surge resistance of device.
The manufacturing method of semiconductor device and semiconductor device according to the present invention, by having on same semiconductor substrate Standby circuit portion and the protection element for protecting the circuit portion, can be realized micromation, and can obtain the effect for improving surge resistance Fruit.In addition, the manufacturing method of semiconductor device according to the present invention and semiconductor device, can obtain inhibition in same semiconductor Have circuit portion on substrate and protects the effect of the cost of the semiconductor device of the protection element of the circuit portion.
Detailed description of the invention
Fig. 1 is the sectional view for indicating the structure of semiconductor device of embodiment 1.
Fig. 2 is the plan view for indicating the plane figure of semiconductor device of embodiment 1.
Fig. 3 is the explanatory diagram for illustrating the operating principle of semiconductor device of embodiment 1.
Fig. 4 is the performance plot for indicating the rebound characteristic of the semiconductor device of embodiment 1.
Fig. 5 is the sectional view for indicating the structure of semiconductor device of embodiment 2.
Fig. 6 is the sectional view for indicating the structure of semiconductor device of embodiment 3.
Fig. 7 is the sectional view for indicating the structure of semiconductor device of embodiment 4.
Fig. 8 is the plan view of plane figure in the protection element portion for indicate the semiconductor device of embodiment 4.
Fig. 9 is the performance plot of rebound characteristic in the protection element portion for indicate the semiconductor device of embodiment 4.
Figure 10 is the sectional view for indicating the structure of semiconductor device of embodiment 5.
Figure 11 is the sectional view for indicating the structure of semiconductor device of embodiment 6.
Figure 12 is other the exemplary sectional views for the structure of semiconductor device for indicating embodiment 6.
Figure 13 is the sectional view for indicating the structure of existing semiconductor device.
Figure 14 is the sectional view for indicating the structure of semiconductor device of embodiment 7.
Figure 15 is the plan view for indicating the plane figure of semiconductor device of embodiment 7.
Figure 16 is the performance plot for indicating the rebound characteristic of the semiconductor device of embodiment 7.
Figure 17 is the sectional view for indicating the structure of semiconductor device of embodiment 8.
Figure 18 is the plan view for indicating the plane figure of semiconductor device of embodiment 8.
Figure 19 is the sectional view for indicating the structure of semiconductor device of embodiment 9.
Figure 20 is the plan view for indicating the plane figure of semiconductor device of embodiment 9.
Figure 21 is other the exemplary sectional views for the structure of semiconductor device for indicating embodiment 9.
Figure 22 is the sectional view for indicating the structure of semiconductor device of embodiment 10.
Figure 23 is other the exemplary sectional views for the structure of semiconductor device for indicating embodiment 10.
Figure 24 is the sectional view for indicating the structure of semiconductor device of embodiment 11.
Figure 25 is the plan view for indicating the plane figure of semiconductor device of embodiment 11.
Figure 26 is the performance plot for indicating the rebound characteristic of the semiconductor device of embodiment 11.
Symbol description
1:n+Type supporting substrate
2:n-Type epitaxial layer
3: the groove of longitudinal type MOSFET
4: the gate insulating film of longitudinal type MOSFET
5: the grid of longitudinal type MOSFET
6: longitudinal type MOSFET p-type base area
7: the n of longitudinal type MOSFET+Type source region
8: the p of longitudinal type MOSFET++Type contact zone
9: drain electrode
10: the longitudinal type MOSFET of output stage
11: the circuit element of circuit portion
12: the power circuit of circuit portion
13: the hot side n of circuit portion+Type diffusion region
20: the lateral type n-channel MOSFET of circuit portion
21: the p of lateral type n-channel MOSFET-Type base area
22: the n of lateral type n-channel MOSFET+Type source region
23: the n of lateral type n-channel MOSFET+Type drain region
24,44,83: the p of circuit portion+Type diffusion region
25: the p of circuit portion++Type contact zone
26a: the p of circuit portion++The contact portion of the wiring layer of type contact zone and earthing potential
26b, 28b, 29b: the contact hole of lateral type n-channel MOSFET
27: the grid of lateral type n-channel MOSFET
28a: the n of lateral type n-channel MOSFET+The contact portion of type source region and wiring layer
28b: the n of lateral type n-channel MOSFET+The contact portion in type drain region and wiring layer
30: the protection element in protection element portion
31: the p in protection element portion-Type diffusion region
32,62: the p in protection element portion++Type contact zone
33,63: the n in protection element portion+Type diffusion region
34,51,52,71~74,81,82: the p in protection element portion+Type diffusion region
35,65: wiring layer
36a, 37a, 66a, 67a: the contact portion with the wiring layer in protection element portion
36b, 37b: the contact hole in protection element portion
D1, D2: longitudinal type diode
I1, I 1a, I2, I2a: avalanche current
It1, It2: the electric current when rebound of parasitic bipolar element starts
R1: the p in protection element portion-The resistive element of type diffusion region
T1, T2: parasitic bipolar element
Vbv1, Vbv2: breakdown voltage
Vh1, Vh2: the voltage after the rebound of parasitic bipolar element
Vt1, Vt2: the rebound of parasitic bipolar element starts voltage
W1, w2, w11~w13:I-V waveform
X1: the p from protection element portion+Type diffusion region is to p++Distance until type contact zone
X11: the p of circuit portion+The width of type diffusion region
X12: the p of circuit portion++The width of type contact zone
X21: the p from protection element portion+Type diffusion region is to n+Distance until type diffusion region
X2: from the p of circuit portion+Type diffusion region is to n+Distance until type source region
X31: the p from protection element portion+The corner part of type diffusion region is to p++Distance until type contact zone
Specific embodiment
Hereinafter, the manufacturing method of the semiconductor device and semiconductor device that present invention will be described in detail with reference to the accompanying is preferred Embodiment.In the present description and drawings, it in the layer or region for being preceding embroidered with n or p, respectively indicates electronics or hole is more Number carrier.In addition, being marked on n or p+and-respectively indicate impurity concentration than it is unmarked+and-layer or region impurity it is dense It spends high and low.It should be noted that in the description of the following embodiments and the accompanying drawings, symbol identical to same structure tag, And the repetitive description thereof will be omitted.
(embodiment 1)
Hereinafter, being illustrated to the structure of the semiconductor device of embodiment 1.Fig. 1 is the semiconductor for indicating embodiment 1 The sectional view of the structure of device.The cross section structure at the cutting line A-A ' of Fig. 2 is shown in FIG. 1.Fig. 2 is to indicate embodiment 1 Semiconductor device plane figure plan view.Be omitted in Fig. 2 the plane figure in output stage portion diagram (Figure 15, It is also same in 18).Plane figure refers to the flat shape and configuration of each section that the face side from semiconductor substrate 100 is seen Structure.
In Fig. 1, an example of the semiconductor device as embodiment 1 is shown the longitudinal type n ditch of output stage Road power MOSFET, control circuit lateral type CMOS and protected from surge these MOSFET protection element 30 be arranged exist Vehicle-mounted high-voltage type Power IC on same semiconductor substrate (semiconductor chip).In circuit portion, control circuit is being constituted In the lateral type p-channel MOSFET and lateral type n-channel MOSFET of the complementary connection of lateral type CMOS, lateral type n ditch is only illustrated Road MOSFET 20.
Specifically, as shown in Figure 1, being configured with output stage separated from each other on N-shaped epitaxial substrate (semiconductor substrate) Portion, circuit portion and protection element portion, the N-shaped epitaxial substrate (semiconductor substrate) is in n+The positive upper layer of type supporting substrate 1 Folded n-Made of type epitaxial layer 2.In output stage portion, as the longitudinal type n-channel power MOSFET of output stage, it is configured with example Such as the longitudinal type MOSFET 10 of trench gate structure.In output stage portion, n+Type supporting substrate 1 and n-Type epitaxial layer 2 respectively as The drain electrode layer and drift layer of longitudinal type MOSFET 10 plays a role.In substrate face side (n-Type epitaxial layer 2 relative to n+Type branch The opposite side of 1 side of support group plate) it is provided with the mos gate pole structure of longitudinal type MOSFET 10.
The mos gate pole structure of longitudinal type MOSFET 10 is by groove 3, gate insulating film 4, grid 5, p-type base area 6, n+Type Source region 7 and p++The general trench gate structure that type contact zone 8 forms.Herein, the mos gate pole of longitudinal type MOSFET 10 is omitted The diagram of the plane figure of structure.n+Type source region 7 and p++Type contact zone 8 is connected to source electrode (source terminal), source terminal via Wiring layer (not shown) is electrically connected with the output terminal (out terminal) that substrate face side is arranged in.It is connected to substrate back (n+Type The back side of supporting substrate 1) longitudinal type MOSFET 10 drain electrode (drain terminal (second electrode)) 9 be, for example, supply voltage electricity Position VCC terminal.
As shown in Figure 1, 2, the lateral type CMOS or circuit element 11, power supply electricity of control circuit are provided in circuit portion The various circuits such as road 12.For example, being selectively provided with p in the superficial layer of substrate face in circuit portion-(the first half lead for base area Body area) 21, in p-The inside of base area 21 is separated from each other and is respectively selectively provided with the lateral type for constituting control circuit The n of the lateral type n-channel MOSFET 20 of CMOS+Type source region (the second semiconductor region) 22 and n+Type drain region (the 8th semiconductor region) 23。n+Type source region 22 and n+The depth in type drain region 23 can be with the n of such as longitudinal type MOSFET 10+The depth of type source region 7 is identical.
In p-Type base area 21 by n+Type source region 22 and n+On the surface of part folded by type drain region, across gate insulating film (not shown) is provided with grid 27.Grid 27 is arranged in for example linear plane figure.In Fig. 2, omit grid 27 with The diagram of outer electrode (wiring layer).In addition, being provided in the depth direction through p-Type base area 21 simultaneously reaches n-Type epitaxial layer 2 By p-Type base area 21 and n+The p of part folded by type supporting substrate 1+Type diffusion region (third semiconductor region) 24.p+Type diffusion region 24 in p-The periphery of type base area 21 is nearby with the n with lateral type n-channel MOSFET 20+Type source region 22 and n+What type drain region 23 separated Mode is arranged.
In addition, p+Type diffusion region 24 is set to for example substantially rectangular frame surrounded around lateral type n-channel MOSFET 20 In the plane figure of shape.In p+The inside of type diffusion region 24 can be configured with the unit list of multiple lateral type n-channel MOSFET 20 First (functional unit of element).p+The depth ratio p of type diffusion region 24-The depth of type base area 21 is deep, from p-Downside (the n of type base area 21+1 side of type supporting substrate) rise be projected into n-In type epitaxial layer 2.p+Type diffusion region 24 is as preventing because being layered in substrate face The current potential of wiring layer (not shown) and the p generated-The reversion of the reversion of type base area 21 prevents layer from playing a role.In addition, p+Type diffusion Area 24 is as preventing by the protection ring from influences such as other devices adjacent with lateral type n-channel MOSFET 20, noises It plays a role.
In p+The inside of type diffusion region 24 is selectively provided with and the p of wiring layer (not shown) Ohmic contact++Type contact Area 25.p++Type contact zone 25 is set to the rectangular box-like plane figure for example surrounded around lateral type n-channel MOSFET 20 On.p++The depth of type contact zone 25 can be with the p of such as longitudinal type MOSFET 10++The depth of type contact zone 8 is identical.For rear The rebound characteristic of the parasitic bipolar element T2 for the circuit portion stated, as long as the parasitic bipolar element T1 in protection element portion has rule Fixed rebound characteristic can be (referring to Fig. 4), according to p+The impurity concentration of type diffusion region 24 can also be not provided with p++Type contact zone 25.
Lateral type n-channel MOSFET 20 is shown in Fig. 1,2 in circuit portion for constituting the CMOS reverse phase of control circuit When the various inverter circuits such as device or ED phase inverter, resistance load inverter an example (Fig. 3,5,11,12,14,15, It is also same in 17~19,21,23).Therefore, it is connected to the n of lateral type n-channel MOSFET 20+Source electrode (the source of type source region 22 Extreme son (first electrode)) it is electrically connected with the GND terminal (GND liner) for the earthing potential that substrate face is arranged in.Constitute n+Type The contact hole 28b of the contact portion 28a of the wiring layer (source electrode) of source region 22 and source electric potential has the plane of such as rectangular shape Shape, and it is configured with one.
P as back grid-Type base area 21 is via p+Type diffusion region 24, p++Type contact zone 25 and wiring layer (not shown) with GND terminal electrical connection.Constitute the p of lateral type n-channel MOSFET 20++The contact of type contact zone 25 and the contact portion 26a of wiring layer Hole 26b has the flat shape of such as rectangular shape, and along p++The circumferencial direction of type contact zone 25 is provided with being dispersed in It is multiple.The n of lateral type n-channel MOSFET 20+Type drain region 23 via drain electrode (drain terminal) and lateral type p-channel MOSFET or Each element of the circuit elements 11 such as person's depletion type MOS FET, resistive element connects.
By the way that each element of these circuit elements 11 is connect with the drain terminal of lateral type n-channel MOSFET 20, from And constitute above-mentioned various inverter circuits.Constitute the n of lateral type n-channel MOSFET 20+The wiring layer in type drain region 23 and electric leakage position The contact hole 29b of the contact portion 29a of (drain electrode) has the flat shape of such as rectangular shape, and is configured with one.In addition, Circuit element 11 is connected to the hot side n on the superficial layer for being selectively arranged at substrate face via power circuit 12+ Type diffusion region 13.Power circuit 12 is made of high voltage bearing circuit element (not shown), receives the power supply potential of N-shaped epitaxial substrate (current potential of VCC terminal) and to circuit element 11 export low potential, to various inverter circuit supply line voltages.
As shown in Figure 1, 2, configured with the protection element 30 being made of longitudinal type diode in protection element portion.It is protecting In components department, on the superficial layer of substrate face, with the p with circuit portion-The isolated mode in type base area 21 is selectively provided with p- Type diffusion region (the 4th semiconductor region) 31.In p-The inside of type diffusion region 31 is selectively provided with p respectively++Type contact zone (the Seven semiconductor regions) 32, n+Type diffusion region (the 5th semiconductor region) 33 and p+Type diffusion region (the 6th semiconductor region) 34.p++Type contact Area 32 is configured in p-The substantially central portion of type diffusion region 31.p++Type contact zone 32 and 35 Ohmic contact of wiring layer.n+Type diffusion region 33 to surround p++The plane figure of the rectangular shape on the periphery of type contact zone 32 configures.
p+Type diffusion region 34 is in p-Near the periphery of type diffusion region 31, run through p in the depth direction-Type diffusion region 31 and arrive Up to n-Type epitaxial layer 2 is sandwiched in p-Type diffusion region 31 and n+Part between type supporting substrate 1.In addition, p+Type diffusion region 34 Such as in n+The outside of type diffusion region 33 is to surround n+The plane figure of the rectangular shape on the periphery of type diffusion region 33 configures.That is, In P+Type diffusion region 34 and p++N is configured between type contact zone 32+Type diffusion region 33.n+It type diffusion region 33 can be with p++Type contact Area 32 connects, can also with p++The isolated mode in type contact zone 32 configures.p+It type diffusion region 34 can be with n+Type diffusion region 33 Connect, can also with n+The isolated mode in type diffusion region 33 configures.p+The depth ratio p of type diffusion region 34-The depth of type diffusion region 31 Degree is deep, passes through p+Type diffusion region 34 and n-Pn-junction between type epitaxial layer 2 constitutes longitudinal type diode.
p-Type diffusion region 31, p++Type contact zone 32, n+Type diffusion region 33 and p+The depth of type diffusion region 34 is for example preferably distinguished With the p of circuit portion-Type base area 21, p++Type contact zone 25, n+Type source region 22 and p+The depth of type diffusion region 24 is identical.The reason is that Can be utilized respectively the identical impurity injection in identical with the conductivity type, impurity concentration and the depth that configured in circuit portion diffusion region and Impurity diffusion process (impurity injection and impurity diffusion processing) forms each diffusion region in protection element portion.Accordingly, even if process Fluctuation, the deviation situation of the diffusion region of protection element portion and circuit portion also trend having the same.Therefore, being easy respectively will protection Components department and circuit portion are adjusted to defined acting characteristic.In addition, forming protection element portion and electricity on same semiconductor substrate When the portion of road, without increasing new process, therefore cost can be controlled.
p++Type contact zone 32 and n+Type diffusion region 33 is connect via wiring layer 35 with GND terminal.Constitute p++Type contact zone 32 And n+Contact hole 36b, 37b of contact portion 36a, 37a of type diffusion region 33 and wiring layer 35 are each configured with more than one more It is a.The state (part of the dotted smearing of rectangle) configured with multiple contact hole 36b, 37b is shown in FIG. 2.Preferably comprise protection The n of components department+N of the quantity of the contact hole 37b of the contact portion 37a of type diffusion region 33 and wiring layer 35 than constituting circuit portion+Type source The quantity of the contact hole 28b of the contact portion 28a of the wiring layer (not shown) of area 22 and source electric potential (earthing potential) is more.In addition, excellent Select the n in protection element portion+Type diffusion region 33 and p-Type diffusion region 31 is formed by the n of pn-junction area ratio circuit portion+22 He of type source region p-It is big that type base area 21 is formed by pn-junction area.In protection element portion, by by the quantity or n of contact hole 37b+Type diffusion Area 33 and p-The pn-junction area of type diffusion region 31 or above-mentioned the two are set to above-mentioned condition, so that the parasitism with circuit portion is double Polar form element T2 is compared, and can be improved the breakdown potential flow of the parasitic bipolar T1 in protection element portion.For aftermentioned circuit portion Parasitic bipolar element T2 rebound characteristic, as long as the parasitic bipolar element T1 in protection element portion has defined rebound spy Property can (referring to Fig. 4), according to p-The impurity concentration of type diffusion region 31 can be not provided with p++Type contact zone 32.In such case Under, in p-Type diffusion region 31 by n+The substantially central portion that type diffusion region 33 surrounds is formed for contacting with what wiring layer 35 contacted Hole 37b.
Next, being illustrated to the movement of the semiconductor device of embodiment 1.Fig. 3 is to illustrate partly leading for embodiment 1 The explanatory diagram of the operating principle of body device.Fig. 4 is the performance plot for indicating the rebound characteristic of the semiconductor device of embodiment 1.Such as Shown in Fig. 3, pass through p respectively+34,24 and n of type diffusion region-Pn-junction between type epitaxial layer 2 is formed in protection element portion and circuit portion There are longitudinal type diode D1, D2.Firstly, referring to the schematic diagram of movements of Fig. 3 and current-voltage (I-V) the waveform w2 of Fig. 4 to circuit The movement of circuit portion when portion's individualism is illustrated.If surge voltage invades and makes the voltage of VCC terminal from VCC terminal Rise and reach first voltage (hereinafter referred to as breakdown voltage) Vbv2 to the application voltage of circuit portion, then longitudinal type diode D2 Pass through p+Type diffusion region 24 and n-Pn-junction breakdown between type epitaxial layer 2, electric current (avalanche current) I2 start to flow.According to snowslide The positive carrier (hole) that electric current I2 is generated in longitudinal type diode D2 is via p+Type diffusion region 24 is from p++Type contact zone 25 is logical It crosses wiring layer and flows into GND terminal.Moreover, with to the application voltage of circuit portion rise and avalanche current I2 increase, longitudinal type two The breakdown position of pole pipe D2 is to p+Type diffusion region 24 and n-The whole of pn-junction face between type epitaxial layer 2 expands, the generation of carrier Region expands.Along with this, avalanche current I2 reaches p++It flows before type contact zone 25 very over long distances, in p+Type diffusion region 24 In, due to meeting from breakdown position to p++Voltage drop caused by the resistive element of the distance of type contact zone 25 becomes larger.If to The application voltage of circuit portion increases to defined electric current It2 further up into second voltage Vt2, avalanche current I2, then in p+ The voltage drop of type diffusion region 24 is more than p-Type base area 21 and n+The forward voltage of pn-junction between type source region 22.Accordingly, p-Type base area 21 and n+Pn-junction between type source region 22 is forward biased, and the one part of current I2a of avalanche current I2 flows to n+22 side of type source region. Flow to the n+The electric current I2a of 22 side of type source region becomes base current, by n+Type source region 22, p-Type base area 21 and n-Type epitaxial layer 2 forms Parasitic bipolar element T2 become on state, knock-on.At this point, the voltage for being applied to circuit portion, which drops to, compares longitudinal type The breakdown voltage Vbv2 of diode D2 low voltage Vh2.
Then, protection when referring to the I-V waveform w1 of the schematic diagram of movements of Fig. 3 and Fig. 4 to protection element portion individualism The movement of components department is illustrated.If surge voltage from VCC terminal invade and make VCC terminal voltage rise and to protection member The application voltage of part reaches first voltage (breakdown voltage) Vbv1, then longitudinal type diode D1 passes through p+Type diffusion region 34 and n-Type Pn-junction breakdown between epitaxial layer 2, avalanche current I1 start to flow.It is generated according to avalanche current I1 in longitudinal type diode D1 Positive carrier (hole) is via p+Type diffusion region 34 and p-Type diffusion region 31, by wiring layer 35 from p++Type contact zone 32 flows into GND terminal.The operating resistance of longitudinal type diode D1 passes through p-Resistive element R1 in type diffusion region 31 becomes bigger.If To protection element portion application voltage is further up into second voltage Vt1 and avalanche current I1 increases to rated current It1, then Pass through p-Resistive element R1 in type diffusion region 31 is in p-The voltage drop that type diffusion region 31 generates is more than p-Type diffusion region 31 and n+Type The forward voltage of pn-junction between diffusion region 33.Accordingly, p-Type diffusion region 31 and n+Pn-junction between type diffusion region 33 is by forward bias It sets, the one part of current I1a of avalanche current I1 flows to n+33 side of type diffusion region.Flow to the n+The electric current I1a of 33 side of type diffusion region at For base current, by n+Type diffusion region 33, p-Type diffusion region 31 and n-The parasitic bipolar element T1 that type epitaxial layer 2 forms becomes leading Logical state, knock-ons.At this point, the voltage for being applied to protection element portion drops to the breakdown voltage than longitudinal type diode D1 Vbv1 low voltage Vh1.In Fig. 3, symbol I1b, I2b indicate the avalanche current that GND terminal is flowed into via wiring layer 35.
The longitudinal type diode D1 in the more above-mentioned protection element portion and longitudinal type diode D2 of circuit portion.Two pole of longitudinal type The p of pipe D1, D2 due to constituting each pn-junction+The condition (impurity concentration and diffusion depth) of type diffusion region 34,24 is almost the same, because This breakdown voltage Vbv1, Vbv2 is equal.On the other hand, protection element portion and circuit portion are different in terms of following two.First Difference is as described below.In circuit portion, due to avalanche current I2 longitudinal type diode D2 generate positive carrier only By p+Type diffusion region 24 and reach p++Type contact zone 25.In contrast, in protection element portion, since avalanche current I1 is vertical The positive carrier generated to type diode D1 is via impurity concentration ratio p+The low p in type diffusion region 34-Type diffusion region 31 and reach p++Type contact zone 32.Therefore, the operating resistance of the longitudinal type diode D1 in protection element portion becomes two pole of longitudinal type than circuit portion The operating resistance of pipe D2 is high.Accordingly, between the first voltage Vbv1- second voltage Vt1 in the I-V waveform w1 in protection element portion The gradient of avalanche current I1 is than the avalanche current between the first voltage Vbv2- second voltage Vt2 in circuit portion I-V waveform w2 The gradient of I2 is slow.That is, breakdown voltage Vbv1, Vbv2 or more application voltage in, two pole of longitudinal type in protection element portion The incrementss of the avalanche current I1 of pipe D1 are smaller than the incrementss of the avalanche current I2 of the longitudinal type diode D2 of circuit portion.
Second difference is as described below.It is different from circuit portion in protection element portion, n+Type diffusion region 33 is configured in quilt It is clipped in p+Type diffusion region 34 and p++Position between type contact zone 32.Therefore, in most of snowslide electricity of protection element portion flowing It flows I1 to flow near the route of wiring layer 35, there are p-Type diffusion region 31 and n+Pn-junction between type diffusion region 33.Therefore, because Avalanche current I1, p-Type diffusion region 31 and n+Pn-junction between type diffusion region 33 becomes easy forward bias, also, also by vertical It is influenced to the height of the operating resistance of type diode D1, the parasitic bipolar element T1 in protection element portion is more double than the parasitism of circuit portion Polar form element T2 is easier to knock-on.In addition, the electric current when rebound of the parasitic bipolar element T1 in protection element portion starts Electric current It2 when It1 starts than the rebound of the parasitic bipolar element T2 of circuit portion is small (It1 < It2).At this point, protection element portion Parasitic bipolar element T1 start rebound second voltage (hereinafter referred to as rebound start voltage (snap-back starting Voltage)) Vt1 is set as starting the second voltage of rebound than the parasitic bipolar element T2 of circuit portion (rebound starts voltage) Vt2 low (Vt1 < Vt2).The adjustment that rebound starts voltage Vt1, Vt2 can be by adjusting p-Resistive element in type diffusion region 31 R1 is realized.Specifically, the adjustment that rebound starts voltage Vt1, Vt2 can be by adjusting p in protection element portion-Type diffusion The impurity concentration in area 31 carries out, can also be by adjusting from p+P is arrived in type diffusion region 34++The distance x1 of type contact zone 32 come into Row, can also be by adjusting from p+N is arrived in type diffusion region 34+The distance of type diffusion region 33 carries out, can also by merge adjustment this Come carry out.
Circuit portion and protection element portion with this characteristic configure on same semiconductor substrate.Therefore, when surge electricity When pressure is invaded from VCC terminal, in the rebound for the parasitic bipolar element T1 for rising to protection element to the application voltage of circuit portion Parasitic bipolar element T1 starts to knock-on when starting voltage Vt1, and surge current protected element portion absorbs.That is, even if surge is electric Pressure is invaded from VCC terminal, and the parasitic bipolar element T2 of circuit portion does not also knock-on.Therefore, by micromation, even if constituting The n of lateral type n-channel MOSFET 20+The diameter of the contact hole 28b of the contact portion 28a of type source region 22 and wiring layer becomes smaller, electric current It will not concentrate, therefore will not puncture to contact hole 28b.On the other hand, for protection element portion, if with existing The p of (referring to Fig.1 3)+Type diffusion region 131 to same extent ensures p-The occupied area of type diffusion region 31 then can be configured more Contact hole 36b, 37b with contact portion 36a, 37a of wiring layer 35 are constituted, or can singly be matched with wider width It sets.Accordingly, since the breakdown current of contact hole 36b, 37b can be made to become larger, so contact hole 36b, 37b will not be because of protection elements The rebound of the parasitic bipolar element T1 in portion and be immediately destroyed, can be improved the breakdown potential flow in protection element portion.Therefore, i.e., Make the surge resistance that also can be improved Power IC in the case where realization micromation.
As described above, running through the p in protection element portion in the depth direction by being arranged according to embodiment 1-Type diffusion region And there is p-The p more than depth of type diffusion region+Type diffusion region, and in p+Type diffusion region and p++GND is arranged between contact zone in type The n of current potential+Type diffusion region can make longitudinal type two pole of the operating resistance of the longitudinal type diode in protection element portion than circuit portion The operating resistance of pipe is high.Accordingly, when being applied with surge voltage, surge current can be absorbed by protection element portion.Therefore, i.e., Make by the way that the n for making to constitute lateral type n-channel MOSFET is miniaturized+The diameter of the contact hole of the contact portion of type source region and wiring layer becomes It is small, it is also possible to enough to inhibit surge current to the n of the lateral type n-channel MOSFET of circuit portion+The contact portion of type source region and wiring layer It concentrates.Therefore, it can be improved the surge resistance of Power IC entirety.
In addition, according to embodiment 1, due to can use respectively in circuit portion impurity concentration and depth it is identical each The identical impurity injection in diffusion region and impurity diffusion process are formed simultaneously each diffusion region in protection element portion, and there is no need to increase New process, is able to suppress increased costs.In addition, according to embodiment 1, by utilizing the injection of same impurity and impurity diffusion work Sequence is formed simultaneously the diffusion region in protection element portion and the diffusion region of circuit portion, so that protection element portion and circuit portion become identical Diffusion layer constitute, therefore because process fluctuation caused by parasitic bipolar element rebound start electric current deviation in protection element Portion and circuit portion trend having the same.Therefore, parasitic bipolar element can be kept to open in protection element portion and circuit portion The balance of size of current relationship when beginning to knock-on is able to carry out stable protection act for process fluctuation.
(embodiment 2)
Next, being illustrated to the structure of the semiconductor device of embodiment 2.Fig. 5 is to indicate partly leading for embodiment 2 The sectional view of the structure of body device.The state when semiconductor device of embodiment 2 is acted is shown in FIG. 5 (in Fig. 6 (a), also identical in 11,12).The semiconductor device of the semiconductor device and embodiment 1 of embodiment 2 the difference lies in that Make the p for constituting longitudinal type diode D2 in circuit portion+The part width x11 of type diffusion region 44 extends inwardly.Specifically, For p+The width x11 of type diffusion region 44, in the n with lateral type n-channel MOSFET 20+In the opposite part of type source region 22, expand Width is from p-The periphery of type base area 21 nearby reaches n+The degree of type source region 22.p+Type diffusion region 44 can with n+Type source region 22 A part overlapping mode configure.It is selectively arranged at p+The p of the inside of type diffusion region 44++The width of type contact zone 45 X12 can be with p+The width x11 of type diffusion region 44 is accordingly widened.p++It type contact zone 45 can be with n+Type source region 22 connects.
By widening p+The width x11 of type diffusion region 44, thus even if as caused by longitudinal type diode D2 breakdown Avalanche current I2 increases and the generating region of carrier is caused to broaden, and can also make avalanche current I2 a part flows to n+Type source The electric current I2a of 22 side of area passes through low-resistance p+The ratio of type diffusion region 44 becomes more.Therefore, there is the parasitic bipolar for making circuit portion The electric current It2 that type element T2 starts rebound becomes larger, and the rebound for improving the parasitic bipolar element T2 of circuit portion starts voltage Vt2 Effect (referring to Fig. 4).Accordingly, when surge voltage is invaded from VCC terminal, it is easy to be formed in the parasitic bipolar of circuit portion The composition for making the parasitic bipolar element T1 in protection element portion knock-on before element T2 improves in the design of protection element portion Freedom degree.
As described above, effect same as embodiment 1 can be obtained according to embodiment 2.
(embodiment 3)
Hereinafter, being illustrated to the structure of the semiconductor device of embodiment 3.Fig. 6 is the semiconductor for indicating embodiment 3 The sectional view of the structure of device.The cross section structure in protection element portion is shown in FIG. 6, is omitted and is formed in protection element portion The diagram of circuit portion and output stage portion on same semiconductor substrate.The circuit portion and output of the semiconductor device of embodiment 3 The structure in grade portion is identical as the semiconductor device of embodiment 1 (referring to Fig.1).In addition, the electricity of the semiconductor device of embodiment 3 The structure in road portion and output stage portion, can also be identical as the semiconductor device of embodiment 2 (referring to Fig. 5).The half of embodiment 3 Conductor device, the difference lies in that in protection element portion, is constituting longitudinal type diode with the semiconductor device of embodiment 1 The p of D1+The inside of type diffusion region 51,52 is configured with n+Type diffusion region 33.It is configured at p-The p of the substantially central portion of type diffusion region 33++ Type contact zone 32 can with p+The isolated mode in type diffusion region 51 configures (Fig. 6 (a)), also can be only fitted to p+Type diffusion region 52 Inside (Fig. 6 (b)).
As shown in Fig. 6 (a), by p+The inside of type diffusion region 51 configures n+Type diffusion region 33, can reduce with from longitudinal direction The breakdown position of type diode is to p++The corresponding p of the distance of type contact zone 32-Resistive element R1 in type diffusion region 31.Therefore, It can be with p-The reduction amount of resistive element R1 in type diffusion region 31 accordingly increases the parasitic bipolar element in protection element portion Start electric current It1 when rebound.Furthermore it is possible to and p-The reduction amount of resistive element R1 in type diffusion region 31 accordingly improves guarantor The rebound of the parasitic bipolar element in protection element portion starts voltage Vt1.Hereby it is possible to make to cause protection element portion due to noise The malfunction (referring to Fig. 4) of parasitic bipolar element rebound is difficult to occur.Noise refers to for example in the voltage lower than surge voltage Under may cause IC malfunction abnormal voltage.The adjustment for starting voltage (second voltage) Vt1 for rebound, in protection element It, can be by adjusting p in portion-The impurity concentration of type diffusion region 31 carries out, can also be by adjusting from p+P is arrived in type diffusion region 51++The distance of type contact zone 32 carries out, and can also be carried out by adjusting them compoundly.
In addition, as shown in Fig. 6 (b), can by with p-The mode that type diffusion region 31 is almost overlapped configures p+Type diffusion region 52, in p+The inside of type diffusion region 52 configures p++Type contact zone 32 and n+Type diffusion region 33.Shown in Fig. 6 (b) width with p- The wide p of the degree of two corner part 31a overlapping of type diffusion region 31+Type diffusion region 52.Hereby it is possible to be further reduced p-Type Resistive element (not shown) in diffusion region 31, additionally it is possible to be difficult to happen the above-mentioned malfunction due to caused by noise.For returning The adjustment for jumping beginning voltage Vt1 can be by adjusting p in protection element portion-Type diffusion region 31 and p+Type diffusion region 52 it is miscellaneous Matter concentration carries out.
As described above, can be obtained and embodiment 1,2 identical effects according to embodiment 3.
(embodiment 4)
Hereinafter, being illustrated to the structure of the semiconductor device of embodiment 4.Fig. 7 is the semiconductor for indicating embodiment 4 The sectional view of the structure of device.The cross section structure in the protection element portion of Fig. 8 is shown in FIG. 7, omission is formed with protection element portion The diagram of circuit portion and output stage portion on same semiconductor substrate.Fig. 8 is the guarantor for indicating the semiconductor device of embodiment 4 The plan view of plane figure in protection element portion.Be omitted in fig. 8 the plane figure in circuit portion and output stage portion diagram ( It is also identical in Figure 20).Fig. 9 is the performance plot of the rebound characteristic in the protection element portion for indicate the semiconductor device of embodiment 4. The circuit portion of the semiconductor device of embodiment 4 and the (reference identical as the semiconductor device of embodiment 1 of the structure in output stage portion Fig. 1).The semiconductor device of the semiconductor device and embodiment 1 of embodiment 4 the difference lies in that making protection element portion Structure becomes almost the same composition with the structure of circuit portion.
Specifically, as shown in Figure 7,8, in protection element portion, as being connected between the wiring layer 35 of GND terminal Contact portion p++Type contact zone 62 and n+The configuration of type diffusion region 63 is different from embodiment 1.More specifically, n+Type diffusion Area 63 is configured in p-The substantially central portion of type diffusion region 31.Constitute the p of longitudinal type diode D1+Type diffusion region 34 is in p-Type expands Dissipate the periphery and n in area 31+Type diffusion region 63 separates, and surrounds n+Mode around type diffusion region 63 configures.p++Type connects The configuration of area 62 is touched in p+The inside of type diffusion region 34.Symbol 66a, 67a indicate p++Type contact zone 62 and n+Type diffusion region 63 and cloth The contact portion of line layer 35.Symbol 66b, 67b are respectively indicated for by p++Type contact zone 62 and n+Type diffusion region 63 and wiring layer 35 The contact hole (the rectangular part of the painting of Fig. 8) of contact.
In this way, the p in protection element portion++Type contact zone 62, n+Type diffusion region 63 and p+The p of type diffusion region 34 and circuit portion++ Type contact zone 25, n+Type source region 22 and p+Type diffusion region 24 similarly configures.As shown in figure 9, by adjusting from protection element portion p+N is arrived in type diffusion region 34+Distance x21 until type diffusion region 63, the parasitic bipolar element T1 in adjustable protection element portion are opened Electric current It1 and rebound when beginning to knock-on start voltage Vt1.For example, the p from protection element portion+N is arrived in type diffusion region 34+Type diffusion region Distance x21 until 63 is longer, and the electric current It1 that the parasitic bipolar element T1 in protection element portion starts when knock-oning is smaller, more holds Easily knock-on.Therefore, by adjusting from the p in protection element portion+N is arrived in type diffusion region 34+Distance x21 until type diffusion region 63, It can make the parasitic bipolar member in protection element portion before the parasitic bipolar element T2 of circuit portion in the same manner as embodiment 1 Rebound (referring to Fig. 4) occurs for part T1.As long as specifically, making the p from protection element portion+N is arrived in type diffusion region 34+Type diffusion region 63 Until distance x21 than the p from circuit portion+N is arrived in type diffusion region 24+Distance x2 (referring to Fig.1) until type source region 22 is long (x21>x2).In addition, the adjustment for starting voltage Vt1 for rebound can be by adjusting p in protection element portion-Type diffusion region 31 impurity concentration carries out.
In addition it is also possible to make the structure of circuit portion (ginseng identical as the structure of the circuit portion of the semiconductor device of embodiment 2 According to Fig. 5.That is x2≤0).
As described above, can be obtained and embodiment 1,2 identical effects according to embodiment 4.
(embodiment 5)
Hereinafter, being illustrated to the structure of the semiconductor device of embodiment 5.Figure 10 is to indicate partly leading for embodiment 5 The sectional view of the structure of body device.The cross section structure in protection element portion is shown in FIG. 10, omission is formed in protection element portion The diagram of circuit portion and output stage portion on same semiconductor substrate.The circuit portion and output of the semiconductor device of embodiment 5 The structure in grade portion is identical as the semiconductor device of embodiment 1 (referring to Fig.1).In addition, the electricity of the semiconductor device of embodiment 5 The structure in road portion and output stage portion can be identical as the semiconductor device of embodiment 2 (referring to Fig. 5).Embodiment 5 is partly led Body device, the difference lies in that in protection element portion, makes to constitute longitudinal type diode D1 with the semiconductor device of embodiment 1 P+The depth and p of type diffusion region 71-The depth of type diffusion region 31 is identical (Figure 10 (a)).That is, in embodiment 5, protection member The breakdown position of the longitudinal type diode D1 in part portion is p+Type diffusion region 71 and n-Pn-junction between type epitaxial layer 2.
By making p+The depth of type diffusion region 71 in p+The p of avalanche breakdown degree occurs for the bottom of type diffusion region 71-Type expands The depth for dissipating area 31 is almost the same, to form p so as to shorten+For the heat treatment time of diffusion impurity when type diffusion region 71. Hereby it is possible to inhibit p+The transverse direction (direction parallel with substrate face) of type diffusion region 71 is spread, and is conducive to the micromation of circuit, Cost can be controlled.Furthermore, it is possible to embodiment 5 is applied to embodiment 3,4, using making to constitute snowslide in protection element portion Puncture the p at position+The depth and p of type diffusion region 72~74-The identical structure of the depth of type diffusion region 31 (Figure 10 (b)~Figure 10 (d)).In Figure 10 (b), 10 (c), shows and apply reality in the semiconductor device (referring to Fig. 6 (a), 6 (b)) of embodiment 3 Apply the situation of mode 5.In Figure 10 (d), shows and apply embodiment party in the semiconductor device (referring to Fig. 7) of embodiment 4 The situation of formula 5.
Figure 10 (e) indicates the variation of Figure 10 (a).In the variation shown in Figure 10 (e), p+The depth of type diffusion region 71 Compare p-The slightly shallower in depth of type diffusion region 31.Even in this case, by so that protection element portion avalanche breakdown position at For p+The mode of the bottom of type diffusion region 71 forms p+Type diffusion region 71 can play effect identical with structure shown in Figure 10 (a) Fruit.p+As long as the pressure resistance of the depth protection element of type diffusion region 71 is by p+The depth that the bottom of type diffusion region 71 determines.
It is also the same in Figure 10 (b), 10 (c) and 10 (d), p+The depth of type diffusion region 71 can compare p-Type diffusion region 31 Slightly shallower in depth.
As described above, effect identical with Embodiments 1 to 4 can be obtained according to embodiment 5.
(embodiment 6)
Hereinafter, being illustrated to the structure of the semiconductor device of embodiment 6.Figure 11 is to indicate partly leading for embodiment 6 The sectional view of the structure of body device.Figure 12 is another the exemplary section for the structure of semiconductor device for indicating embodiment 6 Figure.The circuit portion of the semiconductor device of embodiment 6 and the composition in output stage portion are identical as the semiconductor device of embodiment 1. The semiconductor device of embodiment 6 is with the semiconductor device of embodiment 1 the difference lies in that being not provided in protection element portion p-Type diffusion region, and utilize and constitute p++Type contact zone (the 6th semiconductor region) 32, n+Type diffusion region 33 and longitudinal type diode D1 P+Type diffusion region (the 4th semiconductor region) 81 constitutes protection element portion.
Specifically, as shown in figure 11, in protection element portion, with the p on the superficial layer of substrate face with circuit portion- The isolated mode in type base area 21 is selectively provided with p+Type diffusion region 81.In p+The inside of type diffusion region 81 is respectively selectively It is provided with p++Type contact zone 32 and n+Type diffusion region 33.p++Type contact zone 32 is configured in p+The substantially central portion of type diffusion region 81. For the rebound characteristic of the parasitic bipolar element T2 of circuit portion, as long as the parasitic bipolar element T1 in protection element portion has rule Fixed rebound characteristic can be (referring to Fig. 4), according to p+The impurity concentration of type diffusion region 81 can also be not provided with p++Type contact zone 32.In this case, in p+Type diffusion region 81 by n+The substantially central portion that type diffusion region 33 surrounds is formed with composition and wiring The contact hole 36b of the contact portion of layer 35.n+Type diffusion region 33 with p++Type contact zone 32 separates, and surrounds p++The week of type contact zone 32 The plane figure for the rectangular shape enclosed configures.That is, being formed in protection element portion by n+Type diffusion region 33, p+Type diffusion region 81 and n-The parasitic bipolar element T1 that type epitaxial layer 2 forms.
p++Type contact zone 32, n+Type diffusion region 33 and p+The depth of type diffusion region 81 for example preferably respectively with the p of circuit portion++ Type contact zone 25, n+Type source region 22 and p+The depth of type diffusion region 24 is identical.The reason is that can be utilized respectively and configure in electricity Conductivity type, the identical impurity injection of impurity concentration and the identical diffusion region of depth and (the impurity injection of impurity diffusion process in road portion With impurity diffusion handle) formed protection element portion each diffusion region.
When using such composition, p+Corner part (lower outer periphery end) 81a of type diffusion region 81 becomes longitudinal type diode The breakdown position of D2.Therefore, by adjusting from p+Corner part 81a to the p of type diffusion region 81++Distance until type contact zone 32 X31, so that in the same manner as embodiment 1 posting for protection element portion can be made before the parasitic bipolar element T2 of circuit portion Rebound (referring to Fig. 4) occurs for raw bipolar components T1.As long as specifically, making from p+Corner part 81a to the p of type diffusion region 81++ Distance x31 until type contact zone 32 is than the p from circuit portion+N is arrived in type diffusion region 24+Distance x2 long until type source region 22 (x31>x2)。
Compared with the protection element portion of the circuit portion of Figure 11 and Fig. 1, the protection element portion of Figure 11 can lose p-Type diffusion region Electric field alleviation effects, therefore be easy avalanche breakdown.Therefore, in the breakdown voltage Vbv1 in protection element portion and the breakdown of circuit portion Between voltage Vbv2, the relationship of Vbv1 < Vbv2 is set up.Accordingly, compared with when only adjusting operating resistance, it is easier to by protection element The rebound in portion starts the value that voltage Vt1 is adjusted to smaller than the rebound beginning voltage Vt2 of circuit portion.Further, since can save Protection element portion forms p-The process of type diffusion region, thus, for example forming each diffusion in protection element portion by different processes When area and each diffusion region between circuit portion, it is possible to reduce process number reduces cost.Start the tune of voltage Vt1 for rebound It is whole, it, can be by adjusting p in protection element portion+The impurity concentration of type diffusion region 81 carries out.
As shown in figure 12, the p that longitudinal type diode D1 is constituted in protection element portion can be made+The depth of type diffusion region 82 With the p for constituting longitudinal type diode D2 in circuit portion+The depth of type diffusion region 83 and the p of circuit portion-The depth phase of type base area 21 Together.
As described above, according to embodiment 6, even if being not provided with p in protection element portion-When type diffusion region, it can also take Obtain effect identical with Embodiments 1 to 5.
(embodiment 7)
Hereinafter, being illustrated to the structure of the semiconductor device of embodiment 7.Figure 14 is to indicate partly leading for embodiment 7 The sectional view of the structure of body device.The cross section structure at the cutting line B-B ' of Figure 15 is shown in FIG. 14.Figure 15 is to indicate to implement The plan view of the plane figure of the semiconductor device of mode 7.The lateral type n-channel configured with multiple circuit portions is shown in FIG. 15 The situation of the unit cell of MOSFET 20.The difference of the semiconductor device of the semiconductor device and embodiment 6 of embodiment 7 Point is, the p of longitudinal type diode D1 is constituted in protection element portion+Type diffusion region 82 and the p+N inside type diffusion region 82+ The diffusion region (the 9th semiconductor region) 91 of N-shaped or p-type is provided between type diffusion region 33.Diffusion region 91 has adjustment protection member The rebound of the parasitic bipolar element T1 of part 30 starts the function of voltage Vt1.
Specifically, as shown in figure 14, diffusion region 91 is in p+The inside of type diffusion region 82 covers n+Type diffusion region 33 it is whole A lower part (n+The part of 1 side of type supporting substrate) mode be arranged.In addition, diffusion region 91 with p++The isolated side in type contact zone 32 Formula configuration.Diffusion region 91 is in p+N-type diffusion region or p-type made of p-type impurity or n-type impurity are imported in type diffusion region 82 Diffusion region, such as heat treatment by ion implanting and for activation are formed.To p+Type diffusion region 82 import n-type impurity and When forming diffusion region 91, n-type impurity concentration ratio p is formed+The diffusion region 91 of the highly concentrated p-type of the n-type impurity of type diffusion region 82.With It is not provided with comparing when diffusion region 91, the n-type impurity concentration of the diffusion region 91 of p-type is higher, the parasitic bipolar member of protection element 30 The rebound of part T1, which starts voltage Vt1, becomes higher.
On the other hand, to p+When type diffusion region 82 imports p-type impurity and forms diffusion region 91, p-type impurity concentration is formed Compare p+The diffusion region 91 of the highly concentrated p-type of the p-type impurity of type diffusion region 82.In this case, by importeding into p+Type diffusion region 82 P-type impurity dosage determine diffusion region 91 conductivity type.As the p-type impurity concentration ratio p of diffusion region 91+The p of type diffusion region 82 When type impurity concentration is low, impurity concentration ratio p is formed+The diffusion region 91 of the low p-type of the impurity concentration of type diffusion region 82.Work as diffusion region 91 p-type impurity concentration ratio p+When the n-type impurity concentration of type diffusion region 82 is high, p+A part of type diffusion region 82 be reversed to N-shaped and Form the diffusion region 91 of N-shaped.Compared with when being not provided with diffusion region 91, the p-type impurity concentration of the diffusion region 91 of N-shaped is higher, protection The rebound of the parasitic bipolar element T1 of element 30, which starts voltage Vt1, becomes lower.
As shown in figure 15, n+Type diffusion region 33 is configurable to the plane figure of such as substantially linear.p++Type contact zone 32 for example can be with n+The length direction (direction linearly extended) of type diffusion region 33, which is configured in parallel in, passes through n+Type diffusion region On 33 straight line.Diffusion region 91 is configured to covering n+The plane figure of such as substantially linear around type diffusion region 33.Constitute n+ The contact hole 37b of the contact portion 37a (referring to Fig.1 4) of type diffusion region 33 and wiring layer (not shown) has for example substantially rectangular shape The flat shape of shape, and along n+The mode of the length direction dispersion of type diffusion region 33 is provided with multiple.Constitute p++Type contact The contact hole 36b of the contact portion of area 32 and wiring layer has the flat shape of such as rectangular shape, and is configured with one.Electricity The composition in road portion and output stage portion is identical as embodiment 6.
Hereinafter, being illustrated to the movement in protection element portion.Figure 16 is the rebound for indicating the semiconductor device of embodiment 7 The performance plot of characteristic.Embodiment when surge voltage invades from VCC terminal and increase the voltage of VCC terminal is shown in FIG. 16 1,2 and comparative example current-voltage (I-V) waveform.Embodiment 1 is the structure according to the semiconductor device of above embodiment 7 At the protection element 30 of the diffusion region 91 of setting N-shaped.Embodiment 2 is the composition according to the semiconductor device of above embodiment 7 The protection element 30 of the diffusion region 91 of p-type is set.Comparative example has and embodiment 1,2 other than being not provided with diffusion region 91 Identical composition, such as it is equivalent to the protection element 30 of embodiment 6.
As shown in figure 16, the rebound of the parasitic bipolar element T1 of embodiment 1 starts voltage Vt11 posting lower than comparative example The rebound of raw bipolar components T1 starts voltage Vt1.The rebound of the parasitic bipolar element T1 of embodiment 2 starts voltage Vt12 high Start voltage Vt1 in the rebound of the parasitic bipolar element T1 of comparative example.Therefore, the p-type impurity by adjusting diffusion region 91 is dense Degree or n-type impurity concentration, start voltage Vt1 so as to adjust the rebound of parasitic bipolar element T1 of protection element 30. Its adjustable range is the rebound beginning voltage Vt11 or more of the parasitic bipolar element T1 of embodiment 1 and posting for embodiment 2 The rebound of raw bipolar components T1 starts voltage Vt12 range X below.
Furthermore, it is possible to which the application implementation mode 2 in embodiment 7, is constituted longitudinal type diode to expand in circuit portion The p of D2+The width of type diffusion region 83 and the n for making itself and lateral type n-channel MOSFET 20+The side of a part overlapping of type source region 22 Formula configures p+Type diffusion region 83.Accordingly, identical as embodiment 2, the parasitic movement of lateral type n-channel MOSFET 20 is pressed down System, the rebound of the parasitic bipolar element T2 of circuit portion start voltage Vt2 and get higher.Accordingly, the parasitic bipolar of protection element 30 The difference that the rebound that the rebound of element T1 starts the parasitic bipolar element T2 of voltage Vt1 and circuit portion starts voltage Vt2 becomes larger, because This also can ensure that the space (margin) of parasitic movement.
As described above, effect identical with Embodiments 1 to 6 can be obtained according to embodiment 7.In addition, according to implementation Mode 7 is constituted the p of longitudinal type diode by covering in protection element portion+N inside type diffusion region+Type diffusion region it is whole The diffusion region of N-shaped or p-type is arranged in the mode of a lower part, and the rebound that can adjust the parasitic bipolar element of protection element starts Voltage.Accordingly, in order to which the rebound for adjusting the parasitic bipolar element of protection element starts voltage, without as above patent document 11 Ensure the width of the p-type diffusion region of the dead resistance for adjusting protection element portion like that, or without as above-mentioned patent Document 12 adds trigger element on the same substrate like that.Hereby it is possible to reduce the occupied area of protection element, therefore close The position for being easy to happen the position of rebound is easy to configuration protection element, and the freedom degree of circuit design is higher.In addition, even if more When a position configuration protection element, the freedom degree of circuit design is also got higher.
(embodiment 8)
Hereinafter, being illustrated to the structure of the semiconductor device of embodiment 8.Figure 17 is to indicate partly leading for embodiment 8 The sectional view of the structure of body device.The cross section structure at the cutting line C-C ' of Figure 18 is shown in FIG. 17.Figure 18 is to indicate to implement The plan view of the plane figure of the semiconductor device of mode 8.The semiconductor device of embodiment 8 and the semiconductor of embodiment 7 Device the difference lies in that will be provided with the protection element 40 of the diffusion region 91 of N-shaped or p-type in circuit portion as protection ring The p to play a role+83 integration of type diffusion region.That is, by being made of protection member the longitudinal type diode D2 for being formed in circuit portion Part 40 is configured with protection element 40 in the inside of circuit portion.
Specifically, as shown in Figure 17,18, for example, along the configuration surrounded around lateral type n-channel MOSFET20 At the p of the plane figure of rectangular shape+One side of type diffusion region 83 is configured with n in the plane figure of substantially linear+ Type diffusion region 33.In this case, p+P inside type diffusion region 83++Type contact zone 25 is along such as p+Type diffusion region 83 Remaining three sides and the plane figure for being configured to substantially C font.Accordingly, p+Type diffusion region 83 is configured with n+The portion of type diffusion region 33 Divide 83b to become protection element 40, is configured with p++The part 83a of type contact zone 25 plays a role as protection ring.
Diffusion region 91 with p++The isolated mode in type contact zone 25 is in p+The inside of type diffusion region 83 (83b) is configured to cover n+The plane figure of such as substantially linear around type diffusion region 33.Composition and embodiment other than the configuration of diffusion region 91 7 is identical.Herein, make protection element 40 and in p+The n with lateral type n-channel MOSFET 20 of type diffusion region 83+Type source region 22 Opposite one side integration, but protection element 40 and p can also be made+Other three sides integration of type diffusion region 83.Although omitting Diagram, but can in embodiment 7 application implementation mode 8, and with the protection element 40 configured inside circuit portion with match Set the protection element (symbol 30 of Figure 14) in the protection element portion on the outside of circuit portion.
In this way, even if under the protection element 40 that will be made of longitudinal type diode D2 and the integrated situation of protection ring, By to cover n+The diffusion region 91 of N-shaped or p-type is arranged in the mode of the entire lower part of type diffusion region 33, can obtain and implement The identical effect of mode 7.In addition, if in protection element portion 40 by n+Type diffusion region 33, p+Type diffusion region 83 and n-Type extension The parasitic bipolar element T1 of 2 composition of layer knock-ons, then avalanche current flows through the n of lateral type n-channel MOSFET 20+Type source Area 22 and p+The n of the inside of type diffusion region 83+Type diffusion region 33.With the longitudinal direction for being not provided with the parasitic movement of progress in protection ring It is compared when type diode D2, avalanche current is distributed to the n of lateral type n-channel MOSFET 20+Type source region 22 and p+Type diffusion region 83, Therefore can circulate bigger electric current.
As described above, according to embodiment 8, even if making protection element in circuit portion and playing a role as protection ring p+In the integrated situation in type diffusion region, effect identical with Embodiments 1 to 7 can be also obtained.In addition, according to embodiment 8, pass through the p for making protection element in circuit portion with playing a role as protection ring+The integration of type diffusion region, can be realized small-sized Change.
(embodiment 9)
Hereinafter, being illustrated to the structure of the semiconductor device of embodiment 9.Figure 19 is to indicate partly leading for embodiment 9 The sectional view of the structure of body device.The cross section structure at the cutting line D-D ' of Figure 20 is shown in FIG. 19.Figure 20 is to indicate to implement The plan view of the plane figure of the semiconductor device of mode 9.Figure 21 be indicate the semiconductor device of embodiment 9 structure it is another One exemplary sectional view.Figure 20, embodiment 9 shown in 21 semiconductor device be to be applied in embodiment 1,6 respectively The semiconductor device of embodiment 7.
Specifically, along the p for surrounding protection element portion++Rectangular shape is configured to around type contact zone 32 The n of plane figure+Type diffusion region 83, the diffusion region 92 in substantially rectangular cricoid plane figure configured with N-shaped or p-type. Diffusion region 92 is identical as embodiment 7, to cover n+The mode of the entire lower part of type diffusion region 33 is arranged.By adjusting the diffusion The p-type impurity concentration and n-type impurity concentration in area 92, thus identical as embodiment 7, the parasitism that can adjust protection element 30 is double The rebound of polar form element T1 starts voltage Vt1.
As described above, can be obtained and the identical effect of embodiment 1,6,7 according to embodiment 9.
(embodiment 10)
Hereinafter, being illustrated to the structure of the semiconductor device of embodiment 10.Figure 22 is indicate embodiment 10 half The sectional view of the structure of conductor device.Figure 23 is another exemplary section of the structure of semiconductor device for indicating embodiment 10 Face figure.Figure 22, embodiment 10 shown in 23 semiconductor device be to apply embodiment 8 in embodiment 1,2 respectively Semiconductor device.
Specifically, as shown in figure 22, making the protection of the diffusion region 91 identically as embodiment 8 with N-shaped or p-type Element 40 and the p to play a role in circuit portion as protection ring+A part of 24b integration of type diffusion region 24.Accordingly, in addition to Other than the protection element (not shown) for configuring the protection element portion on the outside of circuit portion, in the inside of circuit portion, configuration has diffusion The protection element 40 in area 91, and with the two protection elements.In addition, as shown in figure 23, can expand in circuit portion as guarantor The p that retaining ring plays a role+The width with the integrated part 44b of protection element 40 of type diffusion region 44, makes itself and lateral type n ditch The n of road MOSFET 20+A part overlapping of type source region 22.
Herein, make protection element 40 and p+In type diffusion region 24 with the n of lateral type n-channel MOSFET 20+Type source region 22 Opposite part 24b, 44b integration, but protection element 40 and p can also be made+Other parts 24a, 44a mono- of type diffusion region 24 Body.In addition, the diagram for configuring each section in the composition protection element portion on the outside of circuit portion is omitted in Figure 22,23, but The composition in protection element portion can be identical as embodiment 1,2, can also be identical as embodiment 9.When make configuration in circuit portion When the protection element portion in outside and embodiment 9 have identical composition, configured in the protection element in protection element portion N-shaped or The diffusion region 91 of p-type.
As described above, can be obtained and the identical effect of embodiment 1,8,9 according to embodiment 10.
In above embodiment 1 is equal, in order to adjust the longitudinal type snap-off dioder (snap as protection element 30 Diode rebound) starts electric current, needs to adjust p-The impurity concentration and/or depth of type diffusion region 31.On the other hand, institute as above It states, in order to reduce production cost, is preferably formed simultaneously the p for constituting the protection element 30 in protection element portion-Type diffusion region 31 and structure At the p of the lateral type n-channel MOSFET 20 of circuit portion-Type diffusion region 21.In this case, if preferential lateral type n-channel The characteristic of MOSFET 20 and determine p-Type diffusion region 21 and p-The impurity concentration and/or depth of type diffusion region 31, then sometimes very The rebound of hardly possible adjustment protection element 30 starts electric current.Even if hereinafter, pair be difficult adjust protection element 30 rebound start electric current In the case where be also able to carry out the semiconductor device being effectively protected and be illustrated.
(embodiment 11)
Hereinafter, being illustrated to the structure of the semiconductor device of embodiment 11.Figure 24 is indicate embodiment 11 half The sectional view of the structure of conductor device.The cross section structure in the protection element portion of Figure 24 is the section knot at the cutting line E-E ' of Figure 25 Structure.Figure 25 is the plan view for indicating the plane figure of semiconductor device of embodiment 11.Protection element is only shown in Figure 25 Portion.The semiconductor device of the semiconductor device and embodiment 1 of embodiment 11 the difference lies in that in protection element portion, Also there is the protection element (second protection element) 50 isolated with protection element (the first protection element) 30.
Protection element 50 is by being selectively disposed in n-The p of the superficial layer of type epitaxial layer 2-Type diffusion region (the tenth semiconductor Area) 51 compositions.p-Type diffusion region 51 is with the p-type base area 6 of the longitudinal type MOSFET 10 with output stage portion, the p of circuit portion-Type diffusion The p in area 21 and protection element 30-The isolated mode in type diffusion region 31 configures.In p-The inside of type diffusion region 51 is selectively arranged There is p++Type contact zone (the 12nd semiconductor region) 52 and p+Type diffusion region (the tenth semiconductor area) 53.
p++Type contact zone 52 is connected to GND terminal by wiring layer 35.Constitute p++Between type contact zone 52 and wiring layer 35 Contact portion 55a contact hole 55b be configured with more than one (Figure 25).It is shown in FIG. 25 configured with multiple contact hole 55b State (paints the dotted part of rectangle).p+The depth of type diffusion region 53 can compare p-The depth of type diffusion region 51 is deep.Pass through p+Type Diffusion region 53 and n-Pn-junction between type epitaxial layer 2 is formed with longitudinal type diode D3.
Breakdown voltage (breakdown voltage) ratio of the longitudinal type diode D3 of protection element 50 is by protection element 30 P+Type diffusion region 34 and n-The breakdown potential for the longitudinal type diode D1 that pn-junction between type epitaxial layer 2 generates is forced down.Specifically It says, makes the p from protection element 50-The p of type diffusion region 51+Type diffusion region 53 is to laterally projecting width wa ratio from protection element 30 P-The p of type diffusion region 31+Type diffusion region 34 is small to laterally projecting width wb.By the p for making protection element 50-Type diffusion region P of the 51 protrusion width wa than protection element 30-The protrusion width wb of type diffusion region 31 is small, thus the peripheral part of protection element 50 Electric field alleviation effects become smaller.Hereby it is possible to make the breakdown voltage of longitudinal type diode D3 than longitudinal type diode D1 breakdown potential It presses small.
In the present embodiment, even if preferably protection element 30 is set as being more than thirty years of age of parasitic bipolar element T1 of breakdown voltage Movement.Specifically, making from p+P is arrived in type diffusion region 34++Distance x1 long enough until type contact zone 32.In such protection member In part 30, knock-on since parasitic bipolar element T1 is acted, there is no need to adjust p-The impurity concentration of type diffusion region 31 Or depth and adjust rebound start electric current.
In the present embodiment, even if being formed simultaneously protection element by the injection of same impurity and impurity diffusion process The p in portion-Type diffusion region 31, p-The p of type diffusion region 51 and circuit portion-It the case where each diffusion region of type diffusion region 21, also can be preferential The characteristic of the element formed in circuit portion and set p-The impurity concentration or depth of type diffusion region 21.
Figure 26 is the performance plot for indicating the rebound characteristic of the semiconductor device of embodiment 11.Firstly, referring to current-voltage (I-V) movement when waveform w12 is to 50 individualism of protection element is illustrated.If surge voltage from VCC terminal invade and Increase the voltage of VCC terminal, applies voltage and reach breakdown voltage Vbv11, then longitudinal type diode D3 is in p+Type diffusion region 53 With n-Pn-junction between type epitaxial layer 2 punctures, and electric current (avalanche current) starts to flow.In longitudinal type two due to avalanche current The positive carrier (hole) that pole pipe D3 is generated is via p+Type diffusion region 53, by wiring layer 35 from p++Type contact zone 52 flows into GND terminal.Also, subsequently, as the operating resistance of diode D3 and apply voltage rising, avalanche current increases therewith.
Secondly, referring to Figure 26 I-V waveform w13 to 30 individualism of protection element when movement be illustrated.If unrestrained It gushes voltage to invade from VCC terminal and increase the voltage of VCC terminal, applies voltage and reach breakdown voltage Vbv12, then longitudinal type two Pole pipe D1 is in p+Type diffusion region 34 and n-Pn-junction between type epitaxial layer 2 punctures, and avalanche current starts to flow.Because of snowslide electricity Stream and longitudinal type diode D1 generate positive carrier (hole) via p+Type diffusion region 34 and p-Type diffusion region 31, passes through Wiring layer 35 is from p++Type contact zone 32 flows into GND terminal.The operating resistance of longitudinal type diode D1, passes through p-In type diffusion region 31 Resistive element and become bigger.Once puncturing, then by p-Resistive element in type diffusion region 31 generate in p-Type expands The voltage drop dissipated in area 31 can be immediately more than p-Type diffusion region 31 and n+The forward voltage of pn-junction between type diffusion region 33.Accordingly, p-Type diffusion region 31 and n+Pn-junction between type diffusion region 33 is forward biased, and the one part of current of avalanche current flows to n+Type expands Dissipate 33 side of area.Flow to the n+The electric current of 33 side of type diffusion region becomes base current, by n+Type diffusion region 33, p-Type diffusion region 31 and n- The parasitic bipolar element T1 that type epitaxial layer 2 forms becomes on state, knock-ons.At this point, being applied in protection element 30 Voltage drop to the voltage Vh11 lower than the breakdown voltage Vbv11 of longitudinal type diode D1.
Secondly, being illustrated referring to current-voltage (I-V) waveform w11 to the movement in entire protection element portion.Due to surge Voltage invades from VCC terminal and increase the voltage of VCC terminal, applies voltage and reaches breakdown voltage Vbv11, then two pole of longitudinal type Pipe D3 punctures, and electric current (avalanche current) starts to flow.If passing through the operating resistance of longitudinal type diode D3, apply voltage When reaching breakdown voltage Vbv12, longitudinal type diode D1 is in p+Type diffusion region 34 and n-Pn-junction between type epitaxial layer 2 is hit It wears, avalanche current starts to flow.Once puncturing, then by n+Type diffusion region 33, p-Type diffusion region 31 and n-2 groups of type epitaxial layer At parasitic bipolar element T1 can immediately become on state, knock-on.At this point, being applied under the voltage of protection element 30 Drop to the voltage Vh1 lower than the breakdown voltage Vbv1 of longitudinal type diode D1.
Such embodiment 11 can be applied to embodiment 2~5 to replace being applied to embodiment 1.
As described above, effect identical with Embodiments 1 to 5 can be obtained according to embodiment 11.In addition, according to reality Mode 11 is applied, the rebound due to not needing adjustment protection element (snap-off dioder) starts electric current, so even if preferentially forming In the element of circuit portion characteristic and set p-In the case where the impurity concentration or depth of type diffusion region, it can also be easy to set Count protection element.
More than, in the present invention, the respective embodiments described above are not limited to, it can be into the range of without departing from present subject matter The various changes of row.For example, in above-mentioned each embodiment, as the semiconductor element of output stage, to be provided with trench gate It is illustrated for the situation of the longitudinal type MOSFET of structure, but the semiconductor element as output stage, also can be set The various devices such as the longitudinal type MOSFET of planar gate.In addition, present invention may apply on same semiconductor substrate The semiconductor device for having the various devices (element) for constituting circuit portion and the protection element that these devices are protected from surge.This Outside, even if conductivity type (N-shaped, p-type) is inverted also the same set up by the present invention.
Industrial availability
As described above, the manufacturing method of semiconductor device and semiconductor device of the invention is suitable for same semiconductor-based Has the semiconductor device of the device for constituting circuit portion and the protection element that the device is protected from surge on plate.

Claims (32)

1. a kind of semiconductor device, which is characterized in that have:
First semiconductor region of the second conductive type is selectively arranged at the first interarea of the semiconductor substrate of the first conductive type Superficial layer；
The component structure of semiconductor element is set in first semiconductor region；
Second semiconductor region of the first conductive type, is selectively arranged at the inside of first semiconductor region, and constitutes institute State the component structure of semiconductor element；
The third semiconductor region of the second conductive type runs through first semiconductor region in the depth direction, with described the first half The mode of more than depth of conductor region depth and the component structure of the encirclement semiconductor element is selectively set, and Impurity concentration is higher than the impurity concentration of first semiconductor region；
4th semiconductor region of the second conductive type is selectively arranged at institute in a manner of separating with first semiconductor region State the superficial layer of the first interarea of semiconductor substrate；
5th semiconductor region of the first conductive type is selectively arranged at the inside of the 4th semiconductor region；
6th semiconductor region of the second conductive type runs through the 4th semiconductor region in the depth direction, and with the described 4th The depth more than depth of semiconductor region is selectively set, and impurity concentration is denseer than the impurity of the 4th semiconductor region Degree is high；
First electrode is electrically connected to second semiconductor region, the third semiconductor region, the 4th semiconductor region and institute State the 5th semiconductor region；And
Second electrode is connected to the second interarea of the semiconductor substrate.
2. semiconductor device according to claim 1, which is characterized in that
The semiconductor device is also equipped with the 7th semiconductor region of the second conductive type, the 7th semiconductor region choosing of the second conductive type It is set to selecting property the inside of the 4th semiconductor region, and impurity concentration is higher than the impurity concentration of the 4th semiconductor region,
The first electrode is electrically connected to the 4th semiconductor region via the 7th semiconductor region,
The 5th semiconductor region configuration is between the 6th semiconductor region and the 7th semiconductor region.
3. semiconductor device according to claim 1, which is characterized in that
The semiconductor device is also equipped with the 7th semiconductor region of the second conductive type, the 7th semiconductor region choosing of the second conductive type It is set to selecting property the inside of the 4th semiconductor region, and impurity concentration is higher than the impurity concentration of the 4th semiconductor region,
The first electrode is electrically connected to the 4th semiconductor region via the 7th semiconductor region,
7th semiconductor region is configured in a manner of separating with the 6th semiconductor region,
5th semiconductor region is selectively arranged at the inside of the 6th semiconductor region.
4. semiconductor device according to claim 1, which is characterized in that
The semiconductor device is also equipped with the 7th semiconductor region of the second conductive type, the 7th semiconductor region choosing of the second conductive type It is set to selecting property the inside of the 6th semiconductor region, and impurity concentration is higher than the impurity concentration of the 6th semiconductor region,
The first electrode is electrically connected to the 4th semiconductor region via the 7th semiconductor region,
5th semiconductor region is selectively arranged at the inside of the 6th semiconductor region.
5. semiconductor device according to claim 1, which is characterized in that
The semiconductor device is also equipped with the 7th semiconductor region of the second conductive type, the 7th semiconductor region choosing of the second conductive type It is set to selecting property the inside of the 6th semiconductor region, and impurity concentration is higher than the impurity concentration of the 6th semiconductor region,
The first electrode is electrically connected to the 4th semiconductor region via the 7th semiconductor region,
5th semiconductor region is configured in a manner of separating with the 6th semiconductor region.
6. semiconductor device according to claim 2, which is characterized in that the 5th semiconductor region is to surround the described 7th Mode around semiconductor region configures.
7. semiconductor device according to claim 2, which is characterized in that
5th semiconductor region is configured in the mode surrounded around the 7th semiconductor region,
6th semiconductor region is configured in the mode surrounded around the 5th semiconductor region.
8. semiconductor device according to claim 2, which is characterized in that the 6th semiconductor region is to surround the described 7th Mode around semiconductor region configures.
9. semiconductor device according to claim 2, which is characterized in that the 6th semiconductor region is to surround the described 5th Mode around semiconductor region configures.
10. semiconductor device according to claim 1, which is characterized in that the 6th semiconductor region has and described the The identical impurity concentration of three semiconductor regions and depth.
11. semiconductor device according to claim 1, which is characterized in that the 4th semiconductor region has and described the The identical impurity concentration in semiconductor area and depth.
12. semiconductor device according to claim 1, which is characterized in that so that by the 5th semiconductor region, described Four semiconductor regions and the semiconductor substrate composition parasitic bipolar element or by the 5th semiconductor region, the described 6th The voltage that the parasitic bipolar element of semiconductor region and semiconductor substrate composition starts rebound is lower than is led by described the second half The parasitic bipolar element in body area, first semiconductor region and semiconductor substrate composition starts the mode of the voltage of rebound Setting is from a distance from the 6th semiconductor region is until the 4th semiconductor region is with the contact portion of the first electrode.
13. semiconductor device according to claim 2, which is characterized in that so that by the 5th semiconductor region, described Four semiconductor regions and the semiconductor substrate composition parasitic bipolar element or by the 5th semiconductor region, the described 6th The voltage that the parasitic bipolar element of semiconductor region and semiconductor substrate composition starts rebound is lower than is led by described the second half The parasitic bipolar element in body area, first semiconductor region and semiconductor substrate composition starts the mode of the voltage of rebound Set the distance until the 6th semiconductor region to the 7th semiconductor region.
14. semiconductor device according to claim 2, which is characterized in that so that by the 5th semiconductor region, described The voltage that the parasitic bipolar element of four semiconductor regions and semiconductor substrate composition starts rebound is lower than by described the second half The parasitic bipolar element of conductor region, first semiconductor region and semiconductor substrate composition starts the side of the voltage of rebound Formula sets the distance until the 6th semiconductor region to the 5th semiconductor region.
15. semiconductor device according to claim 1, which is characterized in that so that by the 5th semiconductor region, described Four semiconductor regions and the semiconductor substrate composition parasitic bipolar element or by the 5th semiconductor region, the described 6th The voltage that the parasitic bipolar element of semiconductor region and semiconductor substrate composition starts rebound is lower than is led by described the second half The parasitic bipolar element in body area, first semiconductor region and semiconductor substrate composition starts the mode of the voltage of rebound Set the impurity concentration of the 4th semiconductor region.
16. semiconductor device according to claim 1, which is characterized in that the component structure of the semiconductor element includes:
Second semiconductor region；
8th semiconductor region of the first conductive type is selectively arranged at institute in a manner of separating with second semiconductor region State the inside of the first semiconductor region；
Grid, across gate insulating film be arranged in first semiconductor region be sandwiched in second semiconductor region with it is described On the surface of part between 8th semiconductor region.
17. semiconductor device according to claim 1, which is characterized in that the semiconductor device is provided with same First semiconductor region and the 4th semiconductor region that process is formed.
18. semiconductor device according to claim 1, which is characterized in that the semiconductor device is provided with same The third semiconductor region and the 6th semiconductor region that process is formed.
19. semiconductor device according to claim 1, which is characterized in that the semiconductor device is provided with same Second semiconductor region and the 5th semiconductor region that process is formed.
20. semiconductor device described according to claim 1~any one of 19, which is characterized in that the semiconductor device exists It is also equipped between 4th semiconductor region and the 5th semiconductor region and is arranged in a manner of covering the 5th semiconductor region The 9th semiconductor region.
21. semiconductor device according to claim 20, which is characterized in that the first conductive type of the 9th semiconductor region Impurity concentration is higher than the first conductive type impurity concentration of the 4th semiconductor region.
22. semiconductor device according to claim 20, which is characterized in that the second conductive type of the 9th semiconductor region Impurity concentration is higher than the second conductive type impurity concentration of the 4th semiconductor region.
23. semiconductor device according to claim 20, which is characterized in that the 4th semiconductor region is the third half A part of conductor region.
24. semiconductor device according to claim 1, which is characterized in that the semiconductor device further include:
Tenth semiconductor region of the second conductive type, with the side separated with first semiconductor region and the 4th semiconductor region Formula is selectively arranged at the superficial layer of the first interarea of the semiconductor substrate；
The tenth semiconductor region is run through in tenth semiconductor area of the second conductive type in the depth direction, and with described The depth more than depth of ten semiconductor regions is selectively set；And
12nd semiconductor region of the second conductive type is selectively arranged at the superficial layer in the tenth semiconductor area, and Impurity concentration is higher than the impurity concentration in the tenth semiconductor area,
Wherein, the breakdown voltage ratio for the first diode being made of the semiconductor substrate and the third semiconductor region is by described The breakdown voltage for the second diode that semiconductor substrate and the tenth semiconductor area are constituted is high.
25. semiconductor device according to claim 24, which is characterized in that in first interarea of the semiconductor substrate Surface, the distance between the semiconductor substrate and the 6th semiconductor region are than the semiconductor substrate and the tenth half The distance between conductor region is big.
26. a kind of semiconductor device, which is characterized in that have:
First semiconductor region of the second conductive type is selectively arranged at the first interarea of the semiconductor substrate of the first conductive type Superficial layer；
The component structure of semiconductor element is set in first semiconductor region；
Second semiconductor region of the first conductive type, is selectively arranged at the inside of first semiconductor region, and constitutes institute State the component structure of semiconductor element；
The third semiconductor region of the second conductive type is selectively set in a manner of surrounding the component structure of the semiconductor element It is placed in the inside of first semiconductor region, and impurity concentration is higher than the impurity concentration of first semiconductor region；
4th semiconductor region of the second conductive type is selectively arranged at institute in a manner of separating with first semiconductor region State the superficial layer of the first interarea of semiconductor substrate；
5th semiconductor region of the first conductive type is selectively arranged at the inside of the 4th semiconductor region；
6th semiconductor region of the second conductive type is selectively disposed in the inside of the 4th semiconductor region, and impurity is dense It spends higher than the impurity concentration of the 4th semiconductor region；
First electrode is electrically connected to second semiconductor region, the third semiconductor region, the 4th semiconductor region and institute State the 5th semiconductor region；And
Second electrode is connected to the second interarea of the semiconductor substrate.
27. a kind of semiconductor device, which is characterized in that have:
First semiconductor region of the second conductive type is selectively arranged at the first interarea of the semiconductor substrate of the first conductive type Superficial layer；
The component structure of semiconductor element is set in first semiconductor region；
Second semiconductor region of the first conductive type, is selectively arranged at the inside of first semiconductor region, and constitutes institute State the component structure of semiconductor element；
The third semiconductor region of the second conductive type runs through first semiconductor region in the depth direction, with described the first half The mode of more than depth of conductor region depth and the component structure of the encirclement semiconductor element is selectively set, and Impurity concentration is higher than the impurity concentration of first semiconductor region；
4th semiconductor region of the second conductive type is selectively arranged at institute in a manner of separating with first semiconductor region State the superficial layer of the first interarea of semiconductor substrate；
5th semiconductor region of the first conductive type is selectively arranged at the inside of the 4th semiconductor region；
First electrode is electrically connected to second semiconductor region, the third semiconductor region, the 4th semiconductor region and institute State the 5th semiconductor region；And
Second electrode is connected to the second interarea of the semiconductor substrate.
28. semiconductor device according to claim 27, which is characterized in that
The semiconductor device is also equipped with the 6th semiconductor region of the second conductive type, the 6th semiconductor region choosing of the second conductive type It is set to selecting property the inside of the 4th semiconductor region, and impurity concentration is higher than the impurity concentration of the 4th semiconductor region,
The first electrode is electrically connected to the 4th semiconductor region via the 6th semiconductor region,
5th semiconductor region is configured in the mode surrounded around the 6th semiconductor region.
29. semiconductor device according to claim 27, which is characterized in that so that by the 5th semiconductor region, described The voltage that the parasitic bipolar element of 4th semiconductor region and semiconductor substrate composition starts rebound is lower than by described second The parasitic bipolar element of semiconductor region, first semiconductor region and semiconductor substrate composition starts the voltage of rebound Mode set from the corner part of the 4th semiconductor region to the 4th semiconductor region with the contact portion of the first electrode as Distance only.
30. semiconductor device according to claim 28, which is characterized in that so that by the 5th semiconductor region, described The voltage that the parasitic bipolar element of 4th semiconductor region and semiconductor substrate composition starts rebound is lower than by described second The parasitic bipolar element of semiconductor region, first semiconductor region and semiconductor substrate composition starts the voltage of rebound Mode sets the distance until the corner part to the 6th semiconductor region of the 4th semiconductor region.
31. semiconductor device according to claim 27, which is characterized in that the semiconductor device is provided with same The third semiconductor region and the 4th semiconductor region that process is formed.
32. a kind of manufacturing method of semiconductor device, which is characterized in that it is the manufacturing method of following semiconductor device, described half Conductor device includes:
First semiconductor region of the second conductive type is selectively arranged at the first interarea of the semiconductor substrate of the first conductive type Superficial layer；
The component structure of semiconductor element is set in first semiconductor region；
Second semiconductor region of the first conductive type, is selectively arranged at the inside of first semiconductor region, and constitutes institute State the component structure of semiconductor element；
The third semiconductor region of the second conductive type runs through first semiconductor region, described first in the depth direction The mode of more than depth of semiconductor region depth and the component structure of the encirclement semiconductor element is selectively set, and And impurity concentration is higher than the impurity concentration of first semiconductor region；
4th semiconductor region of the second conductive type is selectively arranged at institute in a manner of separating with first semiconductor region State the superficial layer of the first interarea of semiconductor substrate；
5th semiconductor region of the first conductive type is selectively arranged at the inside of the 4th semiconductor region；
6th semiconductor region of the second conductive type runs through the 4th semiconductor region, in the depth direction with the described 4th half The depth more than depth of conductor region is selectively set, and impurity concentration is than the impurity concentration of the 4th semiconductor region It is high；
First electrode is electrically connected to second semiconductor region, the third semiconductor region, the 4th semiconductor region and institute State the 5th semiconductor region；And
Second electrode is connected to the second interarea of the semiconductor substrate,
The manufacturing method of the semiconductor device includes:
By the injection of same impurity and impurity diffusion processing, by first semiconductor region and described the in a manner of being separated from each other The process that four semiconductor regions are selectively formed at the superficial layer of the first interarea of the semiconductor substrate；
By the injection of same impurity and impurity diffusion processing, described the is formed selectively in the inside of first semiconductor region Two semiconductor regions, and the process for being formed selectively the 5th semiconductor region in the inside of the 4th semiconductor region；With And
By the injection of same impurity and impurity diffusion processing, it is optionally formed on depth direction through first semiconductor The third semiconductor region in area, and be optionally formed on depth direction through described the of the 4th semiconductor region The process of six semiconductor regions.
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