KR20100052293A - A device for preventing circuit from discharge - Google Patents

A device for preventing circuit from discharge Download PDF

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Publication number
KR20100052293A
KR20100052293A KR1020080111248A KR20080111248A KR20100052293A KR 20100052293 A KR20100052293 A KR 20100052293A KR 1020080111248 A KR1020080111248 A KR 1020080111248A KR 20080111248 A KR20080111248 A KR 20080111248A KR 20100052293 A KR20100052293 A KR 20100052293A
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KR
South Korea
Prior art keywords
input
well
region
contact region
contact
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Application number
KR1020080111248A
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Korean (ko)
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KR101050456B1 (en
Inventor
최낙헌
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주식회사 하이닉스반도체
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Priority to KR20080111248A priority Critical patent/KR101050456B1/en
Publication of KR20100052293A publication Critical patent/KR20100052293A/en
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Publication of KR101050456B1 publication Critical patent/KR101050456B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: A device for protecting a circuit from electrostatic discharge is provided to improve electrostatic discharge efficiency by minimizing dopants, which are connected to an input-output region, and a well region which are contact to the dopants. CONSTITUTION: A first well(210) and a second well(220) are formed. A guard ring(230) is formed by implanting a first dopant into the first well. A first contact region(250) is formed by implanting a second dopant into a overlapped region of the first well and the second well. A second contact region(270) is formed by implanting the second dopant into a region which is adjacent to the first contact region. A first input-output contact(240) is formed by implanting the second dopant into the inside of a first input-output contact region. A second input-output contact(260) is formed by implanting the first dopant into the inside of a second input-output contact region.

Description

 Static protection device {A DEVICE FOR PREVENTING CIRCUIT FROM DISCHARGE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic protection device, and more particularly, to an electrostatic protection device for minimizing input capacitance of a high speed semiconductor by minimizing a contact area between an area connected to an input / output terminal and a well to increase electrostatic discharge efficiency.

In general, when a semiconductor integrated circuit is in contact with a human body or a machine, the static electricity charged in the human body or the machine is discharged into the semiconductor, and thus the semiconductor internal circuit may be greatly damaged.

The semiconductor integrated circuit configures an electrostatic protection circuit between the input / output pad and the semiconductor internal circuit to protect the semiconductor internal circuit from such damage.

1 illustrates a layout of a static electricity protection circuit provided in a conventional input / output terminal.

Referring to FIG. 1, the conventional static electricity protection circuit 100 includes an N-type well 120 formed by being surrounded by a P-type well 110, and the P-type well 110 includes N + impurity zero having a bar shape. An inverse 130 is formed, and a P-type impurity region 140 having a bar shape is formed in the N-type well 120.

At this time, a guard ring 150 formed by P + impurities is formed at the periphery of the P-type well 110.

Meanwhile, a bar-shaped N + impurity region 160 is formed at a portion where the P-type well 110 and the N-type well 120 are joined, while the N + impurity region 170 is a P-type spaced apart from the N + impurity region 160. Formed on the well 110.

The gate pattern 180 is formed between the N + impurity region 160 and the N + impurity region 170.

  In the conventional static electricity protection circuit 100 as shown in FIG. 1, the input / output terminal I / O is connected to the N + impurity region 130 and the P + impurity region 140, and the ground voltage pad VSS is connected to the gate 180. It is connected to the N + impurity region 170 and the guard ring 150.

By the above configuration, the static electricity protection circuit of FIG. 1 serves to discharge static electricity applied from the input / output terminal I / O.

However, the conventional static electricity protection circuit has a bar shape that makes electrical contact with the input / output pad (I / O), thereby increasing the junction area between the N type well and the P type well with each P + impurity region and the N + impurity region.

Therefore, the capacitance component at the input and output terminals is increased due to the large bonding area, which leads to a problem of lowering the electrostatic discharge efficiency. As a result, the junction between each well and an impurity in a high-speed semiconductor device requiring a device having a higher electrostatic discharge efficiency compared to the capacitance. There was a need for a technique that could reduce area.

The present invention provides an electrostatic protection device in which the electrostatic discharge efficiency of the capacitance is greatly increased by reducing the contact area between impurities connected to the input and output terminals and each well bonded to the input and output terminals.

An electrostatic protection device according to the present invention includes a first well, a second well formed inside the first well, and a first input / output contact region in which a plurality of separated first wells are exposed, and on the first well. The first well and the guard ring having a second ring having a second ring formed therein and a plurality of second wells exposed therein. A first contact region formed by implanting a second impurity into a region over a second well, a second contact region formed by implanting the second impurity into a region adjacent to the first contact region on the first well, A gate pattern formed on a space in which the first contact region and the second contact region are spaced apart; a first input / output contact formed by implanting the second impurities into a plurality of the first input / output contact regions; And a second input / output contact formed by injecting the first impurities into a plurality of second input / output contact regions, wherein the first input / output contact and the second input / output contact are electrically connected to an input / output pad. .

 Preferably, the first well is characterized in that the P-type.

In addition, the second well is characterized in that the N-type.

In addition, the guard ring is preferably formed of a P-type impurity, characterized in that the ground voltage is connected.

In addition, the first contact region is preferably formed of an N-type impurity, characterized in that the power supply voltage is connected.

In addition, the second contact region is preferably formed of an N-type impurity, characterized in that the power supply voltage is connected.

Preferably, the first input / output contact is formed of an N-type impurity.

In addition, preferably, the second input / output contact is formed of a P-type impurity.

In addition, preferably, a resistance is connected between the gate and the second contact region, and the first contact region is connected with the gate and the resistor interposed between the capacitor.

According to the present invention, in the formation of the electrostatic discharge element at the input / output terminal, by forming a small number of impurities connected to the input / output terminal, the electrostatic discharge efficiency is greatly increased compared to the capacitance while reducing the contact area of each well bonded thereto. There is an effect that can increase the stability and reliability of the semiconductor.

In addition, the present invention is composed of a small number of impurities connected to the input and output terminals, the current is proportional to the parameter (PERIMETER) due to the characteristic that there is no loss in the amount of current compared to the conventional, so conducting a large amount of electrostatic current even in a small junction area It can be effected.

The electrostatic protection device according to the present invention discloses a configuration in which P-type or N-type impurities are formed to have a small contact area with respect to N-type wells and P-type wells.

2 and 3 to describe in detail, the electrostatic protection device 200 according to the present invention first. The first well 210 and the second well 220 formed inside the first well 210 are formed, the first well 210 is formed in a P type, and the second well 220 is an N type. Is formed.

The guard ring 230 is formed on the first well 210 to form a ring shape along an edge of the first well 210.

The guard ring 230 is formed by implanting a first impurity, and is formed to have a first input / output contact region 231 in which a plurality of separated first wells 210 are exposed.

A second impurity is implanted into the first input / output contact region 231 to form a first input / output contact 240.

In this case, the guard ring 230 is formed of P-type impurities, and the first input / output contact 240 is formed of N-type impurities.

A ground voltage is connected to the guard ring 230, and an input / output terminal (I / O) is connected to the first input / output contact 240 so as to be connected to an input / output pad (not shown), and the first input / output contact 240 and the guard ring. Region A, including 230, acts as a diode.

Meanwhile, the first contact region 250 is formed in the region spanning the first well 210 and the second well 220.

The first contact region 250 is formed by implanting second impurities, and has a second input / output contact region 251 in which a plurality of separated second wells 220 are exposed.

First impurities are implanted into the second input / output contact region 251 to form a second input / output contact 260.

The first contact region 250 is formed of N-type impurities, and the second input / output contact 260 is formed of P-type impurities.

A power supply voltage is connected to the first contact region 250, and the second input / output contact 260 is connected to an input / output pad (not shown) by connecting an input / output terminal I / O.

Meanwhile, a second contact region 270 formed by implanting a second impurity is formed in a region adjacent to the first contact region 250 on the first well 210.

The second contact region 270 is formed of N-type impurities and is connected to the ground voltage.

The region B including the second input / output contact 260 of the first contact region 250 acts as a diode, and the first contact region 250 includes the gate 280 from the first contact region 250 including the gate 280 to the second contact region 270. The leading region C acts as an NMOS transistor.

Meanwhile, referring to FIG. 4, a resistor 291 is connected between the gate 280 and the second contact region 270, and the first contact region 250 has a capacitor 292 interposed therebetween, and the gate 280 is interposed therebetween. And another embodiment in connection with the resistor 291 is possible.

According to another embodiment of the present invention, the static electricity applied to the input / output terminal is discharged at a low voltage, thereby further increasing the discharge efficiency.

As described above, the configuration of the electrostatic protection device according to the preferred embodiment of the present invention is illustrated in the drawings and described as described above, but this is merely described, for example, and various designs without departing from the technical spirit of the present invention. And it will be readily apparent to those skilled in the art that modifications and variations are possible within the scope of the invention.

1 is a layout of a conventional static electricity protection device.

2 is a layout of the electrostatic protection device according to the present invention.

3 is a sectional view taken along line D-D 'of the electrostatic protection device according to the present invention;

4 is a sectional view taken along the line D-D 'according to another embodiment of the present invention.

Claims (9)

First well; A second well formed inside the first well; A guard ring having a first input / output contact region in which a plurality of separated first wells are exposed, and having a first impurity implanted into the ring to form a ring shape along an edge of the first well; A first contact region having a second input / output contact region in which a plurality of separated second wells are exposed, and having a second impurity injected into a region extending between the first well and the second well; A second contact region formed by implanting the second impurity into a region adjacent to the first contact region on the first well; A gate pattern formed on a space in which the first contact region and the second contact region are spaced apart from each other; A first input / output contact formed by injecting the second impurities into a plurality of the first input / output contact regions; And A second input / output contact formed by injecting the first impurities into a plurality of second input / output contact regions; And the first input / output contact and the second input / output contact are electrically connected to an input / output pad. The method of claim 1, The first well is a static electricity protection device, characterized in that the P-type. The method of claim 2, And the second well is N-type. The method of claim 3, wherein The guard ring is formed of a P-type impurity, characterized in that the ground voltage is connected to the electrostatic protection device. The method of claim 4, wherein The first contact region is formed of N-type impurities, characterized in that the power supply voltage is connected. The method of claim 5. The second contact region is formed of an N-type impurities, characterized in that the ground voltage is connected to the electrostatic protection device. The method of claim 6, And the first input / output contact is formed of an N-type impurity. The method of claim 7, wherein And the second input / output contact is formed of a P-type impurity. The method according to any one of claims 1 to 9, A resistor is connected between the gate and the second contact region, and the first contact region is connected with the gate and the resistor interposed between the capacitor and the capacitor.
KR20080111248A 2008-11-10 2008-11-10 Static electricity protection device KR101050456B1 (en)

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Application Number Priority Date Filing Date Title
KR20080111248A KR101050456B1 (en) 2008-11-10 2008-11-10 Static electricity protection device

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Application Number Priority Date Filing Date Title
KR20080111248A KR101050456B1 (en) 2008-11-10 2008-11-10 Static electricity protection device

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KR20100052293A true KR20100052293A (en) 2010-05-19
KR101050456B1 KR101050456B1 (en) 2011-07-19

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Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2770341B1 (en) * 1997-10-24 2000-01-14 Sgs Thomson Microelectronics PROTECTION AGAINST ELECTROSTATIC DISCHARGES AT LOW THRESHOLD LEVEL
KR101043737B1 (en) * 2007-02-15 2011-06-24 주식회사 하이닉스반도체 Electrostatic discharge protection element

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