CN106788431B - Successive approximation register type analog-to-digital converter - Google Patents
Successive approximation register type analog-to-digital converter Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
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Abstract
The invention relates to an analog-to-digital conversion technology, in particular to a successive approximation register type analog-to-digital converter, which comprises a sampling comparator, a digital-to-analog converter, a controller, a register, a memory, a processor and a reference circuit, wherein the comparator compares input analog quantity with each reference analog quantity in sequence and outputs a group of digital signals reflecting comparison results to the memory; the controller receives the analysis result from the processor, and changes the reference analog quantity or the control signal of the controller according to the analysis result, so that the successive approximation register type analog-to-digital converter changes the search strategy, reduces the approximation times, and achieves the purposes of reducing power consumption, accelerating speed and increasing resolution.
Description
Technical Field
The present invention relates to analog-to-digital conversion technologies, and in particular, to a successive approximation register analog-to-digital converter.
Background
ADC (Analog-to-Digital Converter) is an important tool for computer-to-human communication with the real world, and can convert Analog signals widely existing in the real world into Digital signals that can be recognized by a computer. There are many types of ADCs on the market today, including SAR ADCs (Successive Approximation Register ADCs), pipelined ADCs, sigma-delta ADCs, FLASH ADCs, etc. Among them, the SAR ADC is one of the most widely used ones, and has advantages of low power consumption and low cost.
However, the SAR ADC has some disadvantages, such as that it needs to be approached from the most significant bit to the least significant bit every time a/D conversion is performed, which greatly slows down the speed of the SAR ADC; for example, each time the SAR ADC is approached, the capacitor needs to be charged and discharged, so that the power consumption of the SAR ADC is greatly increased; and because the required capacitance of the DAC increases exponentially for every 1 bit of resolution improvement, the improvement of the resolution is also limited.
Disclosure of Invention
In view of the above problem, the present invention provides a successive approximation register analog-to-digital converter, including:
the comparator comprises a positive phase input end, a negative phase input end and a comparison output end;
the positive phase input end is used for receiving an input analog quantity;
the digital-to-analog converter comprises an input pin, a reference power supply pin and an output pin; the analog-to-digital converter outputs a plurality of reference analog quantities with different sizes through the output pin;
the inverting input end of the comparator is connected with the digital-to-analog converter;
the comparator receives each reference analog quantity in sequence through the inverting input end, compares the input analog quantity with each reference analog quantity in sequence, and outputs a digital signal reflecting a comparison result through the comparison output end;
the controller comprises a first control input end, a second control input end, a control output end and a signal output end;
the first control input of the controller is connected with the comparison output of the comparator to receive the digital signal;
the first control output end of the controller is connected with the input pin of the digital-to-analog converter so as to output a first control signal to the digital-to-analog converter, wherein the first control signal is used for controlling the reference analog quantity output by the digital-to-analog converter;
the signal output end of the controller is used for outputting the digital signal;
the register is connected with the signal output end of the controller and used for receiving and temporarily storing the digital signal output by the controller;
the memory is connected with the register so as to extract the temporarily stored digital signals from the register and store the digital signals;
the processor comprises a signal input port, a first control output port and a second control output port;
the signal input port of the processor is connected with the memory so as to receive and analyze the digital signal in a preset time period and output a corresponding analysis result;
the first control output port of the processor is connected with the second control input end of the controller so as to output the analysis result corresponding to the time period to the controller, and therefore the self-learning updating process of the processor on the analysis result is achieved;
the reference circuit is connected with the second control output port of the processor to receive a second control signal corresponding to the time period;
the reference circuit is also connected with the reference power supply pin of the digital-to-analog converter so as to output a reference voltage to the digital-to-analog converter according to the second control signal;
and the digital-to-analog converter performs weight calculation on the received first control signal and the reference voltage to form the reference analog quantity.
The successive approximation register analog-to-digital converter has the advantages that the controller has the functions of logic conversion and digital output.
In the successive approximation register analog-to-digital converter, the controller changes the control mode according to the analysis result.
In the successive approximation register analog-to-digital converter, the control mode includes: the potential of a specific bit number is fixed, and the number of conversion bits is changed.
In the successive approximation register analog-to-digital converter, when each bit of the digital signal obtained through analysis is 1 or 0, the controller restores the value range of the reference voltage output by the reference circuit through the second control signal.
In the successive approximation register analog-to-digital converter, the reference circuit is a power circuit whose power supply is programmable.
In the successive approximation register analog-to-digital converter, the memory includes a nonvolatile volatile memory.
In the successive approximation register analog-to-digital converter, the memory is manufactured by adopting a back-end nonvolatile volatile memory production process compatible with a CMOS (complementary metal oxide semiconductor) process.
In the successive approximation register analog-to-digital converter, the memory is made of a finfet transistor.
Has the advantages that: the invention enables the power consumption of the successive approximation register type analog-to-digital converter to be capable of learning autonomously and storing the autonomously learned information in the storage module, so that the successive approximation register type analog-to-digital converter changes the search strategy according to the information in the storage module, reduces the approximation times, and achieves the purposes of reducing the power consumption, accelerating the speed or increasing the resolution.
Drawings
FIG. 1 is a schematic diagram of a successive approximation register analog-to-digital converter according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a successive approximation register ADC according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a successive approximation register analog-to-digital converter according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a cell structure of a memory according to an embodiment of the present invention;
FIG. 5 is a flowchart illustrating the operation of a successive approximation register ADC according to an embodiment of the present invention;
FIG. 6 is a flowchart illustrating the operation of a successive approximation register ADC according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a successive approximation register analog-to-digital converter according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a part of the structure of the learned successive approximation register type analog-to-digital converter in the embodiment shown in FIG. 7;
FIG. 9 is a schematic diagram of a part of the structure of the learned successive approximation register type analog-to-digital converter in the embodiment shown in FIG. 7;
FIG. 10 is a flowchart illustrating the operation of a successive approximation register analog-to-digital converter according to an embodiment of the present invention;
FIG. 11 is a block diagram of a successive approximation register ADC according to an embodiment of the present invention;
fig. 12 is a schematic diagram of a part of the structure of the learned successive approximation register analog-to-digital converter according to an embodiment of the present invention.
Detailed Description
The invention is further illustrated with reference to the following figures and examples.
In a preferred embodiment, as shown in fig. 3, a successive approximation register analog-to-digital converter 300 is provided, which may include:
a comparator 310 including a positive input terminal, a negative input terminal, and a comparison output terminal;
the positive phase input end is used for receiving an input analog quantity;
a digital-to-analog converter 370 including an input pin, a reference power pin, and an output pin; the analog-to-digital converter 370 outputs a plurality of reference analog quantities with different sizes through an output pin;
the inverting input of the comparator 310 is connected to the digital-to-analog converter 370;
the comparator 310 receives each reference analog quantity through the inverting input terminal in sequence, compares the input analog quantity with each reference analog quantity in sequence, and outputs a digital signal reflecting the comparison result through the comparison output terminal;
a controller 320 including a first control input, a second control input, a control output and a signal output;
a first control input of the controller 320 is connected to the comparison output of the comparator 310 to receive the digital signal;
the first control output end of the controller 320 is connected to the input pin of the digital-to-analog converter 370 to output a first control signal to the digital-to-analog converter 370, where the first control signal is used to control the magnitude of the reference analog quantity output by the digital-to-analog converter 370;
a signal output terminal of the controller 320 is used for outputting a digital signal;
a register 330, connected to the signal output terminal of the controller 320, for receiving and temporarily storing the digital signal output by the controller 320;
a memory 340 connected to the register 330 for extracting and storing the temporarily stored digital signal from the register 330;
a processor 350 including a signal input, a first control output and a second control output;
the signal input port of the processor 350 is connected to the memory 340 to receive and analyze the digital signal within a predetermined time period, and output a corresponding analysis result;
a first control output port of the processor 350 is connected with a second control input port of the controller 320, so as to output the analysis result corresponding to the time period to the controller 320, and realize a self-learning updating process of the processor 350 on the analysis result;
the reference circuit 360 is connected to the second control output port of the processor 350 to receive a second control signal corresponding to the time period;
the reference circuit 360 is further connected to a reference power pin of the digital-to-analog converter 370 to output a reference voltage to the digital-to-analog converter 370 according to the second control signal;
the digital-to-analog converter 370 performs a weight calculation on the received first control signal and the reference voltage to form a reference analog quantity.
An advantage of this embodiment over a normal SRA ADC is that the reference circuit is intelligently adjustable. Therefore, the conversion precision of the analog signal to the digital signal is improved.
Fig. 1 and fig. 2 are schematic diagrams of two signal trends in an embodiment of the present invention, respectively; as shown in fig. 3, the processor 350 may output control signals to the reference circuit 360 and the controller 320 at the same time, thereby achieving intelligent adjustment of the reference power and the comparison bit number. This embodiment is a combination of figures 1 and 2. The connection relationship is therefore a superposition of fig. 1 and 2.
In a preferred embodiment, the controller 320 has the functions of logic conversion and digital output.
In the above embodiment, the controller 320 preferably changes the control mode according to the analysis result.
In the above embodiment, preferably, the control mode includes: the potential of a specific bit number is fixed, and the number of conversion bits is changed.
In the above embodiment, preferably, when each bit of the digital signal obtained by the analysis is 1 or 0, the controller 320 restores the value range of the reference voltage output by the reference circuit through the second control signal.
In a preferred embodiment, the reference circuit 360 is a power circuit in which the power supply is programmable.
In a preferred embodiment, memory 340 comprises a non-volatile memory.
In the above embodiment, the memory 340 is preferably manufactured by a back-end non-volatile memory manufacturing process compatible with CMOS processes.
In the above embodiments, the memory is preferably made of a finfet transistor.
As shown in fig. 4, the Memory module may be a nonvolatile Memory, such as a conventional ROM (Read Only Memory), an EEPROM (Electrically Erasable Programmable Read-Only Memory), a FLASH Memory, or an emerging FRAM (ferroelectric Random Access Memory), an MRAM (Magnetic Random Access Memory), a PCRAM (Phase Change Memory), and so on. More preferably, considering that an additional mask is required to manufacture the nonvolatile memory in the conventional CMOS process, which may increase process difficulty and cost, the nonvolatile memory of the present invention may use a FIND RRAM (Fin Field Effect Transistor, FinFET Dielectric resistance random access memory) manufactured based on a FinFET CMOS (Fin Field-Effect Transistor, Complementary Metal-Oxide-Semiconductor) process, the cell structure is shown in FIG. 4, where BLm and WLn are bit line and word line of RRAM (Resistive Random Access Memory) cell respectively, the method is used for selecting a nonvolatile memory storage unit which is desired to be operated, and SLn is a line selection used for reading, writing (including setting 1 and clearing 0) and the like on the selected nonvolatile memory storage unit. HfO2 (hafnium oxide) is shown to be both the gate insulator layer of a conventional N-type FinFET transistor and a resistive storage node. Thus, the non-volatile memory is compatible with normal FinFET CMOS processes without adding additional masks. This greatly reduces the manufacturing difficulty and thus the cost.
The successive approximation register analog-to-digital converter workflow can be as shown in fig. 5, and is as follows: 1) the analog input voltage Vinput is sampled and held by a sample/hold circuit. To implement a binary search algorithm, the N-bit register is first set at the middle scale (i.e., 100.. 00 with the most significant MSB set to 1). Thus, the DAC output (VDAC) is set to VREF/2, which is the reference voltage provided to the ADC. 2) The comparison determines whether Vinput is less than or greater than VDAC. If Vinput is greater than VDAC, the comparator outputs a logic high level or 1, and the MSB of the N-bit register remains 1; conversely, if Vinput is less than VDAC, the comparator outputs a logic low level or 0, the MSB of the N-bit register is cleared to 0. 3) The SAR control logic moves to the next bit and sets that bit high for the next comparison to determine the logic level of the current bit. 4) This process is repeated until the least significant bit LSB. After the above operation is completed, the conversion is completed, the N-bit conversion result is stored in the register, and the converted digital signal is output. The input analog quantity can be converted into an N-bit digital quantity by indicating the value of the highest register by Dn, wherein Vinput is Dn Vref/2+ Dn-1 Vref/22+ Dn-2 Vref/23+ … + D1 Vref/2N. By this, the SAR ADC completes one conversion from analog to digital. Then, the CPU (Central Processing Unit) or the MCU (Microcontroller Unit) counts the digital quantities obtained by the conversion of the SAR ADC over a period of time, analyzes the digital quantities by machine learning, such as an artificial neural network or a support vector machine, etc., summarizes the rules, and stores the rules in the nonvolatile memory. When the SAR ADC works again next time, the SAR control logic changes the search strategy according to the information stored in the nonvolatile memory, reduces the search range to perform analog-to-digital conversion, and continues the next conversion if the conversion is successful; if the conversion fails, the complete conversion is performed again.
Two specific applications of the present invention are described in detail below.
There is an instrument for measuring outdoor temperature, and an 8-bit self-learning SAR ADC converts the analog signal of the input temperature into a digital signal, and the structural diagram is shown in FIG. 7. The working flow of the SAR ADC is shown in fig. 6, and specifically as follows: 1) the SAR ADC receives an analog signal, samples and holds it, and then performs normal analog-to-digital conversion (as shown in fig. 6) to obtain digital values from the 1 st bit (MSB) to the 8 th bit (LSB), and outputs them to the CPU. 2) And (3) repeating the step (1) by the SAR ADC within a period of time, and obtaining the digital quantity output by the SAR ADC within the period of time by the CPU. 3) The CPU analyzes and summarizes the rules of the digital quantity and the time obtained in the period of time through machine learning and stores the rules into the nonvolatile memory. For example, in the early morning of winter, the CPU concludes that the temperature during this period is generally low, i.e., the first 6 bits of the digital quantity are generally all 0, the SAR ADC may fix the 1 st to 6 th bits to 0, approach only the 7 th and 8 th bits, and store this information in the nonvolatile memory. For example, at night in summer, the CPU concludes that the temperature is slightly higher but not at noon in summer, so the SAR ADC can fix the 1 st and 2 nd bits to 1, set the 6 th to 8 th bits to 0, and only approach the 3 rd, 4 th, and 5 th bits, and store this information in the nonvolatile memory. In this case, the resolution equivalent to the SAR ADC is reduced, but when the accuracy requirement for the resulting temperature is not high, this can greatly reduce the power consumption of the SAR ADC. 4) The SAR logic changes its search strategy by information in the non-volatile memory to approach only a few of the 8 bits in a particular time period, as shown in fig. 8 and 9. 5) Judging whether the conversion is correct, specifically judging whether the approached bits are all 1 or all 0, if all 0 or all 1, indicating that the obtained digital quantity is in a state to be jumped, and having a larger difference with an actual value, and completely approaching from the 1 st bit to the 8 th bit by the SAR ADC again; if the conversion is correct, namely the approached bits are not all 1 or all 0, the conversion is finished, and the obtained digital quantity is output to a CPU to wait for the next conversion. Thus, in most cases, the SAR ADC operates at a faster rate with lower power consumption.
There is a thermostatic chamber, the structure of which is schematically shown in fig. 11, and an 8-bit self-learning SAR ADC converts the analog signal of the input temperature into a digital signal. The working flow of the SAR ADC is shown in fig. 10, and specifically as follows: 1) the SAR ADC receives an analog signal, samples and holds it, and then performs normal analog-to-digital conversion to obtain digital values from bit 1 (MSB) to bit 8 (LSB), and outputs them to the CPU. 2) And (3) repeating the step (1) by the SAR ADC within a period of time, and obtaining the digital quantity output by the SAR ADC within the period of time by the CPU. 3) And analyzing and summarizing rules of the digital quantity and the time obtained in the period of time by the CPU through machine learning. For example, at noon in winter, the CPU finds that the input analog voltage is within a certain small range (for example, 1/16 Vref-0), and concludes that the temperature in this period is generally low, that is, the first 4 bits of the digital quantity are generally 0, the reference voltage Vref can be changed to the original 1/16, and the reference voltage approaches to the 1 st bit to the 8 th bit, which is equivalent to using 8 bits to represent the original last 4 bits, so that the resolution is greatly improved, and the power consumption of the SAR ADC is also reduced due to the reduction of the reference voltage. The CPU then stores the change in the reference voltage in the non-volatile memory. 4) The SAR control logic changes its reference voltage through information in the non-volatile memory and then performs a complete 1 st bit to 8 th bit approximation as shown in fig. 12. 5) Judging whether the conversion is correct, specifically judging whether the approached digits are all 1 or all 0, if all 0 or all 1, indicating that the obtained digital quantity is in a state to be jumped and has a larger difference with an actual value, and at the moment, changing the reference voltage into the original value and performing a complete approach from the 1 st digit to the 8 th digit again; if the conversion is correct, i.e. the approached bits are not all 1 or all 0, the conversion is completed, the obtained digital quantity is output to the CPU to represent the last 4 bits of the digital quantity, and the first 4 bits are preset 0000, and then the next conversion is waited. Thus, in most cases, SAR ADCs operate with higher resolution and lower power consumption.
In summary, the present invention provides a successive approximation register type analog-to-digital converter, which mainly includes a sampling comparator, a digital-to-analog converter, a controller, a register, a memory, a processor and a reference circuit; the comparator compares the input analog quantity with each reference analog quantity in turn, and outputs a digital signal reflecting the comparison result through the output terminal. The reference circuit is a reference power supply circuit with programmable output, and can improve different power supply signals by itself or according to a power supply control signal output by the processor. The processor is connected with the output end of the memory and used for receiving and analyzing the digital signals in a time period and outputting an analysis result corresponding to the time period, and the processor periodically reads the digital signals stored in the memory so as to realize the self-learning updating process of the processor on the analysis result. The controller receives signals of the comparator and the processor, is respectively connected with the register and the digital-to-analog conversion circuit, and is used for reading a comparison result from the comparator and outputting a digital signal to the register according to the comparison result; and receives the processor instruction to output the particular DAC digital bit control signal. The successive approximation register analog-to-digital converter changes the search strategy according to the information in the storage module, and reduces the approximation times, thereby achieving the purposes of reducing power consumption, accelerating speed or increasing resolution.
While the specification concludes with claims defining exemplary embodiments of particular structures for practicing the invention, it is believed that other modifications will be made in the spirit of the invention. While the above invention sets forth presently preferred embodiments, these are not intended as limitations.
Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above description. Therefore, the appended claims should be construed to cover all such variations and modifications as fall within the true spirit and scope of the invention. Any and all equivalent ranges and contents within the scope of the claims should be considered to be within the intent and scope of the present invention.
Claims (5)
1. A successive approximation register analog-to-digital converter, comprising:
the comparator comprises a positive phase input end, a negative phase input end and a comparison output end;
the positive phase input end is used for receiving an input analog quantity;
the digital-to-analog converter comprises an input pin, a reference power supply pin and an output pin; the digital-to-analog converter outputs a plurality of reference analog quantities with different sizes through the output pin;
the inverting input end of the comparator is connected with the digital-to-analog converter;
the comparator receives each reference analog quantity in sequence through the inverting input end, compares the input analog quantity with each reference analog quantity in sequence, and outputs a digital signal reflecting a comparison result through the comparison output end;
the controller comprises a first control input end, a second control input end, a control output end and a signal output end;
the first control input of the controller is connected with the comparison output of the comparator to receive the digital signal;
the first control output end of the controller is connected with the input pin of the digital-to-analog converter so as to output a first control signal to the digital-to-analog converter, wherein the first control signal is used for controlling the reference analog quantity output by the digital-to-analog converter;
the signal output end of the controller is used for outputting the digital signal;
the register is connected with the signal output end of the controller and used for receiving and temporarily storing the digital signal output by the controller;
the memory is connected with the register so as to extract the temporarily stored digital signals from the register and store the digital signals;
the processor comprises a signal input port, a first control output port and a second control output port;
the signal input port of the processor is connected with the memory so as to receive and analyze the digital signal in a preset time period and output a corresponding analysis result;
the first control output port of the processor is connected with the second control input end of the controller so as to output the analysis result corresponding to the time period to the controller, and therefore the self-learning updating process of the processor on the analysis result is achieved;
the reference circuit is connected with the second control output port of the processor to receive a second control signal corresponding to the time period;
the reference circuit is also connected with the reference power supply pin of the digital-to-analog converter so as to output a reference voltage to the digital-to-analog converter according to the second control signal;
the digital-to-analog converter performs weight calculation on the received first control signal and the reference voltage to form the reference analog quantity;
the controller has the functions of logic conversion and digital output;
the controller changes a control mode according to the analysis result, wherein the control mode comprises the following steps: fixing the electric potential of a specific digit, and changing the conversion digit;
the reference circuit is a power supply circuit with a power supply which is controlled in a programmable way;
through self-learning, different conversion strategies can be set according to different scenes, the number of bits required to be compared is reduced, or the power supply voltage is changed, the reference voltage is reduced, the precision is improved, and the power consumption is reduced.
2. The successive approximation register analog-to-digital converter according to claim 1, wherein when each bit of the digital signal obtained by the analysis is 1 or 0, the controller restores a value range of a reference voltage output by the reference circuit by the second control signal.
3. The successive approximation register analog to digital converter according to claim 1, wherein said memory comprises a non-volatile memory.
4. The successive approximation register analog-to-digital converter according to claim 3, wherein said memory is manufactured using a back-end non-volatile memory production process compatible with CMOS processes.
5. The successive approximation register analog-to-digital converter according to claim 4, wherein the memory is fabricated using FinFET transistors.
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| US20070103357A1 (en) * | 2000-06-19 | 2007-05-10 | Silicon Labs Cp, Inc. | Analog-to-digital converter with low power track-and-hold mode |
| US20130135125A1 (en) * | 2010-03-17 | 2013-05-30 | Texas Instruments Incorporated | Electronic Device and Method for Analog to Digital Conversion Using Successive Approximation |
| CN105531933A (en) * | 2013-09-11 | 2016-04-27 | 美敦力公司 | Ultra low power interface using adaptive successive approximation register |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070103357A1 (en) * | 2000-06-19 | 2007-05-10 | Silicon Labs Cp, Inc. | Analog-to-digital converter with low power track-and-hold mode |
| US20130135125A1 (en) * | 2010-03-17 | 2013-05-30 | Texas Instruments Incorporated | Electronic Device and Method for Analog to Digital Conversion Using Successive Approximation |
| CN105531933A (en) * | 2013-09-11 | 2016-04-27 | 美敦力公司 | Ultra low power interface using adaptive successive approximation register |
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