CN106776468B

CN106776468B - Dual-redundancy reconfigurable satellite-borne computer system based on CPCI bus

Info

Publication number: CN106776468B
Application number: CN201611204421.1A
Authority: CN
Inventors: 刘振星; 高丁; 张振; 孙立超; 张琦
Original assignee: Shandong Institute of Space Electronic Technology
Current assignee: Shandong Institute of Space Electronic Technology
Priority date: 2016-12-23
Filing date: 2016-12-23
Publication date: 2020-03-17
Anticipated expiration: 2036-12-23
Also published as: CN106776468A

Abstract

The invention discloses a dual-redundancy reconfigurable on-board computer system based on a CPCI bus, which is designed to support a dual-computer hot backup mode and simultaneously and independently complete respective work tasks, thereby meeting the requirements of the software radio technology on the generalization, standardization, modularization and reconfiguration of a hardware platform at home and abroad and the requirements of long service life and high reliability of the redundancy design of on-board electronic equipment; by designing a flexible logic control circuit, the reconfiguration of a computer system can be realized in various ways, and the safety and the reliability of the computer system are improved; the schematic diagrams of the dual-redundancy computer system are completely consistent, and the aims of generalization, standardization and modularization of a hardware platform are fulfilled; the back board of the computer system supports at least two slots and at most eight slots, can conveniently configure the functional board card according to different task requirements, and has the characteristic of expandability.

Description

Dual-redundancy reconfigurable satellite-borne computer system based on CPCI bus

Technical Field

The invention belongs to the technical field of software radio, and particularly relates to a dual-redundancy reconfigurable on-board computer system based on a CPCI bus.

Background

The basic idea of the software radio technology is to realize hardware configuration through the software technology on the basis of a modularized and universal hardware platform, and the software radio technology has flexible reconfigurable characteristics. One of the key technologies is to realize the reconfigurable function of a computer system, and the system reconfiguration is one of important means for improving the safety and reliability of the computer. The redundancy design is one of requirements for satellite-borne key electronic equipment, and aims to reduce single-point failure and improve task reliability.

On the bus architecture, the CPCI bus is a bus interface method often adopted by software radio hardware platforms. In 1994, for the purpose of applying the PCI bus in the embedded domain, the international association of industrial computer manufacturers proposed the CPCI high performance industrial bus standard based on the electrical specification of the PCI bus. The CPCI bus has the characteristics of hot plugging, high openness and high reliability, and is widely applied to the fields of industrial control computers and communication products. Generally, only one system card is arranged in the CPCI bus, so that the reconfiguration of the system card cannot be realized, and the redundancy design requirement of the satellite-borne electronic equipment cannot be met. For example, chinese patent CN102571317A, entitled PCI bus-based data synchronization method and system in software radio system, adopts a single processor module architecture, i.e. only one system card.

Disclosure of Invention

The invention provides a dual-redundancy reconfigurable satellite-borne computer system based on a CPCI bus, aiming at the requirements of software radio technology at home and abroad on generalization, standardization, modularization and reconfiguration of a hardware platform and the requirement of taking long service life and high reliability into consideration for redundancy design of satellite-borne electronic equipment.

A dual-redundancy reconfigurable on-board computer system based on a CPCI bus comprises two system cards and a back board; the two system cards are connected through a CPCI bus on the backboard;

the system card comprises a processor, control logic and a bottom connector; the processor is connected with the control logic, the processor is connected with the back plate through a bottom connector, and the logic control is also connected with the back plate through the bottom connector;

the control logic controls the processor of the system card to be in an on-duty state or an off-duty state according to the received reconfiguration instruction; meanwhile, a reconfiguration instruction sent by the non-counterpart system card is sent to the control logic of the counterpart system card through the CPCI bus; the reconfiguration instruction is a remote control instruction received from the outside, or a reconfiguration instruction received from a processor in the system card, or a reconfiguration instruction received from an opposite system card; after receiving a reset instruction, the control logic controls the processor of the system card to reset; when the system card is in the current working state, after the control logic receives the reset command twice, the processor of the system card is controlled to reset and be in the non-working state, and the reset command and the reconstruction command that the system card is the working system card are sent to the opposite control logic through the CPCI bus.

Further, the system card further comprises a clock signal control circuit; the control logic comprises a signal direction control circuit and a reset signal control circuit; the processor comprises an arbiter, an IDSEL decoder and an interrupt controller;

respectively defining the two system cards as a system card A and a system card B, and respectively defining modules included in the system card A as: the system comprises a processor A, a control logic A and a clock signal control circuit A; the modules included in the system card B are respectively defined as: the processor B, the control logic B and the clock signal control circuit B; then, when the system card a is reconfigured as the system card on duty and the system card B is reconfigured as the system card not on duty:

the reset signal control circuit in the control logic A provides a local reset signal for the processor A, and controls the signal direction control circuit in the system card to send the reset signal to the system card B through the connector;

the signal direction control circuit A controls the clock signal control circuit A to provide a local clock for the processor A, and simultaneously provides a clock for the system card B through a bottom plate connector; the signal direction control circuit A controls an interrupt controller in the processor A to serve as an interrupt controller of the whole system; the signal direction control circuit A controls an IDSEL decoder in the processor A to be used as an IDSEL decoder of the whole system; the signal direction control circuit A enables the arbitrator in the processor A to be used as the arbitrator of the whole system;

a signal direction control circuit B in the control logic B receives a reset signal and sends the reset signal to a processor B; the clock signal control circuit B acquires a CPCI clock as a local clock of the processor B through a bottom plate connector;

the signal direction control circuit B controls an interrupt controller in the processor B to be forbidden as an interrupt controller of the whole system; the signal direction control circuit B controls an IDSEL decoder in the processor B to disable the IDSEL decoder as the whole system, and simultaneously provides an IDSEL signal of a CPCI bus for the processor B; the signal direction control circuit B controls the arbiter in the disable processor B to be an arbiter that is a system CPCI bus.

Preferably, the processor is model MPC 8245.

Preferably, the bus permission signal pin of the arbiter of the processor A is connected with the request signal pin of the arbiter of the processor B; the request signal pin of the arbiter of the processor A is connected with the arbiter bus permission signal pin of the processor B.

Preferably, a pin of the interrupt controller of the processor a is connected to an interrupt request signal pin of the interrupt controller of the processor B; and an interrupt request signal pin of the interrupt controller of the processor A is connected with a pin of the interrupt controller of the processor B.

Further, the clock signal control circuit comprises a crystal oscillator and a clock buffer; wherein the model of the clock buffer is CY 2309; the signal output end of the crystal oscillator is connected with the REF reference end of the chip CY 2309; the control signal of the signal direction control circuit is accessed to the enable control terminals S1 and S2 of the chip CY2309, and the control signal controls the chip CY2309 to output the clock signal or not to output the clock signal; the signal output terminal CLKA1 of the chip CY2309 outputs a clock signal for the present system card, and the output terminal CLKB1 outputs a clock signal for another system card.

Further, the signal direction control circuit receives a local reconfiguration instruction, an external remote control instruction, a 2-time reset command and a reconfiguration instruction sent by the opposite system card; after the signal direction control circuit takes or operates the local reconstruction instruction, the external remote control instruction and the 2-time reset instruction, the obtained result A is subjected to AND operation with the reconstruction instruction sent by the system card of the opposite side to obtain a system reconstruction instruction PCI-DIR; when the reconstruction instruction sent by the opposite system card is a ' the system card is a ' reconstruction instruction of the system card on duty ', the reconstruction instruction sent by the opposite system card is effective and is used as a system reconstruction instruction PCI-DIR; and when the local reconstruction instruction, the external remote control instruction or the 2-time reset instruction is a reconstruction instruction that the system card is a non-current system card, the result A is valid and is used as a system reconstruction instruction PCI-DIR.

Further, the signal direction control circuit comprises a U39 device with a model 74HC157 and a U36 device with a model 74HC 245;

the A1 pin of U39 is connected with a local reset signal generated by the system card; the S pin is a control pin and receives a system reconfiguration command PCI _ DIR, and the Q1 pin is connected with the B0 pin of U36;

a0 pin of U36 is connected with the connector, and DIR pin receives system reconfiguration command PCI _ DIR;

when the system reconfiguration instruction PCI _ DIR is in a low level, a pin A1 of the U39 is connected with a pin Q1, a pin Q1 sends a local reset signal of the system card to a pin B0 of the U36 from a pin A1, and the received pin A0 is sent to the opposite system card through a connector;

when the system reconfiguration command PCI _ DIR is at a high level, the a0 pin of the U36 receives a system reset signal transmitted from the other system card through the connector, and the B0 pin transmits the system reset signal to the processor of the own system card.

Furthermore, when the system reconfiguration command PCI _ DIR is at a low level, the system card provides a system interrupt controller, and interrupt signals PCI _ INTA #, PCI _ INTB #, PCI _ INTC #, and PCI _ INTD # on the CPCI bus are respectively connected to the processor in the system card through pins B1-B4 of U36; pins Q3 and Q4 of the system card output clock signal output enable signals to provide a synchronous clock for the system.

Furthermore, when the system reconfiguration command PCI _ DIR on the opposite system card is at a low level, the opposite system card provides a system interrupt controller, and interrupt signals PCI _ INTA #, PCI _ INTB #, PCI _ INTC #, and PCI _ INTD # on the CPCI bus are respectively connected to the processor in the opposite system card through pins B1-B4 of U36; the pins Q3 and Q4 of the system card do not output the clock signal output enable signal, and the clock signal of the entire system is provided by the counterpart system card.

The invention has the following beneficial effects:

(1) the computer system based on the CPCI bus is designed to support a dual-computer hot backup mode, can simultaneously and independently complete respective work tasks, and meets the requirements of the software radio technology on the generalization, standardization, modularization and reconfiguration of a hardware platform at home and abroad and the requirement of the redundancy design of satellite-borne electronic equipment on long service life and high reliability.

(2) By designing a flexible logic control circuit, the reconfiguration of a computer system can be realized in various ways, and the safety and the reliability of the computer system are improved;

(3) the schematic diagrams of the dual-redundancy computer system are completely consistent, and the aims of generalization, standardization and modularization of a hardware platform are fulfilled;

(4) the back board of the computer system supports at least two slots and at most eight slots, can conveniently configure the functional board card according to different task requirements, and has the characteristic of expandability.

Drawings

FIG. 1 is a block diagram of the system components of the present invention;

FIG. 2 is a block diagram of one of the system card components of the present invention;

FIG. 3 is a pin diagram of a processor according to the present invention;

FIG. 4 is a signal diagram of a cross-connect of the present invention;

FIG. 5 is a schematic diagram of the signal connections of the control logic of the present invention;

FIG. 6 is a schematic diagram of a clock signal control circuit according to the present invention;

FIG. 7 is a schematic diagram of a reset signal logic control circuit of the present invention;

FIG. 8 is a schematic diagram of a signal direction control circuit according to the present invention;

FIG. 9 is a pin diagram of CPCI J1A;

fig. 10 is a CPCI J2A pin diagram.

Detailed Description

The invention is described in detail below by way of example with reference to the accompanying drawings.

A dual-redundancy reconfigurable on-board computer system based on a CPCI bus comprises a system card A, a system card B and a back panel, wherein the system is composed of a block diagram as shown in figure 1.

In fig. 1, the backplane supports at most eight slots, and six slots are taken as an example to specifically describe the implementation manner. The system card A consists of a processor MPC8245(A), a control logic (A) and connectors CPCI J1A and CPCI J2A.

The reconfiguration condition of the system card on duty comprises the following steps: the external remote control instruction A or the external remote control instruction B can complete the reconstruction of the system card on duty through control logic; the local processor MPC8245(A) or the local processor MPC8245(B) can complete the reconstruction of the system card on the spot through the control logic; and the watchdog in the reset unit of the system card A or the system card B only resets the system card by one-time dog biting, and the watchdog continuously resets the whole system by two-time dog biting and completes the reconstruction of the system card on duty.

The reconfiguration operation of the system card on duty comprises that the system card is forbidden to be used as the system card on duty and the system card corresponding to the trigger is the system card on duty.

When the system card is reconstructed into an external card, the system card is controlled by control logic, the reset unit of the system card does not provide system reset for the whole system any more, and the local reset of the system card is controlled by system reset; its clock buffer no longer provides the CPCI clock signal for the whole system, and its local clock is provided by the CPCI clock; the interrupt controller of the system is no longer used as the interrupt controller of the whole system; the IDSEL decoder is no longer used as the IDSEL decoder of the CPCI bus of the system; its arbiter no longer acts as an arbiter for the system CPCI bus.

With reference to fig. 1, the reconstruction implementation process will be described by taking as an example that the system a is reconstructed as a non-current system card and the system B is reconstructed as a current system card: 1. when the control logic A of the class system card A receives an external remote control instruction A, the control processor A is in a non-on-duty state, meanwhile, a reconfiguration command is transmitted to the control logic B through a CPCI bus on a back plate, and the control logic B controls the processor B to be in an on-duty state; 2. the processor A controls the control processing A to be in a non-working state through the control logic A, meanwhile, a reconfiguration command is transmitted to the control logic B through a CPCI bus on the backboard, and the control logic B controls the processor B to be in a working state; 3. when the on-duty system is the system card A, two successive watchdog resets occur, the control logic A controls the processor A to be in the non-on-duty state, and meanwhile, the reconstruction command is transmitted to the control logic B through the CPCI bus on the backboard, and the control logic B controls the processor B to be in the on-duty state.

The system card B is completely consistent with the system card a in a circuit schematic diagram, and the implementation manner is specifically described below by taking the system card a as an example, and differences between the system card B and the system card a are given. The block diagram of the system card a is shown in fig. 2.

Referring to fig. 2, the reconfiguration of the system card a and the system card B will be described by taking the case of reconfiguring the system card a as a non-current system card and reconfiguring the system card B as a current system card.

A reset signal control circuit in the control logic (B) is a local reset signal of the MPC8245(B) of the processor, and simultaneously, a system reset signal is provided for the whole system through a bottom plate connector; the clock signal control circuit provides a local clock for the MPC8245(B) of the processor, and provides a CPCI clock for the whole system through a bottom plate connector; the signal direction control circuit controls an interrupt controller in a processor MPC8245(B) to be used as an interrupt controller of the whole system; the IDSEL decoder in the signal direction control circuit control processor MPC8245(B) is used as the interrupt controller of the whole system and is used as the IDSEL decoder of the CPCI bus of the system; the control logic (B) controls the arbiter in the enable processor MPC8245(B) to be the arbiter that is the system CPCI bus.

A reset signal control circuit in the control logic (A) acquires a system reset signal through a bottom plate connector as a local reset signal of the processor MPC8245 (A); a clock signal control circuit in the control logic (A) acquires a CPCI clock through a bottom plate connector as a local clock of the MPC8245(A) of the processor; the signal direction control circuit controls an interrupt controller in the processor MPC8245(A) to be forbidden as an interrupt controller of the whole system; the signal direction control circuit controls an IDSEL decoder in the processor MPC8245(A) to prohibit the IDSEL decoder serving as a system CPCI bus, and simultaneously provides an IDSEL signal of the CPCI bus for the processor MPC8245 (A); control logic (a) controls the arbiter in disable processor MPC8245(a) to be the arbiter that acts as the system CPCI bus.

The pins associated with processor MPC8245(a) in system card a are shown in fig. 3.

The processor MPC8245(a) in the system card a is not controlled by the control logic (a), and CPCI bus signals directly connected to the connectors CPCI J1A and CPCI J2A include: address and data signals AD [31:0], C/BE [3:0] # and PAR, arbitration signals REQ # and GNT #, control signals FRAME #, IRDY #, TRDY #, STOP #, LOCK # and DEVSEL #, error report signals PERR # and SERR #.

The arbitration signal and the interrupt signal of the processor MPC8245(a) in the system card a and the processor MPC8245(B) in the system card B are cross-connected, as shown in fig. 4. In fig. 3, the system card a is soldered with the fixed resistors R610, R611, R614, and R615, and is not soldered with the resistors R612, R609, R613, and R616; the system card B is soldered with the fixed resistors R612, R609, R613 and R616, and the signal cross connection shown in fig. 4 can be realized without soldering the resistors R610, R611, R614 and R615.

The signals required to be controlled by the control logic (A) in the system card A comprise: clock signals PCI _ CLK (including PCI _ CLK1, PCI _ CLK2, PCI _ CLK3, PCI _ CLK4, PCI _ CLK5, PCI _ CLK6), asynchronous RESET signals PCI _ RESET #, initialization device selection signals P _ IDSEL, interrupt signals PCI _ INT # (including PCI _ INTA #, PCI _ INTB #, PCI _ INTC #, PCI _ INTD #), on-duty system card reconfiguration command signals SEND _ CMD _ DIR, REC _ CMD _ DIR between system card a and system card B.

The schematic diagram of the clock signal control circuit in the control logic (a) is shown in fig. 6.

The 33MHz crystal oscillator output signal is connected to the REF reference terminal of the clock buffer chip CY2309 through the resistor R532, and the CY2309 outputs clock signals PCI _ CLK1 to PCI _ CLK 6. PCI _ CLK1 provides a clock signal for MPC8245(A) of system card A, and in FIG. 3, system card A is soldered with fixed resistor R592, and resistor R593 is not soldered; PCI _ CLK6 provides a clock signal for MPC8245(B) of system card B, and in FIG. 3, system card B is soldered with fixed resistor R593 and resistor R592 is not soldered; PCI _ CLK2 provides a clock signal for peripheral card 1 in FIG. 1; PCI _ CLK3 provides a clock signal for peripheral card 2 of FIG. 1; PCI _ CLK4 provides a clock signal for peripheral card 3 in FIG. 1; PCI _ CLK5 provides a clock signal for peripheral card 4 in FIG. 1. The enable control terminals S1 and S2 of CY2309 are connected to the Q3 and Q4 outputs of 74HC157 in fig. 8, respectively. When the system card A is the best system card in class, the Q3 and Q4 output ends of the 74HC157 output high level, and the CY2309 normally outputs clock signals PCI _ CLK1 to PCI _ CLK 6; when the system card a is most used as a normal peripheral card, the Q3 and Q4 outputs of the 74HC157 are low, and the clock signals PCI _ CLK1 to PCI _ CLK6 output by the CY2309 are in high impedance state.

The schematic diagram of the reset signal logic control circuit in the control logic (a) is shown in fig. 7.

The RESET # is generated when a U29 with the model of MAX811T is powered on or powered off, and is changed into a high-level effective RESET pulse RESET after passing through a NOT gate U49B with the model of 74HC14, and the RESET # is connected to a No. 4 pin of an OR gate U46B with the model of 74HC32 and serves as a dog pulling signal. The RESET # and watchdog signals WDT are respectively connected to

pins

10 and 9 of an or gate U45C with a model 74HC32 to generate a system RESET signal SYS _ RESET #, the input terminal A, B, C of the decoder 74HC138 is respectively connected to pins SDBA1, SDMA11 and SDMA12 of U41 with a model MPC8245 in fig. 3, and G2A # of U33 with a model 74HC138 is connected to pin RCS1# of MPC8245 in fig. 3. When MPC8245 writes system ROM space 0xFF1X _ XXXX, an active low command signal a _ CMD _ DIR is generated to reconstruct system card a as a normal peripheral card and system card B as an on-duty system card. When MPC8245 writes system ROM space 0xFF2X _ XXXX, another pull-DOG signal FEED _ DOG is generated for reconstructing system card A as a normal peripheral card and system card B as an on-duty system card. When U34 with model HC4060 generates two dog-biting-reset signals WDT, pins 9 and 8 of flip-flop U48B with model HC74 output high-level signal WDT _ DIR and low-level signal WDT _ DIR #, respectively, WDT _ DIR is used for reconstructing system card a as a normal peripheral card, and SYSA _ CMD _ DIR generated by WDT _ DIR is connected to the signal direction control circuit in fig. 8, and is used for reconstructing system card B as a current-class system card. When the system card A is the current class system card, WDT _ DIR # and CMD _ DIR control arbitration enable signal P _ MAA2 generated by U45A in the signal direction control circuit of FIG. 8 are low, and MPC8245(A) in the system card A enjoys CPCI bus arbitration right; when the system card a is a normal peripheral card, WDT _ DIR # and CMD _ DIR control arbitration enable signal P _ MAA2 generated by U45A in the signal direction control circuit of fig. 8 are high, and MPC8245(a) in the system card a does not enjoy CPCI bus arbitration right.

The schematic diagram of the signal direction control circuit in the control logic (a) is shown in fig. 8.

A reconstruction command signal IN _ CMD _ DIR of a local processor MPC8245(A), an external remote control 3.3V high pulse effective reconstruction command signal EX _ CMD _ DIR and an output signal WDT _ DIR after two dog bites are IN parallel or IN a relation, an obtained result A is subjected to AND operation with a reconstruction command REC-CMD-DIR sent by a system card of the opposite side, and a system reconstruction command PCI-DIR is obtained; the signal direction control circuit mainly comprises U39 with the model 74HC157 and U36 with the model 74HC245, and the A1 pin of U39 is connected with a local reset signal generated by the system card; the S pin is a control pin, receives a signal PCI _ DIR, and controls the sending terminal Q1 to send a signal from the receiving terminal A1 pin or a signal from the receiving terminal B1 pin according to the signal PCI _ DIR; the Q1 is connected with a B0 pin of the U36 and used for outputting a local reset signal or receiving a system reset signal sent by the U36; the A0 pin of the U36 is connected with the connector and receives a system reset signal sent by another system card or sends a local reset signal received by B0; the DIR pin of U36 receives signal PCI _ DIR to control the B0 and A0 pins as receiving end or sending end;

the reconfiguration command signal IN _ CMD _ DIR, the external remote control 3.3V high pulse valid reconfiguration command signal EX _ CMD _ DIR and the two times of dog biting output signal WDT _ DIR of the local processor MPC8245(A) can prohibit the system card A from being used as the system card on duty, and the SEND _ CMD _ DIR signal is generated by the system card A and the system card A at the same time, is opposite to the signal PCI _ DIR IN logic and is connected to the REC _ CMD _ DIR of the system card B to enable the system card B to be used as the system card on duty. The SEND _ CMD _ DIR signal of the system card B is connected to the REC _ CMD _ DIR of the system card a, and when the system card B is disabled as the system card, the system card a is enabled as the on-duty system card.

When the signal PCI _ DIR is low, the system card a is used as a system card in class, the pin a1 of the U39 is connected to the pin Q1, the pin Q1 transmits the local reset signal received by the pin a1 to the pin B0 of the U36, and the received signal from the pin a0 is transmitted to another system card B and other peripheral cards through connectors. A system RESET signal SYS _ RESET # of the system card A provides a RESET signal for the whole system including a CPCI bus; the system card a provides a system interrupt controller, and interrupt signals PCI _ INTA #, PCI _ INTB #, PCI _ INTC #, and PCI _ INTD # on the CPCI bus are respectively connected to external interrupt input pins IRQ1, IRQ2, IRQ3, and IRQ4 of a processor MPC8245(a) in the system card a through 74HC 245; the P _ IDSEL signal of the processor MPC8245(A) is connected to the 1K pull-down resistor through the 74HC 157; the signals CY _ S1 and CY _ S2 of the system card A are connected to high level through 74HC157, so that the system card A is enabled to output clock signals to provide synchronous clocks for the system.

When the signal PCI _ DIR is at a high level, the a0 pin of U36 receives a system reset signal sent by the system card B through the connector, the B0 pin sends the system reset signal to the Q1 pin of U39 as a local reset signal, and sends the local reset signal to the processor a, and at this time, the system card a serves as an ordinary peripheral card and the system card B serves as a system card on duty. A system RESET signal SYS _ RESET # of the system card B provides a RESET signal for the whole system including a CPCI bus; the system card B provides a system interrupt controller, and interrupt signals PCI _ INTA #, PCI _ INTB #, PCI _ INTC #, and PCI _ INTD # on the CPCI bus are respectively connected to external interrupt input pins IRQ1, IRQ2, IRQ3, and IRQ4 of a processor MPC8245(B) in the system card B through 74HC 245; the P _ IDSEL signal of the processor MPC8245(A) is connected to the PCI _ AD11 signal through 74HC 157; the signals CY _ S1 and CY _ S2 of the system card a go low through 74HC157, and the system card a is disabled from outputting clock signals, which are provided by the system card B.

In fig. 8, the system card a is soldered with the fixed resistor R597, and is not soldered with the resistor R603, and the system card a is in an initial state as a system card on duty; and the fixed resistor R603 is welded and installed on the system card B, the R597 is not welded and installed, and the initial state of the system card B is used as an external card.

Pins of connectors CPCI J1A and CPCI J2A for connecting the backplane in the system card a are shown in fig. 9 and 10, respectively.

In summary, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A dual-redundancy reconfigurable on-board computer system based on a CPCI bus is characterized by comprising two system cards and a back board; the two system cards are connected through a CPCI bus on the backboard;

the control logic controls the processor of the system card to be in an on-duty state or an off-duty state according to the received reconfiguration instruction; meanwhile, a reconfiguration instruction sent by the non-counterpart system card is sent to the control logic of the counterpart system card through the CPCI bus; the reconfiguration instruction is a remote control instruction received from the outside, or a reconfiguration instruction received from a processor in the system card, or a reconfiguration instruction received from an opposite system card; after receiving a reset instruction, the control logic controls the processor of the system card to reset; when the system card is in the current-class state, after the control logic receives the reset command twice, the processor of the system card is controlled to reset and be in the non-current-class state, and the reset command and the reconstruction command that the system card is the current-class system card are sent to the opposite control logic through the CPCI bus.

2. The dual-redundancy reconfigurable on-board computer system based on the CPCI bus as claimed in claim 1, wherein the system card further comprises a clock signal control circuit; the control logic comprises a signal direction control circuit and a reset signal control circuit; the processor comprises an arbiter, an IDSEL decoder and an interrupt controller;

the signal direction control circuit B forbids an interrupt controller in the processor B as an interrupt controller of the whole system; the signal direction control circuit B inhibits an IDSEL decoder in the processor B from being used as an IDSEL decoder of the whole system, and provides an IDSEL signal of a CPCI bus for the processor B; the signal direction control circuit B disables the arbiter in the processor B as an arbiter that is a system CPCI bus.

3. The CPCI bus-based dual-redundancy reconfigurable on-board computer system as claimed in claim 2, wherein the type of the processor is MPC 8245.

4. A dual redundant reconfigurable on-board computer system based on a CPCI bus as claimed in claim 3, wherein the bus enable signal pin of the arbiter of processor a is connected to the request signal pin of the arbiter of processor B; the request signal pin of the arbiter of the processor A is connected with the arbiter bus permission signal pin of the processor B.

5. A CPCI bus-based dual-redundancy reconfigurable on-board computer system as claimed in claim 3 or 4, wherein the pins of the interrupt controller of processor A are connected with the interrupt request signal pins of the interrupt controller of processor B; and an interrupt request signal pin of the interrupt controller of the processor A is connected with a pin of the interrupt controller of the processor B.

6. The CPCI bus-based dual-redundancy reconfigurable on-board computer system of claim 3, wherein the clock signal control circuit comprises a crystal oscillator and a clock buffer; wherein the model of the clock buffer is CY 2309; the signal output end of the crystal oscillator is connected with the REF reference end of the chip CY 2309; the control signal of the signal direction control circuit is accessed to the enable control terminals S1 and S2 of the chip CY2309, and the control signal controls the chip CY2309 to output the clock signal or not to output the clock signal; the signal output terminal CLKA1 of the chip CY2309 outputs a clock signal for the present system card, and the output terminal CLKB1 outputs a clock signal for another system card.

7. The dual-redundancy reconfigurable on-board computer system based on the CPCI bus of claim 2, wherein the signal direction control circuit receives a local reconfiguration instruction, an external remote control instruction, a 2-time reset command and a reconfiguration instruction sent by an opposite system card; after the signal direction control circuit takes or operates the local reconstruction instruction, the external remote control instruction and the 2-time reset instruction, the obtained result A is subjected to AND operation with the reconstruction instruction sent by the system card of the opposite side to obtain a system reconstruction instruction PCI-DIR; when the reconstruction instruction sent by the opposite system card is a ' the system card is a ' reconstruction instruction of the system card on duty ', the reconstruction instruction sent by the opposite system card is effective and is used as a system reconstruction instruction PCI-DIR; and when the local reconstruction instruction, the external remote control instruction or the 2-time reset instruction is a reconstruction instruction that the system card is a non-current system card, the result A is valid and is used as a system reconstruction instruction PCI-DIR.

8. The dual-redundancy reconfigurable on-board computer system based on the CPCI bus of claim 7, wherein the signal direction control circuit comprises U39 device model 74HC157 and U36 device model 74HC 245;

when a system reconfiguration command PCI _ DIR is in a low level, a pin A1 of U39 is connected with a pin Q1, a pin Q1 sends a local reset signal generated by the pin A1 from the system card to a pin B0 of U36, and the pin A0 is sent to the opposite system card through a connector after being received;

9. The dual-redundancy reconfigurable spaceborne computer system based on the CPCI bus as claimed in claim 8, wherein when the system reconfiguration command PCI _ DIR is low level, the system card provides a system interrupt controller, and the interrupt signals PCI _ INTA #, PCI _ INTB #, PCI _ INTC #, and PCI _ INTD # on the CPCI bus are respectively connected to the processor in the system card through the pins B1-B4 of U36; pins Q3 and Q4 of the system card output clock signal output enable signals to provide a synchronous clock for the system.

10. The dual-redundancy reconfigurable spaceborne computer system based on the CPCI bus as claimed in claim 8 or 9, wherein when the system reconfiguration command PCI _ DIR on the opposite system card is low level, the opposite system card provides a system interrupt controller, and interrupt signals PCI _ INTA #, PCI _ INTB #, PCI _ INTC #, and PCI _ INTD # on the CPCI bus are respectively connected to the processor in the opposite system card through pins B1-B4 of U36; the pins Q3 and Q4 of the system card do not output the clock signal output enable signal, and the clock signal of the entire system is provided by the counterpart system card.