CN106776372A - Emulation data access method and device based on FPGA - Google Patents
Emulation data access method and device based on FPGA Download PDFInfo
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- CN106776372A CN106776372A CN201710081428.7A CN201710081428A CN106776372A CN 106776372 A CN106776372 A CN 106776372A CN 201710081428 A CN201710081428 A CN 201710081428A CN 106776372 A CN106776372 A CN 106776372A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/28—Using a specific disk cache architecture
- G06F2212/282—Partitioned cache
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- Computer Hardware Design (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
Abstract
The invention discloses a kind of emulation data access method based on FPGA and device, the method includes：Buffer state table is set up, buffer state table is used for describing the state of each buffering area in memory, and each in state table all records a state for buffering area in correspondence memory；Subaddressing state table is set up, the description information of data buffer zone under a subaddressing of each list item current emulation of record emulator of subaddressing state table；Emulation data are received to be stored in or extract node address therein, subaddress information when reading application；Using node address, subaddress information as |input paramete, subaddressing state table entry address is drawn through Hash compression mapping algorithm；Subaddressing state table is searched according to the entry address, the record list item and buffer zone address of subaddressing is obtained, emulation data are stored in the corresponding buffering area of the buffer zone address or emulation data is read from the corresponding buffering area of the buffer zone address；It is stored in or reads renewal buffer state table and subaddressing state table list item information after finishing.The present invention greatly improved the number of nodes that single emulator supports parallel artificial, while also improving the service efficiency of memory.
Description
Technical field
The present invention relates to Bus simulator technical field of measurement and test, and in particular to it is a kind of for high-speed bus emulator based on
The emulation data access method and device of FPGA.
Background technology
High-speed bus emulator is mainly used in avionics Bus simulator and test system, is developed for avionics system
Half associative simulation test in kind, matter emulation test etc. are carried out in journey.Avionics system is used in rugged environment, it is ensured that avionics system
The completeness of functions of the equipments of uniting and the reliability of performance are the core missions in avionics system development process.Ground in avionics system
, it is necessary to carry out various l-G simulation tests on ground during system, to verify whole avionics system function, whether performance is up to standard.
With the development of avionics bus system, high speed avionics bus of new generation is in terms of supporting node quantity, communication bandwidth
Greatly improve, this also increases the design difficulty of high-speed bus emulator, the storage management for emulating data is therein one
Individual Major Difficulties.
The content of the invention
In order to solve the difficult point of above-mentioned prior art, the present invention propose it is a kind of for high-speed bus emulator based on
The memory management method and device of FPGA.
According to an aspect of the invention, there is provided a kind of emulation data access method based on FPGA, it includes following
Step：
S1：Buffer state table is set up, buffer state table is used for describing the state of each buffering area in memory, in state table
Each all record correspondence memory in a state for buffering area；
S2：Set up subaddressing state table, a son of each list item record emulator currently emulation of subaddressing state table
The description information of data buffer zone under address；
S3：Emulation data are received to be stored in or extract node address therein, subaddress information when reading application；
S4：Using node address, subaddress information as |input paramete, show that subaddressing state table enters through Hash compression mapping algorithm
Port address；
S5：Subaddressing state table is searched according to the entry address, the record list item and buffer zone address of subaddressing is obtained, will
Emulation data are stored in the corresponding buffering area of the buffer zone address or read emulation from the corresponding buffering area of the buffer zone address
Data；
S6：It is stored in or reads renewal buffer state table and subaddressing state table list item information after finishing.
According to another aspect of the present invention, there is provided a kind of emulation DAA based on FPGA, it includes：
Buffer state table sets up module, and the state of each buffering area in memory is described for setting up buffer state table,
Each in state table all records a state for buffering area in correspondence memory；
Subaddressing state table sets up module, and for setting up subaddressing state table, each list item record of subaddressing state table is imitative
The description information of data buffer zone under the subaddressing that true equipment is currently emulated；
Subaddressing state table entry address acquisition module, for receive emulation data be stored in or reads application when, extraction wherein
Node address, subaddress information, using node address, subaddress information as |input paramete, obtained through Hash compression mapping algorithm
Go out subaddressing state table entry address；
Data access module, for according to the entry address search subaddressing state table, obtain subaddressing record list item with
And buffer zone address, emulation data are stored in the corresponding buffering area of the buffer zone address or corresponding from the buffer zone address
Buffering area reads emulation data, and be stored in or reads finish after update buffer state table and subaddressing state table list item and believe
Breath.
The present invention compared with prior art, has the advantage that：
Host computer is not involved in emulating the memory management of data, alleviates the burden of host computer, reduces setting for upper computer software
Meter difficulty, the characteristics of work using each modular concurrent in FPGA inside, improves efficiency.
The access for emulate data using the present invention can greatly improved list while emulate hundreds of to thousands of passages
One emulator supports the number of nodes of parallel artificial.
Employ memory dice management, the scheme of dynamically distributes, compared to using fixed size Buffer allocation scheme
Improve the service efficiency of memory.
Brief description of the drawings
Fig. 1 shows principle schematic of the invention.
Fig. 2 shows that the list item of subaddressing state table of the invention defines schematic diagram.
Fig. 3 shows management schematic diagram in data buffer zone under subaddressing of the invention.
Fig. 4 shows that emulation data of the invention are stored in flow chart.
Fig. 5 shows emulation digital independent flow chart of the invention.
Specific embodiment
Emulation data storage and management method based on FPGA of the invention, multiple sections are realized for high-speed bus emulator
Point, emulates the management of data during multiple subchannel parallel artificial functions under each node.The source for emulating data includes but does not limit
In operating in all-purpose computer, embedded computer, dsp processor, arm processor, power pc processors etc., itself and FPGA
Interface include but is not limited to PCIE, rapid io, AXI and self-defined interconnection etc., the memory for using can be DRAM,
Block ram etc. in SRAM, FPGA.
The present invention is described in further detail below in conjunction with the accompanying drawings.
Fig. 1 is the original of the emulation data storage and management method based on FPGA for high-speed bus emulator of the invention
Reason schematic diagram.
Wherein, storage space size is distributed according to practical application, it is desirable to be continuous memory space, memory is with fixation
The piecemeal of size is managed, and the agreement feature that the size of piecemeal can be realized according to high-speed bus emulator determines, leads to
Often set according to bus protocol, it is general to require to be more than the agreement maximum frame size, and require to be byte.Each piecemeal is used as one
Individual data buffer zone.
Buffer state table is set up in fpga logic, is realized using FPGA inside Block ram resources.Buffer state
Table is used for describing each piecemeal in memory（Buffering area）State, each in state table all recorded one in correspondence memory
The state of individual buffering area.If the buffering area piecemeal is occupied, corresponding record position is 1, otherwise if the buffering area piecemeal is not occupied
With corresponding record position is 0.
Stand-by buffering area inquiry is realized in fpga logic, new data need acquisition one unappropriated slow first before being stored in
Regional address is rushed, stand-by buffering area enquiry module inquires about buffer state table in advance, obtains a number of stand-by buffer zone address
It is stored in be used in inactive data buffering area table, this kind of mode avoids each new data and is stored in and all go inquiry buffer state
Table, improves efficiency.
The corresponding buffering area of pointer being stored in inactive data buffering area table records position in buffer state table and will be set to
1, show that this buffering area is occupied.
After data buffer zone discharges in subaddressing buffering area chained list, by the buffering area in buffer state table
Record position 0, shows that this buffering area has been recovered, available.
Present invention is mainly used for the high speed data bus emulation many subchannels of multinode, such as in FC-AE-1553 bus protocols
Node address bit wide is 24bit, subaddressing（Subchannel）Bit wide is 32bit.Bus simulator would generally simultaneously emulate multiple
Node, address of node is not limited, while can support that the value of multiple subaddressings, subaddressing is not limited under each node.It is imitative
When true need that for each subaddressing under each node a data buffer records will be set up.
Subaddressing is set up in fpga logic（Subchannel）State table, is realized, son using FPGA inside Block ram resources
Address state table each list item record emulator currently under a subaddressing of emulation data buffer zone description information,
Record information form as shown in Fig. 2 the depth of subaddressing state table determine emulator simultaneously support emulation simulation node,
The quantity of subaddressing.
Mapping algorithm is compressed using Hash in fpga logic, due to node address and the spliced addressing space of subaddressing
It is far longer than the address space of subaddressing state table, it is impossible to set up and directly map, therefore mapping is compressed using hash algorithm.
Node address and subaddressing splicing are fixed the key of length by hash algorithm, the key that will be obtained is used as the subaddressing number
According to storage address of the buffer description information in subaddressing state table, the wherein length of key should be with subaddressing state table
Depth is consistent.
Completed in fpga logic to each subaddressing（Subchannel）The management of lower data buffer zone, buffering area under subaddressing
Using one-dimensional chained list way to manage, schematic diagram is as shown in Figure 3.This is record in the corresponding subaddressing state list item of subaddressing to delay
Rush under area head buffer zone address, tail buffer zone address, buffering area number etc. in data buffer zone.Each buffering in memory
There is individual region to deposit next data buffer address pointer information in buffering area chained list in area.Compile the data buffer zone of new application
Enter chained list afterbody；After head buffer data use, discharge the buffering area and update a buffer zone address.
Emulate data is stored in flow as shown in figure 4, comprising the following steps that：
Step 1, node address, subaddress information are extracted after receiving descending emulation packet；
Step 2, with node address, subaddress information draws subaddressing state as |input paramete through Hash compression mapping algorithm
Table entry address；
Step 3, carries out matched and searched in subaddressing state table, if finding occurrence, carries out next step；If not finding
With item and the address is unoccupied, then the record list item of this subaddressing is set up in this address；If not finding occurrence and being somebody's turn to do
Address is occupied, then calculate next entry address according to collision algorithm, then repeat step 3；
Step 4, obtains a buffer zone address in stand-by buffering area table, and emulation data are stored in into the data buffer zone；If this
Current no-buffer under subaddressing, then using this data buffer address as buffering area chained list head buffer zone address；Otherwise, will
This buffering area adds buffering area chained list afterbody, and corresponding operation is to insert this buffering area in the specific description area of current tail buffering area
Address, data length information；
Step 5, by the data buffer zone in buffer state table record position 1；
Step 6, updates subaddressing state table list item information, including head buffer zone address, head buffer data length, tail buffering area
Address, buffering area number etc., if wherein a certain information does not change can not update.
The reading flow of data is emulated as shown in figure 5, comprising the following steps that：
Step 1, receives emulation digital independent application, extracts node address, subaddress information；
Step 2, with node address, subaddress information draws subaddressing state as |input paramete through Hash compression mapping algorithm
Table entry address；
Step 3, carries out matched and searched in subaddressing state table, if finding occurrence, if remembering in subaddressing state table list item
The buffering area number of record is 0, then return to error message, otherwise carries out next step；If do not find occurrence and the address not by
Take, then return to error message, this kind of situation shows not setting up buffer records under the subaddressing；If do not find occurrence and
The address is occupied, then calculate next entry address according to collision algorithm, then repeat step 3；
Step 4, obtains the information such as head buffer zone address, head buffer data length in subaddressing state list item, reads correspondence
The data of buffering area in external memory storage, while obtaining the address of next data buffer zone；
Step 5, after the completion of discharge the buffering area, respective operations be by the data buffer zone in buffer state table record position
0。
Step 6, updates subaddressing state table list item information, including head buffer zone address, head buffer data length, buffering
Area's number etc..
By emulation data storage and management method of the invention, multinode, many subaddressings are capable of achieving（Subchannel）Emulation number
According to management, the node of support, the quantity of subaddressing mainly determines by the depth of subaddressing state table, Block ram in FPGA
Resource very abundant, it is different according to FPGA models, the k depth of several k to more than ten can be easily realized, therefore hundreds of to thousands of can be realized
The management of subaddressing.The buffering area under each subaddressing realizes dynamically distributes simultaneously, is finished and discharges immediately, memory service efficiency
It is very high.
It should be understood by those skilled in the art that, embodiments of the invention can be provided as method, system or computer program
Product.And, the present invention can be used to be can use in one or more computers for wherein including computer usable program code and deposited
The form of the computer program product implemented on storage media (including but not limited to magnetic disk storage and optical memory etc.).
The present invention is the flow chart and/or block diagram with reference to method and computer program product according to embodiments of the present invention
Come what is described.It should be understood that each flow and/or square frame during flow chart and/or block diagram can be realized by computer program instructions,
And the combination of the flow and/or square frame in flow chart and/or block diagram.These computer program instructions to general meter can be provided
The processor of calculation machine, special-purpose computer, Embedded Processor or other programmable data processing devices is made with producing a machine
Must be produced for realizing in flow chart one by the instruction of computer or the computing device of other programmable data processing devices
The device of the function of being specified in individual flow or multiple one square frame of flow and/or block diagram or multiple square frames.
These computer program instructions may be alternatively stored in can guide computer or other programmable data processing devices with spy
In determining the computer-readable memory that mode works so that instruction of the storage in the computer-readable memory is produced and include finger
Make the manufacture of device, the command device realize in one flow of flow chart or multiple one square frame of flow and/or block diagram or
The function of being specified in multiple square frames.
These computer program instructions can be also loaded into computer or other programmable data processing devices so that in meter
Series of operation steps is performed on calculation machine or other programmable devices to produce computer implemented treatment, so as in computer or
The instruction performed on other programmable devices is provided for realizing in one flow of flow chart or multiple flows and/or block diagram one
The step of function of being specified in individual square frame or multiple square frames.Obviously, those skilled in the art can carry out various to the present invention
Change with modification without departing from the spirit and scope of the present invention.So, if these modifications of the invention and modification belong to this hair
Within the scope of bright claim and its equivalent technologies, then the present invention is also intended to comprising these changes and modification.
Claims (14)
1. a kind of emulation data access method based on FPGA, it is characterised in that comprise the following steps：
S1：Buffer state table is set up, buffer state table is used for describing the state of each buffering area in memory, in state table
Each all record correspondence memory in a state for buffering area；
S2：Set up subaddressing state table, a son of each list item record emulator currently emulation of subaddressing state table
The description information of data buffer zone under address；
S3：Emulation data are received to be stored in or extract node address therein, subaddress information when reading application；
S4：Using node address, subaddress information as |input paramete, show that subaddressing state table enters through Hash compression mapping algorithm
Port address；
S5：Subaddressing state table is searched according to the entry address, the record list item and buffer zone address of subaddressing is obtained, will
Emulation data are stored in the corresponding buffering area of the buffer zone address or read emulation from the corresponding buffering area of the buffer zone address
Data；
S6：It is stored in or reads renewal buffer state table and subaddressing state table list item information after finishing.
2. the emulation data access method of FPGA is based on as claimed in claim 1, it is characterised in that also wrapped before step S1
Include step S0：Memory is divided into the piecemeal of fixed size, the size of piecemeal is set greater than the agreement most according to bus protocol
Big frame length, and be byte, n is positive integer, using each piecemeal an as data buffer zone.
3. the emulation data access method of FPGA is based on as claimed in claim 1, it is characterised in that if a certain buffering area piecemeal
Occupied, its corresponding record position in the buffer state table is set to 1, otherwise if the buffering area piecemeal is unoccupied,
Corresponding record position is set to 0.
4. the emulation data access method based on FPGA as claimed in claim 1, it is characterised in that if step S3 receive be
Emulation data are stored in application, in step s 5, when carrying out matched and searched in subaddressing state table according to the entry address, if
Do not find occurrence and the entry address is unoccupied, then the record list item of this subaddressing is set up in this address；If not looking into
Find occurrence and the entry address is occupied, then next entry address is calculated according to collision algorithm, then repeat step S5.
5. the emulation data access method based on FPGA as claimed in claim 1, it is characterised in that if step S3 receive be
Emulation digital independent application, in step s 5, if the buffering area number recorded in the subaddressing record list item for obtaining is 0,
Then return to error message；If not finding occurrence and the entry address being unoccupied, error message is returned；If not finding
With item and the entry address is occupied, then next entry address is calculated according to collision algorithm, then repeat step S5.
6. the emulation data access method of FPGA is based on as claimed in claim 1, it is characterised in that the subaddressing state table
List item information includes that node address, subaddressing, subaddressing status information, head buffer pointer, head buffer data length, tail delay
Rush area's pointer, buffering area number etc..
7. the emulation data access method of FPGA is based on as claimed in claim 1, it is characterised in that inquire about buffering area shape in advance
State table, obtains a number of stand-by buffer zone address and is stored in be used in inactive data buffering area table, is carrying out emulation data
A unappropriated buffer zone address is directly obtained when being stored in from inactive data buffering area table.
8. a kind of emulation DAA based on FPGA, it is characterised in that including：
Buffer state table sets up module, and the state of each buffering area in memory is described for setting up buffer state table,
Each in state table all records a state for buffering area in correspondence memory；
Subaddressing state table sets up module, and for setting up subaddressing state table, each list item record of subaddressing state table is imitative
The description information of data buffer zone under the subaddressing that true equipment is currently emulated；
Subaddressing state table entry address acquisition module, for receive emulation data be stored in or reads application when, extraction wherein
Node address, subaddress information, using node address, subaddress information as |input paramete, obtained through Hash compression mapping algorithm
Go out subaddressing state table entry address；
Data access module, for according to the entry address search subaddressing state table, obtain subaddressing record list item with
And buffer zone address, emulation data are stored in the corresponding buffering area of the buffer zone address or corresponding from the buffer zone address
Buffering area reads emulation data, and be stored in or reads finish after update buffer state table and subaddressing state table list item and believe
Breath.
9. the emulation DAA of FPGA is based on as claimed in claim 8, it is characterised in that also including data buffer zone
Division module, the piecemeal for memory to be divided into fixed size, the size of piecemeal is set greater than the association according to bus protocol
View maximum frame size, and be byte, n is positive integer, using each piecemeal an as data buffer zone.
10. the emulation DAA of FPGA is based on as claimed in claim 8, it is characterised in that if a certain buffering is distinguished
Block is occupied, and its corresponding record position in the buffer state table is set to 1, otherwise if the buffering area piecemeal is not occupied
With corresponding record position is set to 0.
The 11. emulation DAAs based on FPGA as claimed in claim 8, it is characterised in that if what is received is emulation
Data are stored in application, when data access module carries out matched and searched according to the entry address in subaddressing state table, if not
Find occurrence and the entry address is unoccupied, then the record list item of this subaddressing is set up in this address, if not searching
To occurrence and the entry address is occupied, then next entry address is calculated according to collision algorithm, then re-used described
Entry address carries out matched and searched in subaddressing state table.
The 12. emulation DAAs based on FPGA as claimed in claim 8, it is characterised in that if what is received is emulation
Digital independent application, when data access module carries out matched and searched according to the entry address in subaddressing state table, if obtaining
The buffering area number recorded in the subaddressing record list item for taking is 0, then return to error message；If do not find occurrence and
The entry address is unoccupied, returns to error message；If not finding occurrence and the entry address being occupied, according to punching
Prominent algorithm calculates next entry address, and then re-use the entry address carries out matched and searched in subaddressing state table.
The 13. emulation DAAs based on FPGA as claimed in claim 8, it is characterised in that the subaddressing state
Table list item information includes node address, subaddressing, subaddressing status information, head buffer pointer, head buffer data length, tail
Buffer pointer, buffering area number etc..
The 14. emulation DAAs based on FPGA as claimed in claim 8, it is characterised in that also including stand-by buffering
Area's enquiry module, is stored in inactive data and delays for inquiring about buffer state table, after a number of stand-by buffer zone address of acquisition
Rush to be used in area's table, the direct acquisition one from inactive data buffering area table when emulation data are stored in is unappropriated carrying out
Buffer zone address.
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| CN111833232B (en) * | 2019-04-18 | 2024-07-02 | 杭州海康威视数字技术股份有限公司 | Image processing apparatus |
| CN110674053A (en) * | 2019-09-30 | 2020-01-10 | 深圳忆联信息***有限公司 | SSD data storage node management method and device, computer equipment and storage medium |
| CN110674053B (en) * | 2019-09-30 | 2021-09-14 | 深圳忆联信息***有限公司 | SSD data storage node management method and device, computer equipment and storage medium |
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