CN106772176A - A kind of D.C. high-current standard source output intent and device confluxed based on parallel connection - Google Patents
A kind of D.C. high-current standard source output intent and device confluxed based on parallel connection Download PDFInfo
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
The invention discloses a kind of D.C. high-current standard source output intent and device confluxed based on parallel connection, method and step includes：Ensure that each DC output unit signal output is synchronous and sends electric current output order to each DC output unit by host computer；Each DC output unit parsing electric current output order obtains each harmonic content harmonic phase value of electric current to be generated, generates the analog current signal I of assigned frequency0And carry out closed loop feedback and obtain output DC current, most the output DC current parallel connection of each DC output unit is confluxed output at last；Device includes host computer and more than two DC output units, and DC output unit includes control unit, ripple output module, error amplifier, current amplification standard source and direct current transducer.The present invention has the advantages that output current is big, output accuracy is high, extension and simplification are flexible, has a wide range of application.
Description
Technical field
The High-accuracy direct current High-current output traced to the source the present invention relates to the calibration and DC current metering that are used for direct current table is straight
A kind of stream source, and in particular to D.C. high-current standard source output intent and device confluxed based on parallel connection.
Background technology
The fast development of Power Electronic Technique has led new round technological revolution.Currently, DC techniques are fast-developing, electronic
The technologies such as automobile, extra-high voltage direct-current transmission have moved towards maturation from the exploratory stage.Electric automobile becomes the most popular industry in the whole world
One of, it is tesla of the U.S. known to compatriots, domestic BYD E series etc., all move towards market；From Burner zone-on
It is domestic at present to be completed or in the extra-high voltage built since ± 800kV the extra-high voltage direct-current transmission engineerings such as sea, silk screen-southern Jiangsu put into operation
DC power transmission line is a plurality of up to 10.
The application of DC techniques has also urged the fast development in DC measurement field.For charging electric vehicle and extra-high voltage
DC measurement device (device such as including DC voltage transformer, DC current transformer, direct current energy meter) in direct current transportation
Calibrating and inspection, current many enterprises and mechanism do a lot of work.As southern auspicious relay protection, Xi'an Xi electricity Deng companies have produced use
In metering DC current, the transformer of voltage；Wasion, Ke Ludeng companies are had been developed that for measuring the straight of charging electric vehicle
Flow metering device has simultaneously come into operation etc..Multiple mechanisms have been developed that the standard straight for laboratory verification DC measurement device
Flow device.The technical requirements of flow directing device code related to detection method is also constantly put into effect.Guo Wang incorporated businesses standard
QGDW530-2010《D.C. high voltage transmission DC electronic current transformer technical specification》、QGDW531-2010《HVDC
Transmission of electricity direct current electronic voltage transformer technical specification》, national metrological verification regulations JJG 842-1993《Direct current energy meter》、
JJG 982-2003《DC resistance box》, to direct current instrument transformer, direct current energy meter, the technical requirements of resistance box and calibration method etc.
It is made that specified in more detail.
Currently, a large amount of calibration operations about DC measurement equipment are just carried out in high gear.Can be completed greatly in laboratory
The calibration operation of current DC table.But because the DC source of the big output of laboratory high accuracy is generally present, volume is big, equipment is stupid
The problem of weight, the scene of moving to goes development on-site proving work very difficult.It is therefore desirable to develop a kind of big output of high accuracy
Standard source, is easy to the development of metering device scene periodic calibration work.
The content of the invention
The technical problem to be solved in the present invention：For the above mentioned problem of prior art, there is provided a kind of output current is big, output
High precision, extension and simplify the D.C. high-current standard source output intent confluxed based on parallel connection that is flexible, having a wide range of application
And device.
In order to solve the above-mentioned technical problem, the technical solution adopted by the present invention is：
The present invention provides a kind of D.C. high-current standard source output intent confluxed based on parallel connection, and implementation steps include：
1) it is in advance that each is in parallel for exporting the output end of the DC output unit of DC current, by host computer to each
Individual DC output unit sends synchronous trigger pulse come whether signal output between judging each DC output unit is synchronous, such as
Really signal output is asynchronous between each DC output unit, redirects execution step 1)；Otherwise, execution step 2 is redirected)；
2) electric current output order is sent to each DC output unit by host computer；
3) each DC output unit parsing electric current output order obtains each harmonic content harmonic of electric current to be generated
Phase value, the analog current signal I of assigned frequency is generated according to each harmonic content harmonic phase value0；Each direct current
Current output DC current is sampled and reduces specified multiple and obtains sample rate current I by output unitx, by sample rate current IxAnd mould
Intend current signal I0Make the difference and obtain current compensation part Δ I, current compensation part Δ I input current power amplifier standard sources pass through
Current amplification standard source obtains the output DC current of each DC output unit；
4) the output DC current parallel connection of each DC output unit is confluxed output.
Preferably, step 1) detailed step include：
1.1) synchronous trigger pulse is sent to each DC output unit by host computer, the output of each DC output unit
While electric current, start rolling counters forward；
1.2) after specifying the time, while each DC output unit stops output current, by host computer to each
Individual DC output unit sends synchronous trigger pulse again, and the counter of each DC output unit is touched in lock-out pulse respectively
Give stopping timing；
1.3) specify a DC output unit as main frame, remaining DC output unit as slave, by main frame, slave
Count value is subtracted each other, if subtracting each other result is all higher than predetermined threshold value, between judging each DC output unit, signal output is not
It is synchronous, redirect execution step 1)；Otherwise judge signal output synchronization between each DC output unit, redirect execution step 2).
Preferably, step 3) in analog current signal I is generated according to each harmonic content harmonic phase value0It is detailed
Thin step includes：
S1 each harmonic content harmonic phase value) is generated into ripple Wave data；Meanwhile, send frequency control word K works
It is the input of phase accumulator, the phase accumulator is made up of N adder and N-bit register cascade, the FREQUENCY CONTROL
Word K is binary-coded phase increment value；
S2) output of N-bit register is fed back to the N input of adder and realizes cumulative function by phase accumulator,
In each clock pulses fc, N adder accumulates once frequency control word K, and exports corresponding increase by N-bit register
One phase increment of step-length so that phase accumulator is output as the linear increment sequence with K as step-length, is with K by described
The linear increment sequence of step-length is stored in wave memorizer；
S3 ripple signal) is obtained according to the sampling that to the wave memorizer table look-up of ripple Wave data, and by ripple
Signal carries out the analog current signal I that D/A is converted to assigned frequency by D/A modular converters0。
Preferably, step S3) by ripple signal carry out D/A change when, specifically refer to receive from host computer send it is same
Step trigger pulse, often receives a synchronous trigger pulse and then triggers a trigger pulse to interrupt, while being exported by being set to PPS
The source of synchronising signal of pattern exports synchronizing signal, the control of each DC output unit to the control unit of each DC output unit
Unit processed catches the zero-acrross ing moment of output waveform using genlock mechanism, when the mistake for capturing D/A modular converter output waveforms
Zero moment then triggers a DAC zero passage to interrupt, and then obtains the time between adjacent trigger pulse interruption, the interruption of DAC zero passages
Difference, and time difference input DDS digital frequency synthesizers are obtained into DAC frequency control signals, by the DAC frequency control signals
The control end of D/A modular converters is input into, the ripple signal of input is carried out D/A conversions by control D/A modular converters, obtains specifying frequency
The analog current signal I of rate0。
The present invention also provides a kind of D.C. high-current standard source output device confluxed based on parallel connection, including host computer and two
DC output unit more than individual, the DC output unit includes control unit, ripple output module, error amplifier, electricity
Stream power amplifier standard source and direct current transducer, described control unit is connected with host computer respectively, the output end of described control unit with
Ripple output module is connected, and the input all the way of the error amplifier is connected with the output end of ripple output module, Ling Yilu
Input is connected with the output end of direct current transducer, and the output end of the error amplifier is connected with current amplification standard source, institute
The input for stating direct current transducer is connected with the output end of current amplification standard source, and all DC output units current amplification
As D.C. high-current standard source output terminal after the output end parallel connection of standard source.
Preferably, described control unit includes microprocessor and communication interface, the microprocessor by communication interface and
Host computer is connected, and the ripple output module is connected with the output end of microprocessor.
Preferably, institute's described control unit also include display and Keysheet module, the display, Keysheet module respectively with
Microprocessor is connected.
Preferably, institute's described control unit also includes Pulse sampling device, the output end and microprocessor of the Pulse sampling device
Device is connected.
Preferably, institute's ripple output module includes dsp processor, N adder, N-bit register, Waveform storage
Device, D/A modular converters and reference clock module, the dsp processor are connected with microprocessor, the N adder, N post
Both storages concatenation forms phase accumulator, the output end of the dsp processor and the input of phase accumulator, described N
The output of register is connected with the address wire of wave memorizer, the ripple Wave data output end of the dsp processor, with reference to when
The output end of clock module is connected with wave memorizer jointly, the input of the D/A modular converters respectively with wave memorizer, ginseng
Examine clock module to be connected, the dsp processor tables look-up wave memorizer, storage, binary system is compiled in wave memorizer
The signal sampling value of code value form is found and obtains ripple signal, and ripple signal is carried out into D/A by D/A modular converters changes
To the analog current signal of assigned frequency, the output end of the D/A modular converters is connected with error amplifier.
The present invention is had the advantage that based on the D.C. high-current standard source output intent tool for confluxing in parallel：
1st, the present invention is straight to each by host computer between each DC output unit on the premise of signal output synchronization
Stream output unit sends electric current output order, and each DC output unit parsing electric current output order obtains each of electric current to be generated
Subharmonic content harmonic phase value, the analog current of assigned frequency is generated according to each harmonic content harmonic phase value
Signal I0；Current output DC current is sampled and reduces specified multiple and obtains sample rate current I by each DC output unitx, will
Sample rate current IxWith analog current signal I0Make the difference and obtain current compensation part Δ I, by current compensation part Δ I input current work(
Standard source is put, the output DC current of each DC output unit is obtained by current amplification standard source, confluxed skill using parallel connection
Art, is exported by the low current of the completely the same drive signal of multichannel and combines feedback regulation, obtains distortionless high-precision linear
High-current output, has the advantages that output current is big, output accuracy is high, extension and simplification are flexible.
2nd, the present invention can examine and determine direct current energy meter, DC ammeter, direct current instrument transformer, dc power table, and support upper
Machine software program control is exported, and supports secondary development, has the advantages that have a wide range of application.
The present invention is had the advantage that based on the D.C. high-current standard source output device tool for confluxing in parallel：The present invention is based on simultaneously
The D.C. high-current standard source output device that connection confluxes is the present invention based on the D.C. high-current standard source output side confluxed in parallel
The corresponding device of method, by its part and its annexation, can realize the present invention based on the D.C. high-current mark for confluxing in parallel
Quasi- source output intent, equally also has the present invention based on the foregoing excellent of the D.C. high-current standard source output intent for confluxing in parallel
Point, will not be repeated here.
Brief description of the drawings
Fig. 1 is the basic procedure schematic diagram of present invention method.
Fig. 2 is the schematic flow sheet of signal output synchronization judgement in the embodiment of the present invention.
Fig. 3 is the Principle of Synchronic Control schematic diagram of D/A conversions in the embodiment of the present invention.
Fig. 4 is the theory structure schematic diagram of embodiment of the present invention device.
Fig. 5 is the theory structure schematic diagram of ripple output module in the embodiment of the present invention.
Fig. 6 is the structural representation that embodiment of the present invention device is applied to direct current energy meter error testing.
Marginal data：1st, host computer；2nd, DC output unit；21st, control unit；211st, microprocessor；212nd, communication connects
Mouthful；213rd, Pulse sampling device；214th, Keysheet module；215th, Pulse sampling device；22nd, ripple output module；221st, dsp processor；
222nd, N adder；223rd, N-bit register；224th, wave memorizer；225th, D/A modular converters；226th, reference clock module；
23rd, error amplifier；24th, current amplification standard source；25th, direct current transducer.
Specific embodiment
As shown in figure 1, the present embodiment is based on the implementation steps bag of the D.C. high-current standard source output intent for confluxing in parallel
Include：
1) it is in advance that each is in parallel for exporting the output end of the DC output unit of DC current, by host computer to each
Individual DC output unit sends synchronous trigger pulse come whether signal output between judging each DC output unit is synchronous, such as
Really signal output is asynchronous between each DC output unit, redirects execution step 1)；Otherwise, execution step 2 is redirected)；
2) electric current output order is sent to each DC output unit by host computer；
3) each DC output unit parsing electric current output order obtains each harmonic content harmonic of electric current to be generated
Phase value, the analog current signal I of assigned frequency is generated according to each harmonic content harmonic phase value0；Each direct current output
Current output DC current is sampled and reduces specified multiple and obtains sample rate current I by unitx, by sample rate current IxWith simulation electricity
Stream signal I0Make the difference and obtain current compensation part Δ I, by current compensation part Δ I input current power amplifier standard sources, by electric current
Power amplifier standard source obtains the output DC current of each DC output unit；
4) the output DC current parallel connection of each DC output unit is confluxed output.
Hereafter will be by taking two DC output units as an example, and by two DC output units by the way of main frame and slave
Illustrate, the present invention is carried out further based on the D.C. high-current standard source output intent for confluxing in parallel and device
It is bright.It should be noted that two DC output units of the present embodiment are intended merely to facilitate by the way of main frame and slave
Bright, status is identical between output current link, two DC output units；In addition can also as needed using more
DC output unit, its principle is identical with the present embodiment, therefore will not be repeated here.
Whether the clock module of each DC output unit is precisely consistent, largely determines whether source can be synchronously defeated
Go out.In the present embodiment, step 1) detailed step include：
1.1) synchronous trigger pulse is sent to each DC output unit by host computer, the output of each DC output unit
While electric current, start rolling counters forward；
1.2) after specifying the time, while each DC output unit stops output current, by host computer to each
Individual DC output unit sends synchronous trigger pulse again, and the counter of each DC output unit is touched in lock-out pulse respectively
Give stopping timing；
1.3) specify a DC output unit as main frame, remaining DC output unit as slave, by main frame, slave
Count value is subtracted each other, if subtracting each other result is all higher than predetermined threshold value, between judging each DC output unit, signal output is not
It is synchronous, redirect execution step 1)；Otherwise judge signal output synchronization between each DC output unit, redirect execution step 2).
Referring to Fig. 2, response feedback mechanism is used in the present embodiment, after the synchronous trigger pulse of host computer sends, main frame,
Counter inside slave is started counting up under lock-out pulse triggering；While DC output unit stops output, counter exists
Lock-out pulse triggering is lower to stop timing；When stopping timing, host count device is counted P by main frame, slave respectivelycnt1And slave
Rolling counters forward Pcnt2Send to host computer and compare, between host computer calculating main frame, slave by main frame, slave count value phase
Subtract and obtain subtracting each other result Δ Pcnt, Δ Pcnt=Pcnt1-Pcnt2, when subtracting each other result Δ PcntLess than or equal to default threshold value Pcnt0When,
Main frame, signal output synchronization between slave are judged, when subtracting each other result Δ PcntMore than default threshold value Pcnt0When, judge main frame, from
Signal output is asynchronous between machine.
In the present embodiment, step 3) in analog current signal I is generated according to each harmonic content harmonic phase value0It is detailed
Thin step includes：
S1 each harmonic content harmonic phase value) is generated into ripple Wave data；Meanwhile, send frequency control word K works
It is the input of phase accumulator, phase accumulator is made up of N adder and N-bit register cascade, and frequency control word K enters for two
Make the phase increment value of coding；
S2) output of N-bit register is fed back to the N input of adder and realizes cumulative function by phase accumulator,
In each clock pulses fc, N adder accumulates once frequency control word K, and exports corresponding increase by N-bit register
One phase increment of step-length so that phase accumulator is output as the linear increment sequence with K as step-length, will be with K as step-length
Linear increment sequence store in wave memorizer；
S3 ripple signal) is obtained according to the sampling that to wave memorizer table look-up of ripple Wave data, and by ripple signal
The analog current signal I that D/A is converted to assigned frequency is carried out by D/A modular converters0。
As shown in figure 3, step S3) when ripple signal being carried out into D/A changing, specifically refer to receive and sent from host computer
Synchronous trigger pulse, often receives a synchronous trigger pulse and then triggers a trigger pulse to interrupt, while defeated by being set to PPS
The source of synchronising signal of exit pattern exports synchronizing signal to the control unit of each DC output unit, each DC output unit
Control unit catches the zero-acrross ing moment of output waveform using genlock mechanism, when capturing D/A modular converter output waveforms
Zero-acrross ing moment then triggers DAC zero passage to interrupt, then obtain adjacent trigger pulse interrupt, DAC zero passages interrupt between when
Between it is poor, and by the time difference input DDS digital frequency synthesizers obtain DAC frequency control signals, DAC frequency control signals is defeated
Enter the control end of D/A modular converters, the ripple signal of input is carried out D/A conversions, obtains assigned frequency by control D/A modular converters
Analog current signal I0.In the present embodiment, source of synchronising signal uses XL8061, and XL8061 is set into pulse per second (PPS) PPS
(Pulse Per Second) output mode, PPS outputs are connected on the synchronous input port of DC output unit.Using synchronization
Lock phase control scheme, using the capturing unit inside DSP, general purpose timer and comparing unit, realizes exporting main frame and slave
The capture of signal, reaches main frame and slave output signal with frequency with the purpose of phase, realizes the synchronization of current output sources.The present embodiment
The D.C. high-current standard source output intent confluxed based on parallel connection using genlock mechanism, when catching the zero passage of output waveform
Carve, remain zero-acrross ing moment and zero cross fired impulsive synchronization, synchronous error is less than 4us, is generally kept in 1us or so.
The control unit of the present embodiment each DC output unit catches the zero passage of output waveform using genlock mechanism
Moment, when the zero-acrross ing moment for capturing D/A modular converter output waveforms then triggers a DAC zero passage to interrupt, so that each
The output of DC output unit can realize synchronism output under synchronous trigger pulse, it is remained and zero cross fired pulse
It is synchronous.The phase-locked function is the frequency trim mechanism by DDS digital frequency synthesizers to be realized, can be by finely tuning DDS numbers
The frequency of word frequency synthesizer come control D/A change speed, D/A conversion output speed change actually just changes output wave
The frequency of shape such that it is able to realize the synchronized tracking to external sync trigger pulse.System triggers arteries and veins by zero passage interruption logging
Punching and the moment of D/A modular converter zero passages, the defeated of DDS digital frequency synthesizers is adjusted by comparing the difference of zero-acrross ing moment
Go out, the output of DDS digital frequency synthesizers adjusts the defeated of DDS digital frequency synthesizers as the output clock of D/A modular converters
Go out just adjust the zero-acrross ing moment of D/A modular converters, until D/A modular converters zero-acrross ing moment and trigger pulse arrival when
Carve basic synchronization.Regulation process locks phase using PID regulative modes, allows the rate-adaptive pacemaker moment of system to track upper trigger signal.
Because interrupt response time is uncertain, in the case of modification of program or different control panels, may all cause to interrupt and ring
Difference between seasonable, in order to accurate compensation due to the different caused lock phase errors of interrupt response, on the software of host computer
It is provided with trigger delay compensation to set, manually can gives an offset before dispatching from the factory to adjust final synchronous error.
As shown in figure 4, the D.C. high-current standard source output device confluxed based on parallel connection of the present embodiment includes host computer 1
With more than two DC output units 2, DC output unit 2 include control unit 21, ripple output module 22, error amplify
Device 23, current amplification standard source 24 and direct current transducer 25, control unit 21 are connected with host computer 1 respectively, control unit 21
Output end is connected with ripple output module 22, the input all the way of error amplifier 23 and the output end phase of ripple output module 22
Even, another road input is connected with the output end of direct current transducer 25, the output end and current amplification standard of error amplifier 23
Source 24 is connected, and the input of direct current transducer 25 is connected with the output end of current amplification standard source 24, and all direct current output lists
As D.C. high-current standard source output terminal after the output end parallel connection of the current amplification standard source 24 of unit 2.The present embodiment based on
The D.C. high-current standard source output device that parallel connection is confluxed is controlled by host computer 1 to DC output unit 2, host computer 1
It is connected with DC output unit 2 through Serial Port Line, output valve is set at the end of host computer 1, by the completely the same driving numeral of two-way
Signal drives the control unit 21 of DC output unit 2 to send signal output instruction, under the Synchronization Control of control unit 21, leads to
Cross the output ripple of ripple output module 22, then carried out after closed loop feedback regulation by current amplification standard source by error amplifier 23
24 output DC currents, obtain distortionless high-precision linear high current after D.C. high-current parallel connection is confluxed.
Referring to Fig. 4, the present embodiment specifically includes two DC output units 2, when required output current is larger, by two
The Parallel opertation of platform DC output unit 2, when in parallel one as main frame, one, as slave, and is controlled by host computer 1
System, host computer 1 is connected through serial ports with main frame, slave, and two electric currents of equipment are exported and together, anode and anode together, are born
End and negative terminal together, are connected in tested load.Main frame, the control unit 21 of slave export dispersion number according to current setting value size
Word signal is to ripple output module 22, the ripple letter obtained after carrying out ripple synthesis and digital-to-analogue conversion through ripple output module 22
Number, ripple signal input current power amplifier standard source 24 after the closed-loop control of error amplifier 23 enters through current amplification standard source 24
Row power amplification simultaneously couples output constant current source.Meanwhile, (the Zero flux current sense of direct current transducer 25 is equipped with analog circuit
Device), the output end current value I of measurement current amplification standard source 24x, IxError amplifier 23 is fed back to, into error amplifier 23
Measured value Ix and user's setting value I0It is compared, the difference compared according to both adjusts the output valve of actual source, protecting
The output valve moment in card source is consistent with setting value, it is ensured that the load regulation in source controls within ± 0.05%RD (to load from sky
It is loaded onto fully loaded).Current amplification standard source can produce each range DC current, design current amount by mV grades of small voltage signal
Cheng Wei：0.2A, 1A, 5A, 10A, 30A, 60A, 120A, 300A, using parallel connection conflux output when, exportable 600A, it is allowed to each amount
Journey maximum overshoot 120%, stability：0.01%/3min.
As shown in figure 4, control unit 21 includes microprocessor 211 and communication interface 212, microprocessor 211 is by communication
Interface 212 is connected with host computer, and ripple output module 22 is connected with the output end of microprocessor 211.
As shown in figure 4, control unit 21 also includes display 213 and Keysheet module 214, display 213, Keysheet module
214 are connected with microprocessor 211 respectively.
As shown in figure 4, control unit 21 also includes Pulse sampling device 215, the output end and microprocessor of Pulse sampling device 215
Device 211 is connected, and can be used to gather the active infrared pulse of tested direct current energy meter, realizes direct current energy meter error testing.
Ripple output module 22 carries out discrete signal fitting and realizes that ripple is exported using DSP+DAC in the present embodiment.Such as Fig. 5
It is shown, ripple output module 22 include dsp processor 221, N adder 222, N-bit register 223, wave memorizer 224,
D/A modular converters 225 and reference clock module 226, dsp processor 221 are connected with microprocessor 211, N adder 222, N
Both bit registers 223 concatenation forms phase accumulator, the output end of dsp processor 221 and the input of phase accumulator, N
The output of bit register 223 is connected with the address wire of wave memorizer 224, the ripple Wave data output of dsp processor 221
End, the output end of reference clock module 226 are connected with wave memorizer 224 jointly, the input difference of D/A modular converters 225
It is connected with wave memorizer 224, reference clock module 226, dsp processor 221 tabled look-up to wave memorizer 224, depositing
Storage signal sampling value of binary coded value form in wave memorizer 224 is found and obtains ripple signal, and by ripple signal
The analog current signal that D/A is converted to assigned frequency, the output of D/A modular converters 225 are carried out by D/A modular converters 225
End is connected with error amplifier 23.According to Fourier transformation theorem, any periodic signal for meeting Dirichlet condition can
A series of sinusoidal or cosine signal sums are decomposed into, and according to nyquist sampling theorem, when sampling frequency is more than or waits
When the twice of analog signal highest frequency, the discrete series that can be obtained by sampling recovers original analog without distortions.
Each harmonic content harmonic phase value is set by input through keyboard in the software interface of host computer 1, using DC digital frequency
Synthetic technology, obtains corresponding discrete digital signal sequence and is stored in wave memorizer 224, and wave memorizer 224 is exported
Discrete digital signal deliver to D/A modular converters 225, dsp processor 221 is tabled look-up to wave memorizer 224, storage is existed
The signal sampling value of binary coded value form is found and obtains ripple signal in wave memorizer 224, and ripple signal is passed through
D/A modular converters 225 carry out the analog current signal that D/A is converted to assigned frequency, so as to synthesize ripple signal, so that
To the precision current source comprising each harmonic content harmonic phase value.Main frame and the DC current of slave output in the present embodiment
After confluxing through parallel connection, to corresponding equipment under test, 2 times of electromechanical stream, defeated by many direct currents based on the current value of final output for output
Go out the output of the sync of unit 2, exportable bigger DC current.In the present embodiment, dsp processor 221 uses 32 bit DSPs,
D/A modular converters 225 are used and double 16 DAC, under dsp processor 221 and the control of adjustable reference clock module 226, by
Waveform synthetic circuit output digit signals, obtain the high-precision analog with certain amplitude of continuous low distortion after being converted through D/A
DC current signal.
Operationally, each harmonic content harmonic phase value is set beforehand through host computer 1, host computer 1 is by setting value
Serial No. is sent to the microprocessor 211 of main frame and slave, and microprocessor 211 sends to dsp processor data message
221, after being processed through dsp processor 221, ripple Wave data is exported to wave memorizer 224 and is stored, it is simultaneously emitted by frequency control
Word K processed, K are binary-coded phase increment values, used as the input of phase accumulator.Phase accumulator is by N adder
222nd, the cascade of N-bit register 223 is formed, and the output of N-bit register 223 is fed back to the N input of adder 222 and realized by it
Cumulative function.In each clock pulses fc, phase accumulator accumulates once frequency word K, the output phase of phase accumulator
A phase increment for step-length should be increased, the output data of phase accumulator is substantially the linear increment sequence with K as step-length,
It reflects the phase information of composite signal.The output of phase accumulator is connected with the address wire of wave memorizer 224, at DSP
Reason device 221 is tabled look-up to wave memorizer 224, signal sampling value (binary coding of the storage in wave memorizer 224
Value) find.In the presence of system clock pulse, phase accumulator ceaselessly adds up, i.e., do not stop to table look-up.Wave memorizer 224
Output data be sent to D/A converter 225, the wave-shape amplitude value of digital quantity form is converted into certain frequency by D/A converter 225
Analog signal, waveform is recombined out.
The present embodiment is based on the D.C. high-current standard source output device for confluxing in parallel to be had high precision, exports big, weight
Gently, it is easy to the characteristics of carrying, and disclosure satisfy that the calibrating requirement to DC ammeter, meets State Grid Corporation of China's company standard
Q/GDW1826-201《Direct-current electric energy meter calibrating device technical specification》And national metrological verification regulations JJG 842《Direct current energy meter
Vertification regulation》Requirement.The major function that the present embodiment is based on the D.C. high-current standard source output device for confluxing in parallel has：1、
It is that 0.1 grade and its metering of above DC current are provided and traced to the source.2nd, high-precision DC current is exported, precision is better than 0.05%.3、
Can be used as single standard dc source, can individually export the DC current of 0~600A.4th, for direct current table calibration, mould
Intend DC charging process.5th, electric automobile charging pile constant-current charge is simulated.The present embodiment is based on the D.C. high-current for confluxing in parallel
The important technological parameters of standard source output device are：Current range：0.2A、1A、5A、10A、30A、60A、120A、300A、
600A；Range of current output：0~600A；Precision：0.05RD%；Stability：0.01%；Port voltage：Maximum 3V；Load is adjusted
Whole rate：0.01%；Operating voltage：AC 220V ± 5%, 50Hz ± 5%；Operating temperature：- 10 DEG C~55 DEG C；Relative temperature：≤
85%；Machine volume：830mm×630mm×600mm；The type of cooling：Air blast cooling；Liquid crystal display：800×600.
In use, the present invention can be with power supply, rectification based on the D.C. high-current standard source output device for confluxing in parallel
Module, power amplifier, control module, DC current output are integrated, the need for meeting laboratory verification and on-site proving.
For example, using pulse frequency multiplication mode, realizing direct current energy meter error testing.Intrusion Detection based on host and slave output current are simultaneously
The technology export DC current that connection confluxes, the DC voltage that main frame output sets to tested direct current energy meter.By current sense
The output electricity of device and the precision resistance potential-divider network measurement present invention based on the D.C. high-current standard source output device for confluxing in parallel
Stream and voltage, through high-speed data acquisition chip and analog-to-digital conversion module, are converted to discrete digital signal, and send extremely by measured value
DSP power generation module computings obtain main frame power output, and above procedure is equivalent to constituting a high-precision standard electric energy
Table.Meanwhile, the collection of the Pulse sampling device 215 active infrared pulse of tested direct current energy meter of main frame configuration, due to flowing through main frame
Standard scale electric current only has the 1/2 of the tested meter electric current of inflow, the active power that Framework computing is obtained is multiplied by into 2, with tested electric energy
Apparent power is compared, and obtains tested direct current energy Watch Error；Scaling down processing is carried out to acquisition pulse, realizes that direct current energy is showed
Field virtual load error testing.
For example, using pulse frequency multiplication mode, realizing direct current energy meter error testing.As shown in fig. 6, realizing direct current energy
It is otherwise varied in the division of labor between main frame and slave when Watch Error is tested, and DC output unit 2 on main frame employs one
Control unit 21 shares two sets of equipment of rear end, and the equipment of a set of rear end is using the classical knot of DC output unit 2 shown in Fig. 4
Structure, including ripple output module 22, error amplifier 23, current amplification standard source 24 and direct current transducer 25；Another set of rear end
Equipment include ripple output module 22, error amplifier 23, voltage power amplifier standard source and voltage sensor, voltage sensor adopts
The voltage of collecting voltage power amplifier standard source output terminal and as error amplifier 23 closed loop be input into；Slave is then using shown in Fig. 4
The classical architecture of DC output unit 2.The electricity of the output of current amplification standard source 24 of the voltage, main frame of the output of voltage power amplifier standard source
Stream, the electric current three of the output of current amplification standard source 24 of slave are together respectively exported voltage or electric current to tested direct current energy
Table, and the electric current and power production module that the voltage of voltage power amplifier standard source output, the current amplification standard source 24 of main frame are exported
Input be connected, the output end of power production module is connected with an input of application condition module, application condition module
Another input be then connected with tested direct current energy meter by Pulse sampling device.Referring to Fig. 6, operationally, microprocessor
211 dsp processors 221 for sending output magnitude signal to ripple output module 22, it is determined that the size of output value digital quantity, by
The signal source of dsp processor 221 and the grade of D/A converter 225 circuit composition exports an analog quantity U for fractional value0Put to error
Big device 23, DC voltage is exported through voltage power amplifier standard source, while voltage sensor is used as DC voltage measurement module, is measured defeated
Go out voltage and scaled to Ux, by UxError amplifier 23 is fed back to, with analog quantity U0By subtraction (Ux-U0) after
To voltage difference delta U, voltage difference delta U is exported to voltage power amplifier standard source, the output of voltage measurement module as voltage compensation part
Amount and voltage power amplifier standard source output quantity into fixed proportion.The dsp processor 221 of main frame is storage in wave memorizer 224
Electric current, voltage data stamp markers by clock module, obtain voltage power amplifier standard source output voltage u (j), the electricity of main frame
Electric current i (j) of the output of stream power amplifier standard source 24, voltage u (j), the current amplification standard of main frame of the output of voltage power amplifier standard source
Electric current i (j) of the output of source 24 is sent to power generation module, and power generation module corresponds voltage u (j), electric current i (j)
It is multiplied, is obtained discrete power data sequence P0, because main frame output current is the half of input direct-current electric energy table electric current,
From formula (1), the power that main frame computing is obtained is the 1/2 of tested direct current energy apparent power.Therefore main engine power generation module
By P02 times are multiplied by, are changed into 2P0After export.
In formula (1), W represents power, and u (j) represents voltage, the i of the voltage power amplifier standard source output that jth time sampling is obtained
J () represents the electric current of the output of current amplification standard source 24 of the main frame that jth time sampling is obtained, N represents the quantity of sampled data, Δ
T represents the sampling interval.Application condition module is relatively tested direct current energy meter power P x and 2 times of main engine power 2P0, application condition mould
Block and it is non-immediate power is compared, but compare within the unit interval, both measure the size of electricity.The microprocessor of main frame
The active pulse of the external tested electric energy meter of the collection of Pulse sampling device 215 of device 211, in two pulse spacing T times of collection, quilt
Survey direct current energy meter to have good luck as shown in formula (2), standard direct current energy meter is had good luck as shown in formula (3)；
In formula (2) and formula (3), WxRepresent that tested direct current energy meter is had good luck, W0Expression standard direct current energy meter is had good luck, Px generations
The tested direct current energy apparent power of table, P0 represents main engine power, and Δ t1 represents host voltage, current sample time interval, Δ t2 tables
Show tested direct current energy meter voltage, current sample time interval, T is two pulse spacings.Application condition module is counted according to formula (4)
Calculation obtains tested direct current energy Watch Error, and the mode of the tested table multiple pulse of collection can be calculated and more accurately be tested direct current
Can Watch Error.
η=(Wx-W0)/W0× 100% (4)
In formula (4), WxRepresent that tested direct current energy meter is had good luck, W0Expression standard direct current energy meter is had good luck, and η represents tested straight
Stream electric energy meter error.
The above is only the preferred embodiment of the present invention, and protection scope of the present invention is not limited merely to above-mentioned implementation
Example, all technical schemes belonged under thinking of the present invention belong to protection scope of the present invention.It should be pointed out that for the art
Those of ordinary skill for, some improvements and modifications without departing from the principles of the present invention, these improvements and modifications
Should be regarded as protection scope of the present invention.
Claims (9)
1. a kind of D.C. high-current standard source output intent confluxed based on parallel connection, it is characterised in that implementation steps include：
1) it is in advance that each is in parallel for exporting the output end of the DC output unit of DC current, it is straight to each by host computer
Stream output unit sends synchronous trigger pulse come whether signal output between judging each DC output unit is synchronous, if respectively
Signal output is asynchronous between individual DC output unit, redirects execution step 1)；Otherwise, execution step 2 is redirected)；
2) electric current output order is sent to each DC output unit by host computer；
3) each DC output unit parsing electric current output order obtains each harmonic content harmony wave phase of electric current to be generated
Value, the analog current signal I of assigned frequency is generated according to each harmonic content harmonic phase value0；Each direct current output
Current output DC current is sampled and reduces specified multiple and obtains sample rate current I by unitx, by sample rate current IxWith simulation electricity
Stream signal I0Make the difference and obtain current compensation part Δ I, by current compensation part Δ I input current power amplifier standard sources, by electric current
Power amplifier standard source obtains the output DC current of each DC output unit；
4) the output DC current parallel connection of each DC output unit is confluxed output.
2. according to claim 1 based on the D.C. high-current standard source output intent for confluxing in parallel, it is characterised in that step
1) detailed step includes：
1.1) synchronous trigger pulse is sent to each DC output unit by host computer, each DC output unit output current
While, start rolling counters forward；
1.2) it is straight to each by host computer while each DC output unit stops output current after specifying the time
Stream output unit sends synchronous trigger pulse again, and each DC output unit counter respectively under lock-out pulse triggering
Stop timing；
1.3) specify a DC output unit as main frame, remaining DC output unit as slave, main frame, slave are counted
Numerical value subtracts each other, if subtracting each other result is all higher than predetermined threshold value, signal output is asynchronous between judging each DC output unit,
Redirect execution step 1)；Otherwise judge signal output synchronization between each DC output unit, redirect execution step 2).
3. according to claim 1 based on the D.C. high-current standard source output intent for confluxing in parallel, it is characterised in that step
3) analog current signal I is generated according to each harmonic content harmonic phase value in0Detailed step include：
S1 each harmonic content harmonic phase value) is generated into ripple Wave data；Meanwhile, frequency control word K is sent as phase
The input of bit accumulator, the phase accumulator is made up of N adder and N-bit register cascade, and the frequency control word K is
Binary-coded phase increment value；
S2) output of N-bit register is fed back to the N input of adder and realizes cumulative function by phase accumulator, every
One clock pulses fc, N adder accumulates once frequency control word K, and exports corresponding increase by by N-bit register
The phase increment of step-length so that phase accumulator is output as the linear increment sequence with K as step-length, will be described with K as step-length
Linear increment sequence store in wave memorizer；
S3 ripple signal) is obtained according to the sampling that to the wave memorizer table look-up of ripple Wave data, and by ripple signal
The analog current signal I that D/A is converted to assigned frequency is carried out by D/A modular converters0。
4. according to claim 3 based on the D.C. high-current standard source output intent for confluxing in parallel, it is characterised in that step
When ripple signal S3) being carried out into D/A conversions, specifically refer to receive the synchronous trigger pulse sent from host computer, often receive one
Individual synchronous trigger pulse then triggers trigger pulse to interrupt, at the same by be set to the source of synchronising signal of PPS output modes to
The control unit output synchronizing signal of each DC output unit, the control unit of each DC output unit uses genlock
Mechanism catches the zero-acrross ing moment of output waveform, when the zero-acrross ing moment for capturing D/A modular converter output waveforms then triggers a DAC
Zero passage is interrupted, and then obtains the time difference between adjacent trigger pulse interruption, the interruption of DAC zero passages, and the time difference is input into
DDS digital frequency synthesizers obtain DAC frequency control signals, and the DAC frequency control signals are input into the control of D/A modular converters
The ripple signal of input is carried out D/A conversions by end processed, control D/A modular converters, obtains the analog current signal I of assigned frequency0。
5. a kind of D.C. high-current standard source output device confluxed based on parallel connection, it is characterised in that：Including host computer (1) and two
It is individual more than DC output unit (2), the DC output unit (2) including control unit (21), ripple output module (22),
Error amplifier (23), current amplification standard source (24) and direct current transducer (25), described control unit (21) respectively with it is upper
Machine (1) is connected, and the output end of described control unit (21) is connected with ripple output module (22), the error amplifier (23)
All the way input be connected with the output end of ripple output module (22), the output end of another road input and direct current transducer (25)
It is connected, the output end of the error amplifier (23) is connected with current amplification standard source (24), the direct current transducer (25)
Input is connected with the output end of current amplification standard source (24), and all DC output units (2) current amplification standard source
(24) as D.C. high-current standard source output terminal after output end parallel connection.
6. the D.C. high-current standard source output device confluxed based on parallel connection according to claim 5, it is characterised in that：Institute
Stating control unit (21) includes microprocessor (211) and communication interface (212), and the microprocessor (211) is by communication interface
(212) it is connected with host computer, the ripple output module (22) is connected with the output end of microprocessor (211).
7. the D.C. high-current standard source output device confluxed based on parallel connection according to claim 5, it is characterised in that：Institute
Stating control unit (21) also includes display (213) and Keysheet module (214), the display (213), Keysheet module (214)
It is connected with microprocessor (211) respectively.
8. the D.C. high-current standard source output device confluxed based on parallel connection according to claim 5, it is characterised in that：Institute
Stating control unit (21) also includes Pulse sampling device (215), the output end and microprocessor of the Pulse sampling device (215)
(211) it is connected.
9. the D.C. high-current standard source output device confluxed based on parallel connection according to claim 5, it is characterised in that：Institute
Stating ripple output module (22) includes dsp processor (221), N adder (222), N-bit register (223), wave memorizer
(224), D/A modular converters (225) and reference clock module (226), the dsp processor (221) and microprocessor (211) phase
Even, both the N adder (222), N-bit register (223) concatenation form phase accumulator, the dsp processor (221)
Output end and phase accumulator input, the output of the N-bit register (223) and the address of wave memorizer (224)
Line be connected, the ripple Wave data output end of the dsp processor (221), the output end of reference clock module (226) jointly with
Wave memorizer (224) is connected, the input of the D/A modular converters (225) respectively with wave memorizer (224), with reference to when
Clock module (226) is connected, and the dsp processor (221) tabled look-up to wave memorizer (224), storing in Waveform storage
The signal sampling value of binary coded value form is found and obtains ripple signal in device (224), and ripple signal is changed by D/A
Module (225) carries out the analog current signal that D/A is converted to assigned frequency, the output end of the D/A modular converters (225) and
Error amplifier (23) is connected.
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