CN106653709A - 封装件及其制造方法 - Google Patents

封装件及其制造方法 Download PDF

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CN106653709A
CN106653709A CN201611256483.7A CN201611256483A CN106653709A CN 106653709 A CN106653709 A CN 106653709A CN 201611256483 A CN201611256483 A CN 201611256483A CN 106653709 A CN106653709 A CN 106653709A
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chip
wiring layer
metal column
layer
packaging part
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马慧舒
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Samsung Semiconductor China R&D Co Ltd
Samsung Electronics Co Ltd
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Samsung Semiconductor China R&D Co Ltd
Samsung Electronics Co Ltd
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Priority to CN201611256483.7A priority Critical patent/CN106653709A/zh
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Abstract

本发明提供了一种封装件及其制造方法。所述封装件包括：第一再布线层；第一芯片，位于第一再布线层上并且电连接到第一再布线层；第二芯片，位于第一芯片上；第二再布线层，位于第二芯片上方并且与第二芯片电连接；塑封层，将第一芯片和第二芯片密封；其中，第一再布线层与第二再布线层之间设置有第一金属柱，第一再布线层与第二再布线层通过第一金属柱电连接，第一芯片和第二芯片之间设置有绝缘粘合层，第二芯片和第二再布线层之间设置有第二金属柱，第一芯片和第二芯片通过第一再布线层、第一金属柱、第二再布线层和第二金属柱电连接。

Description

封装件及其制造方法
技术领域
本发明涉及一种封装件及其制造方法，更具体地，涉及一种包含两个再布线层的封装件及其制造方法。
背景技术
堆叠封装(Package on Package，POP)可以通过将两个或更多个封装件彼此堆叠，将其组合成单个封装结构来减小集成电路所需的***电路板面积，从而实现更大的集成电路密度和更大的封装密度。然而，POP封装结构由于其顶部封装件的热膨胀系数(CTE)高且底部封装件的热膨胀系数低而可能发生翘曲，因此可能导致POP封装结构失效或性能降低等。
晶圆级封装(Wafer Level Package，WLP)是对整片晶圆进行封装测试后再切割成单个成品芯片，因此又可称为圆片级-芯片尺寸封装(WLP-CSP)。晶圆级封装可以实现高度微型化，器件成本随着器件尺寸的减小和晶圆尺寸的增大而显著降低。但是由于采用晶圆级芯片尺寸封装技术封装后的芯片功能较为单一，需要封装后另外加上***电路来实现完整的***功能。
发明内容
为了解决上述问题，本申请采用***级封装(System in a Package，SIP)将包括应用处理器、存储器等多种功能芯片集成在一个封装结构内，同时满足应用处理器(AP)所需要的小迹线间距(trace pitch)和存储器所需要的大迹线间距，工艺简单、成本低、封装件薄。
本发明提供了一种封装件，所述封装件可以包括：第一再布线层；第一芯片，位于第一再布线层上并且电连接到第一再布线层；第二芯片，位于第一芯片上；第二再布线层，位于第二芯片上方并且与第二芯片电连接；塑封层，将第一芯片和第二芯片密封；其中，第一再布线层与第二再布线层之间设置有第一金属柱，第一再布线层与第二再布线层通过第一金属柱电连接，第一芯片和第二芯片之间设置有绝缘粘合层，第二芯片和第二再布线层之间设置有第二金属柱，第一芯片和第二芯片通过第一再布线层、第一金属柱、第二再布线层和第二金属柱电连接。
根据本发明的示例性实施例，连接第一再布线层和第二再布线层的第一金属柱可以穿透塑封层。
根据本发明的示例性实施例，所述封装件还可以包括将第一再布线层与外部连接的焊球。
根据本发明的示例性实施例，第一芯片可以通过焊料凸起与第一再布线层电连接。
根据本发明的示例性实施例，第二芯片可以设置为多个。
根据本发明的示例性实施例，第一芯片与第二芯片的类型可以不同和/或尺寸可以不同。
本发明提供了一种制造封装件的方法，所述方法可以包括以下工艺：
(1)在载板上设置第一再布线层，第一再布线层包括第一介电层和第一金属线，第一介电层具有暴露第一金属线的开口；
(2)将第一芯片附着到设置有第一再布线层的载板上，第一芯片通过焊料凸起与第一再布线层电连接；
(3)在第一芯片上设置第二芯片，第二芯片与第一芯片之间设置有绝缘粘合层；
(4)在第一再布线层上设置第一金属柱，在第二芯片上设置第二金属柱；
(5)使用塑封层将第一芯片、第二芯片、第一再布线层、第一金属柱和第二金属柱密封，并且对塑封层进行蚀刻，从而暴露第一金属柱和第二金属柱；
(6)在暴露的第一金属柱和第二金属柱的上表面上设置第二再布线层，使第二芯片通过第二金属柱、第二再布线层和第一金属柱电连接到第一再布线层，第二再布线层包括第二介电层和第二金属线。
根据本发明的示例性实施例，所述方法还可以包括通过蚀刻去除载板以暴露第一再布线层，并且在第一再布线层的暴露的表面上设置焊球。
根据本发明的示例性实施例，第二芯片可以设置为多个。
根据本发明的示例性实施例，第一芯片与第二芯片的类型可以不同和/或尺寸可以不同。
附图说明
通过下面结合附图进行的描述，本发明的上述和其他目的和特点将会变得更加清楚，其中：
图1是示出根据本发明的示例性实施例的封装件的剖视图；
图2至图9是示出制造根据本发明的示例性实施例的封装件的方法的剖视图；
图10是示出传统POP封装结构的剖视图。
具体实施方式
在下文中将参照附图更充分地描述本发明构思，附图中示出了本发明的实施例。然而，本发明可以以许多不同形式实施并且不应该解释为受限于这里阐述的实施例。相反，提供这些实施例使得本公开将是彻底的和完整的，并且将本发明的范围充分地传达给本领域的技术人员。在附图中，为了清楚，层和区域的尺寸和相对尺寸可以被夸大。附图本质上也是示意性的。在整个附图中，同样的附图标记表示同样的元件。
在这里所使用的术语是仅用于描述具体实施例的目的并且不意图限制本发明。如在这里所使用的，除非上下文另有清楚地指示，否则单数形式“一个”、“一种”、“该”和“所述”也意图包括复数形式。还将理解的是，当在本说明书中使用术语“包括”和/或“包含”时，说明存在陈述的特征、区域、整体、步骤、操作、元件和/或组件，但是不排除存在或添加一个或更多个其他的特征、区域、整体、步骤、操作、元件、组件和/或它们的组。
现在将在下文中参照附图更充分地描述本发明。
图1是示出根据本发明的示例性实施例的封装件10的剖视图。
参照图1，根据示例性实施例的封装件10包括第一芯片140和第二芯片160、第一再布线层和第二再布线层以及塑封层190。
在根据示例性实施例的封装件10中，第一芯片140可以是应用处理器(AP)，第二芯片160可以是存储器，但是本示例性实施例不限于此。第一芯片140和第二芯片160的类型可以相同，也可以不同。第二芯片160堆叠在第一芯片140上，它们之间设置有绝缘粘合层150。尽管图1中示出了一个第二芯片160设置在第一芯片140上，但是本发明不限于此，可以将多个第二芯片设置在第一芯片上。
第一再布线层设置在第一芯片140的下方，通过焊料凸起130与第一芯片140电连接。第一再布线层包括第一金属线110和位于第一金属线110上的第一介电层120。第一金属线110的材料可以包括铜、铝、镍、金、银、钛中的一种或其组合。第一介电层120的材料可以包括环氧树脂、硅胶、PI、PBO、BCB、氧化硅、磷硅玻璃以及含氟玻璃中的至少一种，但是本发明不限于此。第一介电层120具有暴露第一金属线110的开口OP。
第二再布线层设置在第二芯片160的上方，通过第二金属柱200与第二芯片160电连接。第二再布线层包括第二金属线210和位于第二金属线210上的第二介电层220。第二金属线210可以包括铜、铝、镍、金、银、钛中的一种或其组合。第二介电层220可以包括环氧树脂、硅胶、PI、PBO、BCB、氧化硅、磷硅玻璃以及含氟玻璃中的至少一种，但是本发明不限于此。
塑封层190将第一芯片140和第二芯片160塑封在其内部。塑封层190可以一次模塑成型，并且可以包括甲基丙烯酸甲酯-苯乙烯共聚物、酚醛环氧树脂、甲酚甲醛环氧树脂、溴化酚醛环氧树脂等中的任意一种或几种，但本发明中形成塑封层的材料不限于此。
第一再布线层和第二再布线层之间可以设置有第一金属柱180，第一金属柱穿透塑封层190，第一再布线层和第二再布线层通过第一金属柱180电连接。因此，第一芯片140和第二芯片160可以通过第一再布线层和第二再布线层以及焊料凸起130、第一金属柱180和第二金属柱200彼此电连接。
第一再布线层的下表面上可以设置有多个焊球230，以与外部装置连接。焊球可以设置在金属柱180正下方。
尽管在图中示出了第二芯片通过金属柱与第二再布线电连接，但是根据本发明的示例性实施例，第二芯片可以通过诸如焊料凸起等与第二再布线电连接。
图2至图9是示出制造根据本发明的示例性实施例的封装件的方法的剖视图。
参照图2，在诸如硅的载板100上设置第一再布线层。第一再布线层包括第一金属线110和第一介电层120，第一介电层120设置在第一金属线110上。在第一介电层120上设置暴露第一金属线110的多个开口OP。第一介电层120的材料可以包括环氧树脂、硅胶、PI、PBO、BCB、氧化硅、磷硅玻璃以及含氟玻璃中的至少一种，但是本发明不限于此。第一金属线110的材料可以包括铜、铝、镍、金、银、钛中的一种或其组合。
参照图3，采用倒装芯片方法将第一芯片140附着到设置有第一再布线层的载板100上。将焊料凸起130设置在第一芯片140与第一再布线层之间，即，将焊料凸起130设置在第一介电层120的开口OP中，使得第一芯片140通过焊料凸起130与第一再布线层电连接。第一芯片140可以是应用处理器，但本发明不限于此。
如图4所示，通过使用绝缘粘合层150将第二芯片160附着到第一芯片140上。第二芯片160的尺寸可以比第一芯片140的尺寸小。第二芯片160可以设置为多个，并且可以是存储器，但本发明不限于此。
参照图5，分别在第一再布线层和第二芯片160上设置第一金属柱180和第二金属柱200。第一金属柱180和第二金属柱200可以是诸如铜柱、铜螺柱等的导电材料。第一金属柱180设置在第一金属线110上，第一金属柱180通过第一介电层120中的开口OP与第一金属线110电连接。第二金属柱200与焊料凸起170对应地设置在第二芯片160上。
参照图6，可以通过模塑成型形成塑封层190，从而密封第一芯片140、第二芯片160、第一金属柱180和第二金属柱200。在第一芯片140与第一再布线层之间也设置有塑封层190。塑封层190可以一次模塑成型，并且可以包括甲基丙烯酸甲酯-苯乙烯共聚物、酚醛环氧树脂、甲酚甲醛环氧树脂、溴化酚醛环氧树脂等中的任意一种或几种，但本发明中形成塑封层的材料不限于此。
参照图7，对塑封层190进行蚀刻以暴露第一金属柱180和第二金属柱200。如图8所示，在塑封层190的上表面上设置第二再布线层。第二再布线层包括第二金属线210和第二介电层220。第二再布线层与第一金属柱180和第二金属柱200接触，从而第二再布线层和第一再布线层可以通过第一金属柱180电连接，第二芯片160可以通过第二金属柱200与第二再布线层电连接。第二芯片160还可以通过第二金属柱200、第二再布线层、第一金属柱180、第一再布线层和焊料凸起130与第一芯片140电连接。第二介电层220设置在第二金属线210上，并且第二介电层220可以是与第一介电层120相同的材料。
如图9所示，通过蚀刻去掉载板100，使得第一再布线层暴露。在第一再布线层下表面上设置多个焊球230，以使第一再布线110可以通过焊球230电连接到外部。
图10是示出传统POP封装结构20的剖视图。根据图10可以得知，POP封装结构20可以包括第一封装件和第二封装件，第一封装件可以是应用处理器，第二封装件可以是存储器。第二封装件堆叠在第一封装件上方，第一封装件和第二封装件通过焊球彼此电连接。在封装结构20中，第一封装件是扇出晶圆级封装结构，第二封装件是细间距球栅阵列(FBGA)封装结构。
如图1所示的根据本发明的示例性实施例的封装结构10可以是扇出晶圆级结构，利用两个再布线层将第一芯片140和第二芯片160共同封装在一个封装件中，与图10中的封装结构20相比，工艺简单、成本低、厚度较小、热膨胀系数低，从而可以改善封装结构的翘曲等问题。并且，封装件10可以同时满足存储器所需要的大的迹线间距(例如，5μm)和应用处理器所需要的小的迹线间距(例如，2μm)。因此随着小型化、薄膜化以及低成本化的发展趋势，如图1所示出的封装结构越来越受到广泛应用。
虽然已经参照本发明的示例性实施例具体地示出并描述了本发明，但是本领域普通技术人员将理解，在不脱离如所附权利要求和它们的等同物所限定的本发明的精神和范围的情况下，可以在此做出形式和细节上的各种改变。应当仅仅在描述性的意义上而不是出于限制的目的来考虑实施例。因此，本发明的范围不是由本发明的具体实施方式来限定，而是由权利要求书来限定，该范围内的所有差异将被解释为包括在本发明中。

Claims (10)

1.一种封装件，其特征在于，所述封装件包括：
第一再布线层；
第一芯片，位于第一再布线层上并且电连接到第一再布线层；
第二芯片，位于第一芯片上；
第二再布线层，位于第二芯片上方并且与第二芯片电连接；
塑封层，将第一芯片和第二芯片密封；
其中，第一再布线层与第二再布线层之间设置有第一金属柱，第一再布线层与第二再布线层通过第一金属柱电连接，第一芯片和第二芯片之间设置有绝缘粘合层，第二芯片和第二再布线层之间设置有第二金属柱，第一芯片和第二芯片通过第一再布线层、第一金属柱、第二再布线层和第二金属柱电连接。
2.根据权利要求1所述的封装件，其特征在于，连接第一再布线层和第二再布线层的第一金属柱穿透塑封层。
3.根据权利要求1所述的封装件，其特征在于，所述封装件还包括将第一再布线层与外部连接的焊球。
4.根据权利要求1所述的封装件，其特征在于，第一芯片通过焊料凸起与第一再布线层电连接。
5.根据权利要求1所述的封装件，其特征在于，第二芯片设置为多个。
6.根据权利要求1所述的封装件，其特征在于，第一芯片与第二芯片的类型不同和/或尺寸不同。
7.一种制造封装件的方法，其特征在于，所述方法包括以下工艺：
(1)在载板上设置第一再布线层，第一再布线层包括第一介电层和第一金属线，第一介电层具有暴露第一金属线的开口；
(2)将第一芯片附着到设置有第一再布线层的载板上，第一芯片通过焊料凸起与第一再布线层电连接；
(3)在第一芯片上设置第二芯片，第二芯片与第一芯片之间设置有绝缘粘合层；
(4)在第一再布线层上设置第一金属柱，在第二芯片上设置第二金属柱；
(5)使用塑封层将第一芯片、第二芯片、第一再布线层、第一金属柱和第二金属柱密封，并且对塑封层进行蚀刻，从而暴露第一金属柱和第二金属柱；
(6)在暴露的第一金属柱和第二金属柱的上表面上设置第二再布线层，使第二芯片通过第二金属柱、第二再布线层和第一金属柱电连接到第一再布线层，第二再布线层包括第二介电层和第二金属线。
8.根据权利要求7所述的制造封装件的方法，其特征在于，所述方法还包括通过蚀刻去除载板以暴露第一再布线层，并且在第一再布线层的暴露的表面上设置焊球。
9.根据权利要求7所述的制造封装件的方法，其特征在于，第二芯片设置为多个。
10.根据权利要求7所述的制造封装件的方法，其特征在于，第一芯片与第二芯片的类型不同和/或尺寸不同。
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