CN106611788B - 半导体结构的形成方法 - Google Patents

半导体结构的形成方法 Download PDF

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Publication number
CN106611788B
CN106611788B CN201510702088.6A CN201510702088A CN106611788B CN 106611788 B CN106611788 B CN 106611788B CN 201510702088 A CN201510702088 A CN 201510702088A CN 106611788 B CN106611788 B CN 106611788B
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dielectric layer
layer
annealing
gate dielectric
semiconductor structure
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CN106611788A (zh
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李勇
洪中山
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201510702088.6A priority Critical patent/CN106611788B/zh
Priority to US15/275,111 priority patent/US9984882B2/en
Priority to EP16194581.1A priority patent/EP3163627A1/en
Publication of CN106611788A publication Critical patent/CN106611788A/zh
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Abstract

一种半导体结构的形成方法，包括：提供基底；在所述基底表面形成界面层；对所述界面层进行第一退火处理，所述第一退火处理在含氮氛围下进行，使界面层表面形成含氮层；在所述含氮层表面形成高k栅介质层；对所述高k栅介质层进行第二退火处理，使含氮层中的氮离子扩散至高k栅介质层内；在所述高k栅介质层表面形成栅电极层。本发明改善高k栅介质层的介电弛豫问题，从而提高形成的半导体结构的电学性能。

Description

半导体结构的形成方法
技术领域
本发明涉及半导体制造技术领域，特别涉及一种半导体结构的形成方法。
背景技术
集成电路尤其超大规模集成电路的主要半导体器件是金属-氧化物-半导体场效应管(MOS晶体管)。随着集成电路制作技术的不断发展，半导体器件技术节点不断减小，半导体结构的几何尺寸遵循摩尔定律不断缩小。当半导体结构尺寸减小到一定程度时，各种因为半导体结构的物理极限所带来的二级效应相继出现，半导体结构的特征尺寸按比例缩小变得越来越困难。其中，在半导体制作领域，最具挑战性的是如何解决半导体结构漏电流大的问题。半导体结构的漏电流大，主要是由传统栅介质层厚度不断减小所引起的。
当前提出的解决方法是，采用高k栅介质材料代替传统的二氧化硅栅介质材料，并使用金属作为栅电极，以避免高k材料与传统栅电极材料发生费米能级钉扎效应以及硼渗透效应。高k金属栅的引入，减小了半导体结构的漏电流。
尽管高k金属栅极的引入能够在一定程度上改善半导体结构的电学性能，但是现有技术形成的半导体结构的电学性能仍有待提高。
发明内容
本发明解决的问题是提高一种半导体结构的形成方法，改善半导体结构的电学性能。
为解决上述问题，本发明提供一种半导体结构的形成方法，包括：提供基底；在所述基底表面形成界面层；对所述界面层进行第一退火处理，所述第一退火处理在含氮氛围下进行，使界面层表面形成含氮层；在所述含氮层表面形成高k栅介质层；对所述高k栅介质层进行第二退火处理，使含氮层中的氮离子扩散至高k栅介质层内；在所述高k栅介质层表面形成栅电极层。
可选的，所述第二退火处理适于减少高k栅介质层中的氧空位含量。
可选的，所述界面层的材料为氧化硅或氮氧化硅；所述高k栅介质层的材料为HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO2或Al2O3。
可选的，所述第一退火处理采用的气体包括NH3。
可选的，所述第一退火处理还在含氟或氢中的一种或两种氛围下进行。
可选的，所述第一退火处理采用的气体还包括NF3或H2。
可选的，所述第一退火处理的工艺参数包括：退火温度为400摄氏度至1100摄氏度，腔室压强为1托至1标准大气压，处理时长为10分钟至120分钟。
可选的，在进行所述第一退火处理之前，所述界面层内含有未成键的硅离子和未成键的氧离子，所述第一退火处理还适于钝化所述未成键的硅离子和未成键的氧离子。
可选的，所述第二退火处理的工艺参数包括：退火温度为400摄氏度至1100摄氏度，腔室压强为1托至1标准大气压，处理时长为10分钟至120分钟。
可选的，在形成所述界面层之前，还包括步骤：在所述基底表面形成伪栅；在所述伪栅两侧的基底内形成源漏区；在所述伪栅两侧的基底表面形成层间介质层，所述层间介质层覆盖伪栅侧壁；刻蚀去除所述伪栅，暴露出基底表面。
可选的，所述界面层位于基底整个表面，还包括步骤：图形化所述栅电极层以及高k栅介质层，形成栅极结构；在所述栅极结构两侧的基底内形成源漏区；在所述栅极结构两侧的基底表面形成层间介质层，所述层间介质层覆盖栅极结构侧壁。
本发明还提供一种半导体结构的形成方法，包括：提供基底；在所述基底表面形成界面层；在所述界面层表面形成高k栅介质层；对所述高k栅介质层和界面层进行第一退火处理，所述第一退火处理在含氮氛围下进行，使氮离子扩散至高k栅介质层内；在所述高k栅介质层表面形成栅电极层。
可选的，所述第一退火处理适于减少高k栅介质层内的氧空位含量。
可选的，所述界面层的材料为氧化硅或氮氧化硅；所述高k栅介质层的材料为HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO2或Al2O3。
可选的，所述第一退火处理采用的气体包括NH3。
可选的，所述第一退火处理还在含氟或氢中的一种或两种氛围下进行。
可选的，所述第一退火处理采用的气体包括NF3或H2。
可选的，所述第一退火处理的工艺参数包括：退火温度为400摄氏度至1000摄氏度，腔室压强为1托至1标准大气压，退火时长为10分钟至120分钟。
可选的，所述界面层内含有未成键的氧离子，在所述第一退火处理过程中，所述未成键的氧离子扩散至高k栅介质层内。
可选的，在形成所述界面层之前，还包括步骤：在所述基底部分表面形成伪栅；在所述伪栅两侧的基底内形成源漏区；在所述伪栅两侧的基底表面形成层间介质层；刻蚀去除所述伪栅，暴露出基底表面。
与现有技术相比，本发明的技术方案具有以下优点：
本发明提供的半导体结构的形成方法的技术方案中，在形成界面层之后对界面层进行第一退火处理，所述第一退火处理在含氮氛围下进行，从而使得界面层表面形成含氮层，所述第一退火处理还能够钝化界面层内未成键的硅离子和氧离子，改善界面层的性能；接着，在含氮层表面形成高k栅介质层，对所述高k栅介质层进行第二退火处理，使得含氮层中的氮离子扩散至高k栅介质层，扩散至高k栅介质层内的氮离子能够钝化高k栅介质层内的氧空位，从而减少高k栅介质层内氧空位含量，改善高k栅介质层的介电弛豫问题，进而改善半导体结构的电学性能，如正偏压-温度不稳定特性和负偏压-温度不稳定特性得到改善。
进一步，所述第一退火处理还在含氟或氢中的一种或两种氛围下进行，从而使得含氮层中还含有氟离子或氢离子，在后续第二退火处理过程中所述氟离子或氢离子扩散进入高k栅介质层内，能够进一步起到钝化高k栅介质层内氧空位的作用。
本发明还提供一种半导体结构的形成方法的技术方案，在形成界面层之后，在所述界面层表面形成高k栅介质层；接着，对所述高k栅介质层和界面层进行第一退火处理，所述第一退火处理在含氮氛围下进行，使氮离子扩散至高k栅介质层内。其中，在第一退火处理过程中，界面层内未成键的氧离子扩散至高k栅介质层内，起到减少高k栅介质层内氧空位的作用，并且，所述第一退火处理过程中，氮离子扩散至高k栅介质层内，所述氮离子起到钝化高k栅介质层内氧空位的作用，从而进一步减小高k栅介质层内氧空位，改善高k栅介质层的介电弛豫问题，进而提高形成的半导体结构的电学性能。
附图说明
图1至图8是本发明一实施例提供的半导体结构形成过程的剖面结构示意图；
图9至图11为本发明另一实施例提供的半导体结构形成过程的剖面结构示意图。
具体实施方式
如背景技术所述，现有技术形成的半导体结构的电学性能有待提高。
经研究发现，尽管采用高k栅介质材料作为栅介质层的材料，在一定程度上能够改善半导体结构的电学性能，例如，半导体结构中的漏电流(leakage current)减小，然而，半导体结构中的弛豫电流(DR Current，Dielectric Relaxation Current)仍然较大，造成半导体结构的电学性能差，例如，半导体结构的正偏压-温度不稳定特性(PBTI，PositiveBiase Temperature Instability)和负偏压-温度不稳定特性(NBTI，Negative BiaseTemperature Instability)显著。进一步研究发现，导致半导体结构中弛豫电流大的原因包括：高k栅介质材料中具有缺陷，进而导致在高k栅介质材料中产生电子陷阱(electrontraps)，导致高k栅介质材料的介电弛豫效应显著，造成高k栅介质材料具有较大损耗角。
进一步分析发现，高k栅介质材料中的缺陷主要包括氧空位(Oxygen Vacancy)，若能够减少高k栅介质材料中氧空位含量，则能显著改善半导体结构的电学性能。
为解决上述问题，本发明提供一种半导体结构的形成方法，包括：提供基底；在所述基底表面形成界面层；对所述界面层进行第一退火处理，所述第一退火处理在含氮氛围下进行，使界面层表面形成含氮层；在所述含氮层表面形成高k栅介质层；对所述高k栅介质层进行第二退火处理，使含氮层中的氮离子扩散至高k栅介质层内；在所述高k栅介质层表面形成栅电极层。本发明中由于含氮层中的氮离子扩散至高k栅介质层内，所述氮离子能够钝化高k栅介质层内的氧空位，从而改善高k栅介质层的介电弛豫特性，减小半导体结构的弛豫电流，改善形成的半导体结构的电学性能。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1至图8为本发明一实施例提供的半导体形成过程的剖面结构示意图。
参考图1，提供基底101；在所述基底101表面形成伪栅102。
所述基底101的材料为硅、锗、锗化硅、碳化硅、砷化镓或镓化铟，所述基底101还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底。本实施例中，所述基底101的材料为硅。
所述基底101内还形成有隔离结构(未图示)，所述隔离结构用于电隔离相邻有源区(AA，Active Area)。
所述伪栅102替后续形成的栅极结构占据空间位置。所述伪栅102的材料为氧化硅、多晶硅、氮化硅、氮氧化硅、碳化硅、碳氮化硅、碳氮氧化硅或非晶碳。本实施例中，所述伪栅102的材料为多晶硅，为了避免后续刻蚀去除伪栅102的工艺对基底101造成过刻蚀，所述伪栅102与基底101之间还能够形成氧化层。
在一个实施例中，形成所述伪栅102的工艺步骤包括：在所述基底101表面形成伪栅膜；图形化所述伪栅膜，去除位于部分基底101表面的伪栅膜，形成所述伪栅102。本实施例中，所述伪栅102侧壁表面还形成有侧墙(未标示)，所述侧墙的材料为氮化硅。
在形成所述伪栅102之后，还包括步骤：在所述伪栅102两侧的基底101内形成源漏区。在一个实施例中，形成的半导体结构为PMOS器件，所述源漏区的掺杂离子为P型离子，例如为B、Ga或In。在另一实施例中，形成的半导体结构为NMOS器件，所述源漏区的掺杂离子为N型离子，例如为P、As或Sb。
在其他实施例中，形成的半导体结构为鳍式场效应管，所述基底包括：衬底、以及位于衬底表面的若干分立的鳍部、位于衬底表面的隔离层，其中，所述隔离层覆盖鳍部的部分侧壁表面，且所述隔离层顶部低于鳍部顶部。相应的，所述伪栅位于部分隔离层表面，且所述伪栅横跨所述鳍部，覆盖鳍部的部分顶部表面和侧壁表面，所述源漏区位于伪栅两侧的鳍部内。
参考图2，在所述伪栅102两侧的基底101表面形成层间介质层103，所述层间介质层103覆盖伪栅102侧壁。
所述层间介质层103顶部与伪栅102顶部齐平。形成所述层间介质层103的工艺步骤包括：在所述伪栅102两侧的基底101表面形成层间介质膜，所述层间介质膜覆盖伪栅102的顶部表面和侧壁表面，且所述层间介质膜顶部高于伪栅102顶部；去除高于伪栅102顶部的层间介质膜，形成所述层间介质层103。
所述层间介质层103的材料为氧化硅、氮化硅、氮氧化硅或碳氮氧化硅。本实施例中，所述层间介质层103的材料与伪栅102的材料不同，层间介质层103的材料为氧化硅。
参考图3，刻蚀去除所述伪栅102(参考图2)，暴露出基底101表面。
本实施例中，采用干法刻蚀工艺，刻蚀去除所述伪栅102，所述干法刻蚀工艺对伪栅102的刻蚀速率大于对层间介质层103的刻蚀速率。
参考图4，在所述基底101表面形成界面层104。
本实施例中，所述界面层104位于基底101部分表面，在所述暴露出的基底101表面形成界面层104。一方面，所述界面层104作为栅极结构的一部分，与后续形成的高k栅介质层构成的叠层结构作为栅介质层；另一方面，所述界面层104为后续形成高k栅介质层提供良好的界面基础，从而提高形成的高k栅介质层的质量，且避免高k栅介质层与基底101直接接触造成的不良影响。
所述界面层104的材料为氧化硅、氮化硅或碳氮氧化硅；采用化学气相沉积、物理气相沉积或原子层沉积工艺形成所述界面层104，还能够采用氧化工艺形成所述界面层104。
本实施例中，所述界面层104的材料为氧化硅。为了提高界面层104与基底101之间的界面性能，采用热氧化(thermal oxidation)工艺，在所述基底101表面形成界面层104，其中，热氧化工艺为干氧氧化或湿氧氧化。在采用热氧化工艺形成所述界面层104的工艺过程中，向反应腔室内通入氧源，为了降低热氧化工艺对基底101的氧化速率，还能够向反应腔室内通入硅源。
在一个具体实施例中，采用热氧化工艺形成所述界面层104的工艺参数包括：提供氧化气体，所述氧化气体包括O2、H2O、NO或N2O，氧化气体流量为10sccm至100sccm，腔室温度为500摄氏度至850摄氏度。
参考图5，对所述界面层进行第一退火处理105，所述第一退火处理105在含氮氛围下进行，使界面层104表面形成含氮层106。
在进行第一退火处理105之前，所述界面层104中具有未成键的硅离子和未成键的氧离子，因此界面层104的性能较差，例如界面层104的电绝缘性能和致密性差。所述第一退火处理105有利于钝化所述未成键的硅离子和未成键的氧离子，所述未成键的硅离子、未成键的氧离子进行化学键重组，从而改善界面层104的性能，提高界面层104的绝缘性和致密性。
其次，由于第一退火处理105在含氮氛围下进行，所述含氮氛围中的氮离子与界面层104表面的硅离子以及氧离子相结合，从而在界面层104表面形成含氮层106，在对后续形成的高k栅介质层进行第二退火处理时，所述含氮层106中的氮离子向高k栅介质层内扩散，从而起到钝化高k栅介质层中氧空位的作用，减少高k栅介质层内的氧空位含量。
所述第一退火处理105采用的气体包括NH3。本实施例中，所述第一退火处理105的工艺参数包括：退火温度为400摄氏度至1100摄氏度，腔室压强为1托至1标准大气压，退火时长为10分钟至120分钟。采用本实施例提供的第一退火处理105工艺参数，能够避免氮离子扩散进入基底101内，且避免由于退火温度过高造成的源漏区掺杂离子二次扩散的问题；同时，本实施例中退火温度以及腔室压强适中，使得界面层104的性能得到明显改善，并且保证含氮层106中具有较多的氮离子含量，进而在后续起到减小高k栅介质层中氧空位的作用。
在其他实施例中，所述第一退火处理除在含氮氛围下进行以外，所述第一退火处理还在含氟或氢中的一种或两种氛围下进行，相应的，所述含氮层中还含有氟离子或氢离子中的一种或两种，所述第一退火处理采用的气体还包括NF3或H2。具体的，在一个实施例中，所述第一退火处理在含氮和氟氛围下进行，所述第一退火处理采用的气体包括NH3和NF3；在另一实施例中，所述第一退火处理在含氮和氢氛围下进行，所述第一退火处理采用的气体包括NH3和H2；在又一实施例中，所述第一退火处理在含氮、氢和氟氛围下进行，所述第一退火处理采用的气体包括NH3、NF3和HF。
参考图6，在所述含氮层106表面形成高k栅介质层107。
所述高k栅介质层107的材料为高k栅介质材料，其中，高k栅介质材料指的是，相对介电常数大于氧化硅相对介电常数的栅介质材料，所述高k栅介质层107的材料为HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO2或Al2O3。
采用化学气相沉积、物理气相沉积或原子层沉积工艺形成所述高k栅介质层107。本实施例中，所述高k栅介质层107的材料为HfO2，采用化学气相沉积工艺形成所述高k栅介质层107。
参考图7，对所述高k栅介质层107进行第二退火处理108，使含氮层106中的氮离子扩散至高k栅介质层107内。
所述第二退火处理108能够提高高k栅介质层107的致密度，提高高k栅介质层107材料的相对介电常数。
所述第二退火处理108还适于减少高k栅介质层107内的氧空位含量。由于高k栅介质材料大多为离子晶体，每一个金属离子都与氧离子有较多的键存在，当氧离子缺失时则易形成氧空位，所述氧空位在高k栅介质材料的禁带中央引入了带隙态，成为导电机制中的缺陷能级；若直接以所述高k栅介质层107作为栅极结构中栅介质层一部分，则形成的半导体结构中介电弛豫问题显著。为此，本实施例对高k栅介质层107进行第二退火处理108，使得含氮层106中的氮离子扩散至高k栅介质层107内，氮离子进入氧空位取代了原来氧离子的作用，通过氮离子与高k栅介质层107中的金属离子之间轨道杂化。以高k栅介质层107的材料为HfO2为例，由于氮原子的电负性大于氧原子电负性，将原来Hf5d轨道上的带隙态推至HfO2的导带以下，从而钝化HfO2中的氧空位，进而改善高k栅介质层107的介电弛豫问题，改善半导体结构的正偏压-温度不稳定特性和负偏压-温度不稳定特性。
本实施例中，所述第二退火处理的工艺参数包括：退火温度为400摄氏度至1100摄氏度，腔室压强为1托至1标准大气压，处理时长为10分钟至120分钟。在第二退火处理过程中，所述含氮层106中的氮离子扩散至高k栅介质层107内，且避免所述氮离子扩散至基底101内，避免了沟道区造成不必要的掺杂。
在其他实施例中，所述含氮层中含有氟离子或氢离子时，在第二退火处理过程中，所述含氮层中的氟离子或氢离子扩散至高k栅介质层内，能够进一步起到钝化氧空位的作用。
在后续形成栅电极层之前，还能够在高k栅介质层107表面形成盖层，所述盖层能够阻挡后续形成的栅电极层内的金属离子扩散高k栅介质层107内。
参考图8，在所述高k栅介质层107表面形成栅电极层109。
本实施例中，所述栅电极层109顶部与层间介质层103顶部齐平；在形成所述栅电极层109的过程中，还去除高于层间介质层103顶部的高k栅介质层107。在一个具体实施例中，形成所述栅电极层109的工艺步骤包括：在所述高k栅介质层107表面形成栅电极膜，所述栅电极膜顶部高于层间介质层103顶部；研磨去除高于层间介质层103顶部的栅电极膜，形成所述栅电极层109；研磨去除所述高于层间介质层103顶部的高k栅介质层107。
所述栅电极层109为单层结构或叠层结构。本实施例中，所述栅电极层109包括：位于高k栅介质层107表面的功函数层以及位于功函数层表面的电极层，其中，所述电极层的材料包括Al、Cu、Ag、Au、Pt、Ni、Ti或W。
形成的半导体结构为NMOS器件时，所述功函数层的材料为N型功函数材料，包括TiAl、TaAlN、TiAlN、MoN、TaCN或AlN中的一种或几种；形成的半导体结构为PMOS器件时，所述功函数层的材料为P型功函数材料，包括Ta、TiN、TaN、TaSiN或TiSiN中的一种或几种。
在其他实施例中，所述栅电极层还能够为单层结构，栅电极层的材料包括Al、Cu、Ag、Au、Pt、Ni、Ti或W。
由于本实施例减少了高k栅介质层107中的氧空位含量，改善了高k栅介质层107的介电弛豫问题，从而减小了半导体结构的弛豫电流，因此本实施例能够改善半导体结构的正偏压温度不稳定特性和负偏压温度不稳定特性，提高半导体结构的电学性能。
需要说明的是，本实施例中，以后形成高k栅介质层后形成金属栅极(high k lastmetal gate last)的工艺为例。在其他实施例中，还能够采用先形成高k栅介质层后形成金属栅极(high k first metal gate last)的工艺，具体的，所述界面层位于基底整个表面，在所述高k栅介质层表面形成栅电极层之前，对高k栅介质层进行第二退火处理，接着，在所述高k栅介质层表面形成伪栅膜；图形化所述伪栅膜以及高k栅介质层，从而在图形化后的高k栅介质层表面形成伪栅；在所述伪栅两侧的基底内形成源漏区；在所述伪栅两侧的基底表面形成层间介质层，所述层间介质层覆盖伪栅侧壁；去除所述伪栅；在所述高k栅介质层表面形成栅电极层。
在另一实施例中，还能够采用先形成高k栅介质层先形成金属栅极(high k firstmetal gate first)的工艺。具体的，所述界面层位于基底整个表面，在对高k栅介质层进行第二退火处理之后，在所述高k栅介质层表面形成栅电极层；图形化所述栅电极层以及高k栅介质层，形成栅极结构；在所述栅极结构两侧的基底内形成源漏区；在所述栅极结构两侧的基底表面形成层间介质层，所述层间介质层覆盖栅极结构侧壁。
图9至图11为本发明另一实施例提供的半导体结构形成过程的剖面结构示意图。
参考图9，提供基底201；在所述基底201表面形成界面层204；在所述界面层204表面形成高k栅介质层207。
本实施例中，以后形成高k栅介质层后形成金属栅极为例，在形成所述界面层204之前，还包括步骤：在所述基底201部分表面形成伪栅；在所述伪栅两侧的基底201内形成源漏区；在所述基底201表面形成层间介质层203，所述层间介质层203覆盖伪栅侧壁表面；刻蚀去除所述伪栅，暴露出基底201表面；然后在所述暴露出的基底201表面形成界面层204。
本实施例中，所述高k栅介质层207还位于层间介质层203的顶部表面和侧壁表面。
有关基底201、界面层204、高k栅介质层207的材料和形成工艺可参考前述实施例的说明，在此不再赘述。
参考图10，对所述高k栅介质层207和界面层204进行第一退火处理205，所述第一退火处理205在含氮氛围下进行，使氮离子扩散至高k栅介质层207内。
所述第一退火处理205的作用包括：首先，所述第一退火处理205适于减少高k栅介质层207内的氧空位含量，所述第一退火处理205在含氮氛围下进行，使氮离子扩散至高k栅介质层内，减少高k栅介质层207内的氧空位含量，从而改善高k栅介质层207的介电弛豫问题。其次，所述第一退火处理205还能够提高高k栅介质层207的致密度，提高高k栅介质层207的相对介电常数。再次，所述第一退火处理205不仅能够改善界面层204的致密度，还能够使界面层204内未成键的氧离子扩散至高k栅介质层207内，所述未成键的氧离子占据氧空位位置，从而起到进一步钝化高k栅介质层207内氧空位的作用，进一步减少高k栅介质层207内氧空位含量。
所述第一退火处理205采用的气体包括NH3，所述第一退火处理205采用的气体还能够包括N2。本实施例中，所述第一退火处理205的工艺参数包括：退火温度为400摄氏度至1000摄氏度，腔室压强为1托至1标准大气压，退火时长为10分钟至120分钟。所述第一退火处理的退火温度适中，避免氮离子扩散进入基底201内，并且由于退火温度和腔室压强适中，能够有效的控制扩散进入高k栅介质层207内的氮离子含量，避免氮离子含量过大而导致高k栅介质层207的相对介电常数降低。
在其他实施例中，所述第一退火处理除在含氮氛围下进行外，所述第一退火处理还在含氟或氢中的一种或两种氛围下进行，所述第一退火处理采用的气体还包括NF3或HF中的一种或两种。在一个实施例中，所述第一退火处理在含氮和氟氛围下进行，第一退火处理采用的气体包括NH3和NF3，第一退火处理采用的气体还能够包括N2。在另一实施例中，所述第一退火处理在含氮、氢和氟氛围下进行，所述第一退火处理采用的气体包括NH3、NF3、N2和H2。
参考图11，在所述高k栅介质层207表面形成栅电极层209，且所述栅电极层209顶部与层间介质层203顶部齐平。
本实施例中，还去除高于层间介质层203顶部的高k栅介质层207。
有关栅电极层209的材料以及形成步骤可参考前述实施例的说明，在此不再赘述。
由于本实施例减少了高k栅介质层207中的氧空位含量，改善了高k栅介质层207的介电弛豫问题，从而减小了半导体结构的弛豫电流，因此本实施例能够改善半导体结构的正偏压温度不稳定特性和负偏压温度不稳定特性，提高半导体结构的电学性能。
需要说明的是，本实施例中，以后形成高k栅介质层后形成金属栅极(high k lastmetal gate last)的工艺为例。在其他实施例中，还能够采用先形成高k栅介质层后形成金属栅极(high k first metal gate last)的工艺，具体的，所述界面层位于基底整个表面，在所述高k栅介质层表面形成栅电极层之前，对所述高k栅介质层进行第一退火处理，接着，在所述高k栅介质层表面形成伪栅膜；图形化所述伪栅膜以及高k栅介质层，从而在图形化后的高k栅介质层表面形成伪栅；在所述伪栅两侧的基底内形成源漏区；在所述伪栅两侧的基底表面形成层间介质层；去除所述伪栅；在所述高k栅介质层表面形成栅电极层。
在另一实施例中，还能够采用先形成高k栅介质层先形成金属栅极(high k firstmetal gate first)的工艺。具体的，所述界面层位于基底整个表面，在对高k栅介质层进行第一退火处理之后，在所述高k栅介质层表面形成栅电极层；图形化所述栅电极层以及高k栅介质层，形成栅极结构；在所述栅极结构两侧的基底内形成源漏区；在所述栅极结构两侧的基底表面形成层间介质层。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (11)

1.一种半导体结构的形成方法，其特征在于，包括：
提供基底；
在所述基底表面形成界面层；
对所述界面层进行第一退火处理，所述第一退火处理在含氮氛围下进行，使界面层表面形成含氮层；
在所述含氮层表面形成高k栅介质层；
对所述高k栅介质层进行第二退火处理，使含氮层中的氮离子扩散至高k栅介质层内；
在所述高k栅介质层表面形成栅电极层。
2.如权利要求1所述半导体结构的形成方法，其特征在于，所述第二退火处理适于减少高k栅介质层中的氧空位含量。
3.如权利要求1所述半导体结构的形成方法，其特征在于，所述界面层的材料为氧化硅或氮氧化硅；所述高k栅介质层的材料为HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO2或Al2O3。
4.如权利要求1所述半导体结构的形成方法，其特征在于，所述第一退火处理采用的气体包括NH3。
5.如权利要求1所述半导体结构的形成方法，其特征在于，所述第一退火处理还在含氟或氢中的一种或两种氛围下进行。
6.如权利要求5所述半导体结构的形成方法，其特征在于，所述第一退火处理采用的气体还包括NF3或H2。
7.如权利要求1所述半导体结构的形成方法，其特征在于，所述第一退火处理的工艺参数包括：退火温度为400摄氏度至1100摄氏度，腔室压强为1托至1标准大气压，处理时长为10分钟至120分钟。
8.如权利要求1所述半导体结构的形成方法，其特征在于，在进行所述第一退火处理之前，所述界面层内含有未成键的硅离子和未成键的氧离子，所述第一退火处理还适于钝化所述未成键的硅离子和未成键的氧离子。
9.如权利要求1所述半导体结构的形成方法，其特征在于，所述第二退火处理的工艺参数包括：退火温度为400摄氏度至1100摄氏度，腔室压强为1托至1标准大气压，处理时长为10分钟至120分钟。
10.如权利要求1所述半导体结构的形成方法，其特征在于，在形成所述界面层之前，还包括步骤：在所述基底表面形成伪栅；在所述伪栅两侧的基底内形成源漏区；在所述伪栅两侧的基底表面形成层间介质层，所述层间介质层覆盖伪栅侧壁；刻蚀去除所述伪栅，暴露出基底表面。
11.如权利要求1所述半导体结构的形成方法，其特征在于，所述界面层位于基底整个表面，还包括步骤：图形化所述栅电极层以及高k栅介质层，形成栅极结构；在所述栅极结构两侧的基底内形成源漏区；在所述栅极结构两侧的基底表面形成层间介质层，所述层间介质层覆盖栅极结构侧壁。
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