TW444306B - Wafer-level package structure and method - Google Patents

Wafer-level package structure and method Download PDF

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Publication number
TW444306B
TW444306B TW088100968A TW88100968A TW444306B TW 444306 B TW444306 B TW 444306B TW 088100968 A TW088100968 A TW 088100968A TW 88100968 A TW88100968 A TW 88100968A TW 444306 B TW444306 B TW 444306B
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Taiwan
Prior art keywords
die
wafer
patent application
scope
item
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Application number
TW088100968A
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Chinese (zh)
Inventor
De-Sheng Yang
Kai-Guang He
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United Microelectronics Corp
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Priority to TW088100968A priority Critical patent/TW444306B/en
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Publication of TW444306B publication Critical patent/TW444306B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

There is provided a wafer-level package structure and method, which can apply to package at least two dies. The package dimension is almost equal to the total size of the dies. The method comprises: providing a first die and forming an insulating post after pad redistribution to avoid contaminating the solder ball region in the subsequent molding or coating process; next, providing a second die and adhering the first die to the second die by an insulating tape or non-conductive glue; performing a wire bonding process based on the second die so that the signals of the second die can be transmitted to the pad redistribution layer on the surface of the first die via the gold wire when being used; using molding or coating to protect the bonding wires and fix the first and second dies; and next, performing a ball mounting process on the first die to provide a path for electrically connecting to the external circuit or device.

Description

經濟部中央標隼局員工消費合作社印聚 Λ /1 Vi 42l6Uvf d〇c，帽 Γ^ϋ-6--^___. 五、發明説明（I ) * 本發明疋有關於一種半導體封裝結構，且特別是有關 於〜種晶圓層級封裝(Wafer-level Package)之結構與方法。 隨著半導體業的進展，許多相關技術也日新月異地不 斷演進中。就半導體成品製造而言，一般可分爲三個階段， 一爲半導體基底的形成，即磊晶技術部份；再則半導體元 件製造，諸如MOS製程、多重金屬內連線等；最後則是 封裝製程（Package)。然而現今所有電子產品之開發莫不朝 向輕、薄、短、小的目標發展，對於半導體來說即是提高 其積集度(Integration)，至於封裝技術方面，則有晶片尺寸 封裝（Chip Scale Package，CSp)、多晶片型封裝(Muhi_Chip Module，MCM)等封裝技術的提出。由於半導體製程技術 已發展至線寬0·18μηι的元件生產，在積集度提高上有許 多突破，因此如何開發出相對應之小體積封裝，以達到產 品縮小化的目的，便成爲現今重要課題。此外，不管在電 腦上或民生用品上之應用，爲了縮小產品體積及節省封裝 成本，將兩個或多個的晶片封裝在一起的多晶片型封裝， 將是未來的趨勢之.一。 多曰s片型4裝可以將處理器（pr〇cess〇r)晶片及記憶體 (memory)晶片，或者邏輯電路(L〇gic)晶片及記憶體晶片（包 括DRAM及Flash Memory)封裝在一起’不但可以降低成 本，縮小封裝體積，並可縮短訊號傳輸路徑，提高效能， 並可使不同製程之晶片，合爲一封裝中，而無需使用特殊 整合製程生產。多晶片型封裝可適用於各種功能及各種應 用頻率之多晶片系統，例如，丨，記憶體晶片及微處理器晶 _______ 3 本紙張尺度適用中國囤家橾牟（CNS > M规格（2丨〇>< π]公釐 II--^------<------、1T------"1 (請先閱讀背面之注意事項再填寫本頁) 1 . d c / 0 0 2 44. 1 . d c / 0 0 2 44. A7 B7 第8 Η ] 0 0 9 6 S號説明書修正Η ____ 五、發明說明（z) 片以及一些被動元件的組合；2.記憶體晶片以及邏輯電路 晶片的組合：以及類比晶片（Analog) ’邏輯電路晶片和記 憶體晶片（包括DRAM ' SRAM、Flash Memory)的組合等 等。 請參照第1圖，其所繪示爲一種習知雙晶片型封裝。 目前雙晶片或多晶片型封裝，通常會使用一承載器，以承 載晶片。圖中繪示出基材10，在10上製作有銅的圖案(Cu Pattem)12上，這些銅圖案上再藉由錫球14的形成，與外 界電性連接。常見的基材材料爲一聚亞醯胺層(Polymide)。 然後，將較大面積之晶粒i粘貼在基材1〇上’而在基材 10及晶粒JJ_之間，利用一絕緣層16加以絕緣。接著，在 較大面積之晶粒18上，形成一絕緣層20，然後再裝置一 較小面積之晶粒22。而在晶片18及22上，則以導線24 與基材10上的接點連接，形成電性導通。之後，再以樹 脂26將晶片1S及22包裝起來，而整個封裝與電路板的 電性連接可採用習知錫球格狀陣列封裝（Ball Grid Array, BGA)的方式，以錫球14與電路板上的接點接合。然而， 習知此種多晶片型封裝的缺點在於其晶片係並列於同一平 面’且其厚度大約爲1.4毫米左右，因此其封裝之體積較 大，且晶片間連接的訊號路徑較長。 爲了 IfS小多晶片型封裝的體積，種面對面（face to face)的多晶片型封裝方式曾揭露於美國專利第533 1235號 中。而此種習知多晶片型封裝的缺點在於：利用軟片自動 接合的封裝方式，還需透過導線架或其他載體與電路板接 4 本紙依尺S過用中囷圉豕標準（CNS)A4規格（210 X 297公釐 (請先閲讀背面之注意事項再填寫本頁) IK------ 訂---I I----線 經濟部智慧財產局員工消費合作杜印製 —4^46 05 A7 - M 42 i6(\vf,d〇t；/0〇g HM43 ㈣_—Β7 五、發明説明（今） S ’徒增訊號傳輸路徑；此外，封裝外之封裝材料（樹脂) 將使得封裝成品厚度及面積變大，降低其應用性，且亦會 造成散熱的阻礙，對於將來速度更快的高頻產品，必定影 響其效能。 本發明提供一種晶圓層級之晶片尺寸封裝，晶片與晶 片之間’以一絕緣膠帶或不導電粘膠相連，不但不需使用 承載器而有效地減少封裝所佔之體積，冏時，僅在晶片週 圍以壓模（Molding)或塗佈（Coating)方式，以及保護週圍部 分所形成的金線，使得封裝厚度幾乎與晶片的總厚度相 同’而封裝後成品之面積與較大晶片之面積相仿，因此， 整個封裝的體積大約等於與所封裝的晶片體積。 此外，上述的絕緣體，除在進行壓模或塗佈時，可以 緩衝壓模時，模具材料對晶粒表面所造成的壓力，或避免 塗佈時，污染晶粒表面之植球預定區域。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 晶片與晶片之間，以及晶片與外界的導通，可採三種 方式：1.大晶粒之訊號可經由打線或其他方式，經小晶粒 之銲墊重分佈層至錫球處通路；2.小晶粒本身訊號經銲墊 重分佈層至錫球通路；3.大晶粒訊號經打線或其他方式， 經銲墊重分佈層，與小晶粒導通。藉由此三種方式，可彈 性地增加記憶空間，或轉換產品功能。 本發明提出一種晶圓層級之晶片尺寸封裝的結構’包 括較大晶粒及一較小晶粒，大小晶粒藉由一絕緣膠帶或不 導電膠相連，在較小晶粒上，具有一銲墊重分佈層（Pad Redistribution)，以及一在銲墊重分佈層上的一絕緣體。絕 5 本紙張尺度適用中國國家標準（CNS) Α4规格（210Χ297公釐） 經濟部中央榡率局員工消費合作杜印製 ''1——__一— i、發明说明（1) 綠體外圍之銲墊上，具有金線連接到大晶粒之上表面，這 些導線是利用一模具或塗佈材料固定保護。而在銲墊上， 絕緣體所包圍的區域，則植有錫球，以供外界電路或元件 之連接或導通。 本發明又提出一種晶圓餍級之晶片尺寸封裝的形成方 法，首先，提供一面積較小之晶粒，對較小面積之晶粒進 行銲墊重新分佈，且在其表面上靠近週圍部分形成一絕緣 體。然後，利用絕緣膠帶或不導電膠將大小晶粒接合在一 起，利用打線方式，在小晶粒之表面，絕緣體之外圍，形 成金線，連接至大晶粒之表面。這些金線再經由壓模方式 或塗佈方式，予以固定及保護。接著，在小晶粒的表面上 進行植球。 爲讓本發明之上述和其他目的'特徵、和優點能更明 顯易懂’下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1圖所繪示爲一種習知多晶片型封裝。 第2A圖及第2B圖繪示出依照本發明之一較佳實施例 中’晶粒上銲墊重分佈之剖面示意圖。 第3A圖至第3C圖繪示出依據本發明所提供之一種封 裝方法及結構。 第4圖繪示出依據本發明所提供之另一種封裝方法及 結構。 本紙張尺度適用中國國家標準（CNS ) A4規格（2!〇X297公釐） (請先聞讀背面之注意事項再填寫本頁) -訂 A7 B7 五、發明説明（ς/ ) 圖示標號說明__ 10 :基材 12 *銅圖案 14 :錫球 16 :絕緣層 18 :較大面積之晶片 :絕緣層 2 2 :較小面積之晶片 24 :導線 26 :樹脂 200 :晶粒 202 :銲墊 204 •聚亞醒胺層 206 :介層窗 208 :銲墊重分佈層 208a/2〇8b/2〇8c :銅/鎳/金 21〇 :絕緣體 212 :錫球 2 14 金線 216 :植球預定區域 3〇〇 :晶圓 302 :晶粒 304 :切割線 306 :絕緣膠帶/不導電膠 308 :壓模材料 310 :銲墊 312 :塗佈材料 實施例 經濟部中央搮隼局員工消费合作社印製 本發明提供一種晶圓層級之晶片尺寸封裝的結構及方 法’其中，先提供一小晶粒，在進行封裝及結合另一晶粒 之前，先對此小晶粒進行銲墊重新分佈，亦即，對小晶粒 之輸入/輸出1/◦線路路徑，做一重新分佈。此一重新分步 之結構及步驟可參照第2A圖及第2B圖。 參考第2A圖，提供一晶圓，上面包括複數個晶粒200， 每一晶粒200至少包括一銲墊202，藉由介層窗206的形 成，得以與其他晶粒或外界電路及元件導通或連接。在晶 7 ]--1------- -------ΐτ------線：- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標率（CNS ) A4規格（2丨0X297公楚:)The Consumer Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs, Consumers' Cooperative Print Λ / 1 Vi 42l6Uvf doc, Cap Γ ^ ϋ-6-^ ___. V. Description of the Invention (I) * The present invention relates to a semiconductor packaging structure, and In particular, it is related to the structures and methods of wafer-level packages. With the progress of the semiconductor industry, many related technologies are constantly evolving. In terms of semiconductor finished product manufacturing, it can generally be divided into three stages. One is the formation of a semiconductor substrate, that is, the epitaxial technology part; the other is the manufacturing of semiconductor components, such as MOS processes, multiple metal interconnects, etc .; and finally, packaging. Process (Package). However, the development of all electronic products today is directed towards the goals of lightness, thinness, shortness, and smallness. For semiconductors, it is to increase their integration. As for packaging technology, there is Chip Scale Package. CSp), multi-chip package (Muhi_Chip Module, MCM) and other packaging technologies. Since the semiconductor process technology has developed to the production of line width of 0 · 18μηι, there are many breakthroughs in improving the accumulation. Therefore, how to develop a corresponding small volume package to achieve the purpose of product reduction has become an important issue today. . In addition, regardless of the application on computers or consumer products, in order to reduce product size and save packaging costs, multi-chip packaging that packages two or more chips together will be one of the future trends. More than s chip type 4 packs can package the processor chip and memory chip, or the logic circuit chip and memory chip (including DRAM and Flash Memory) together. 'Not only can reduce costs, reduce package size, but also shorten signal transmission paths, improve performance, and enable chips of different processes to be integrated into a package without the need for special integrated manufacturing processes. Multi-chip package can be applied to multi-chip systems with various functions and various application frequencies, such as 丨, memory chips and microprocessor crystals _______ 3 This paper size is applicable to Chinese stores (CNS > M specifications (2丨 〇 > < π] mmII-^ ------ < ------, 1T ------ " 1 (Please read the precautions on the back before filling in this (Page) 1. Dc / 0 0 2 44. 1. Dc / 0 0 2 44. A7 B7 No. 8 Η] 0 0 9 6 Revised instruction No. S Η __ 5. Description of the invention (z) and some passive components Combination; 2. Combination of memory chip and logic circuit chip: and the combination of analog chip (Analog) 'logic circuit chip and memory chip (including DRAM' SRAM, Flash Memory), etc. Please refer to Figure 1 and its location It is shown as a conventional dual-chip package. At present, a dual-chip or multi-chip package usually uses a carrier to carry the wafer. The substrate 10 is shown in the figure, and a copper pattern (Cu Pattem) 12, these copper patterns are then electrically connected to the outside by the formation of solder balls 14. A common substrate material is a polyimide layer ( Polymide). Then, a larger-area crystal grain i is pasted on the substrate 10, and between the substrate 10 and the crystal grain JJ_, an insulating layer 16 is used for insulation. On the grains 18, an insulating layer 20 is formed, and then a small-area crystal grain 22 is installed. On the wafers 18 and 22, wires 24 are connected to the contacts on the substrate 10 to form electrical conduction. Then, the chips 1S and 22 are packaged with resin 26, and the electrical connection between the entire package and the circuit board can be achieved by the conventional Ball Grid Array (BGA) method, with the solder ball 14 and the circuit board However, the disadvantage of this multi-chip package is that its chips are juxtaposed on the same plane and its thickness is about 1.4 millimeters, so its package size is large and the signals for chip-to-chip connections The path is long. For the small size of the IfS multi-chip package, a face-to-face multi-chip package has been disclosed in US Patent No. 533 1235. The disadvantages of this conventional multi-chip package are: Package using automatic chip bonding It also needs to be connected to the circuit board through a lead frame or other carrier. 4 This paper is used in accordance with the standard S (CNS) A4 specification (210 X 297 mm (please read the precautions on the back before filling this page) IK ------ Order --- I I ---- Printed by the consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs Du 4—46 05 A7-M 42 i6 (\ vf, d〇t; / 0〇 g HM43 ㈣_—Β7 V. Description of the invention (today) S 'Excessive signal transmission path; In addition, the packaging material (resin) outside the package will make the thickness and area of the packaged product larger, reducing its applicability, and it will also cause heat dissipation Obstacles to high-frequency products that will be faster in the future will definitely affect their performance. The present invention provides a wafer-level wafer-size package. The wafer-to-wafer is connected by an insulating tape or non-conductive adhesive, which not only does not need to use a carrier to effectively reduce the volume occupied by the package. The die is surrounded by molding or coating, and the gold wire formed around the chip is protected, so that the package thickness is almost the same as the total thickness of the chip. The area of the finished product after packaging is similar to that of a larger chip. Therefore, the volume of the entire package is approximately equal to the volume of the packaged wafer. In addition, the above-mentioned insulator can buffer the pressure caused by the mold material on the surface of the crystal grains during stamping or coating, or avoid contaminating the predetermined area of the planting balls on the surface of the crystal grains during coating. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). There are three ways to communicate between the chip and the chip and the outside world: 1. Large-grain signals can be transmitted through Wire bonding or other methods, via the redistribution layer of the small-grain pads to the vias of the solder ball; 2. Signals of the small grains via the pad redistribution layer to the solder ball vias; 3. Large-grain signals via the wire or other methods Through the redistribution layer of the bonding pad, it is connected with the small grains. In these three ways, you can flexibly increase memory space or switch product functions. The present invention proposes a wafer-level wafer-size package structure including a larger die and a smaller die. The small and large die are connected by an insulating tape or a non-conductive adhesive, and a solder is provided on the smaller die. Pad Redistribution, and an insulator on the pad redistribution layer. Absolute 5 This paper size applies Chinese National Standard (CNS) A4 specification (210 × 297 mm) Printed by the consumer cooperation of the Central Government Bureau of the Ministry of Economic Affairs `` 1 ——__ 一 — i. Description of the invention (1) Peripheral body The solder pads have gold wires connected to the upper surface of the large grains. These wires are fixed and protected by a mold or coating material. On the pad, the area surrounded by the insulator is implanted with solder balls to connect or conduct external circuits or components. The present invention also proposes a method for forming a wafer-size wafer-size package. First, a die with a smaller area is provided, and the die with a smaller area is redistributed, and formed on the surface near the surrounding part. An insulator. Then, use insulating tape or non-conductive adhesive to join the large and small grains together, and use wire bonding to form a gold wire on the surface of the small grains and the periphery of the insulator to connect to the surface of the large grains. These gold wires are fixed and protected by a stamping method or a coating method. Next, balling was performed on the surface of the small crystal grains. In order to make the features and advantages of the above and other objects of the present invention clearer and easier to understand, the preferred embodiments are described below in detail with the accompanying drawings as follows: Brief description of the drawings: It is shown as a conventional multi-chip type package. Figures 2A and 2B are schematic cross-sectional views showing the redistribution of pads on a die in accordance with a preferred embodiment of the present invention. Figures 3A to 3C illustrate a packaging method and structure provided according to the present invention. FIG. 4 illustrates another packaging method and structure provided by the present invention. This paper size applies to Chinese National Standard (CNS) A4 specification (2.0 × 297 mm) (please read the precautions on the back before filling out this page)-Order A7 B7 V. Description of invention (ς /) __ 10: Base material 12 * Copper pattern 14: Tin ball 16: Insulation layer 18: Larger area wafer: Insulation layer 2 2: Smaller area wafer 24: Wire 26: Resin 200: Die 202: Solder pad 204 Polyimide layer 206: Interlayer window 208: Pad redistribution layer 208a / 2〇8b / 2 0c: Copper / Ni / Gold 21: Insulator 212: Tin ball 2 14 Gold wire 216: Plant ball Planned area 300: wafer 302: die 304: cutting line 306: insulating tape / non-conductive adhesive 308: stamping material 310: solder pad 312: coating material example The present invention provides a wafer-level wafer-size package structure and method. Among them, a small die is provided first, and the pads are redistributed before packaging and combining with another die. That is, redistribution is made to the input / output 1 / ◦ line path of the small die. The structure and steps of this re-step can refer to FIG. 2A and FIG. 2B. Referring to FIG. 2A, a wafer is provided, which includes a plurality of dies 200, and each die 200 includes at least a bonding pad 202. Through the formation of an interlayer window 206, it is possible to conduct conduction with other dies or external circuits and components or connection. In the crystal 7]-1 ------- ------- ΐτ ------ line:-(Please read the precautions on the back before filling this page) This paper size is applicable to China Standard rate (CNS) A4 specifications (2 丨 0X297):

-42 1 6txv f.doc/OOS A7 B7 r^3-(rD~— 五、發明説明（ 經濟部十央標準局貝工消費合作社印犁 粒200表面形成有一層用以保護晶粒.200的聚亞醯胺層 204。然後，進行銲墊重新分佈，以在晶粒200上之聚亞 醯胺層204表面，形成一銲墊重分佈層208。通常，銲墊 重分佈層208包括一層以上的導體層，例如，如圖所示之 銅層208a，鎳層2〇8b，以及金層208c。然而，此一銲墊 重分佈層208之實際層數及組成導體材料仍需視實際應用 上，電路或元件之需求條件而定。接著，在銲墊重分佈層 208上，距離週圍的部分，形成一絕緣體210，其剖面形 狀如一絕緣柱，而材料可以是一絕緣膠帶（Tape)或其他非 金屬材質。絕緣體210可以在後續壓模步驟時，減低小晶 粒200所承受的壓模壓力，或是塗佈步驟中，防止塗佈材 料污染晶粒200上，植球預定區域216，亦即，晶粒200 表面，被絕緣體210包圍的區域。 接著’對晶圓進行晶粒切割（Sawing)，以分離個別的 晶粒200。在完成與另一晶粒之接合步驟之後，在小晶粒 2〇〇上之銲墊重分佈層2〇8，絕緣體210的外圍部分，利 用打線步驟或其他方式，形成連接另一晶粒之金屬線214， 例如’一金線’並在植球預定區216上，植入錫球212。 利用上述之銲墊重分佈步驟，打線步驟，以及植球步 驟’晶粒與晶粒之間，以及晶粒與外界電路或元件之間， 可以彈性地增加記億空間，或轉換產品功能。因此，本發 明所提供之封裝結構及方法，可應用於多種功能不同的元 件，例如，動態隨機存取記憶體（DRAM)、靜態隨機存取 記憶體（SRAM)、唯讀記憶體（ROM)、邏輯電路晶片 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標隼（CNS > A4規格（210X297公釐） 經濟部智慧財產局員工消费合作社印製 -4-44-3-Θ-5 4 2 1 61 w 4443 0 6 五、發明說明（Ί) (LOGIC)、快閃記憶體（Flash Memory)、特殊應用積體電 路(ASIC)或類比晶片（ANALOG)等各種積體電路晶片。 第3A圖至第3C圖例舉一本發明之較佳實施例，進-步介紹及解釋本發明。參考第3A圖，提供一晶圓，晶圓 上包括一些晶粒200。對晶片200的輸入及輸出線路（I/O) 進行銲墊重分佈，以在晶粒200上形成一銲墊重分佈層 2M，其步驟及詳細結構可參考第2A圖及第2B圖。在銲 墊重分佈層2M_±，靠近週圍部分，形成一絕緣體210。 接者，對晶圓進彳了晶粒分割，使晶粒200各自分離。 提供一晶圓300,晶圓300包括了一些由切割線304 分隔之晶粒302。在本實施例，晶粒302具有大於晶粒200 之表面。利用絕緣膠帶或不導電膠306，將晶粒200—— 粒著在晶粒3〇2之上，其中，與晶粒302接合之面爲不包 括靜墊重分佈層之面。然後，利用打線或其他方式，形成 金線214，以連接晶粒200及晶粒302。通常，在晶粒302 上包括一銲墊310(第3C圖），例如是鋁或其他金屬銲墊， 用以連接金線214。 接著’利用壓模方式或塗佈方式，在絕緣體210之外 圍的銲墊重分佈層208表面，以及晶粒302與晶粒200接 合面曝露的表面上，形成一壓模材料308，例如是樹脂 (Resin)。壓模材料308的形成，具有固定及保護金線的作 用。如第3B圖所示，曝露出銲墊重分佈層208被絕緣體 210包圍的區域，亦即預定的植球區216。 請參考第3B圖，在預定植球216植入錫球。然後， 9 本紙張尺度適用冢標準（CNS)A4規格<210x297公爱） (請先Μ讀背面之注意事項再填寫本頁) 裝---— — — — —訂·！--線 42 1 6Uvr.d〇c/0084,4430^__ A7 B7 經濟部中夾標準局—工消费合作社印装 五、發明説明（$ ) 沿著晶圓300上的切割線304,對晶圓300進行晶粒切割， 以形成如第3C圖所示之個別的封裝成品。 第4圖繪示出依據本發明之方法所形成之另一種封裝 結構’其形成步驟與上述方法相同，僅將壓模步驟以一塗 佈步驟取代，亦即在絕緣體210之外側，利用一塗佈材料 312 ’例如是一液態化合物固定保護之。 綜合以上所述，本發明提供了一種晶圓層級的晶片尺 寸封裝結構及方法，其中，封裝的面積僅等於較大晶粒的 表面積，此外，封裝的厚度幾乎等於或僅略爲大於晶片的 厚度和。 此外，本發明所提供的晶片尺寸封裝，由於採用背面 裸晶的封裝方式，可提高晶片的散熱效能，增加其散熱量。 而本發明所提供的封裝結構中，兩晶粒彼此之^的導 訊號導通，或者與外界之間的訊號導通，有三種方方、 1. 晶粒302可經由打線或其他方式，經銲墊重分佈層 208，將訊號導通至錫球212，而藉由錫球212與外界電路 或元件導通。 2. 晶粒200可經由銲墊重分佈層208直接連接錫球 212，而藉由錫球212與外界電路或元件導通。 3. 晶粒302經由打線或其他方式，經晶粒200之銲墊 重分佈層208，與晶粒200導通，再經由晶粒200之銲墊 重分佈層208連接錫球，而藉由錫球212與外界電路或元 件導通。 雖然本發明已以一較佳實施例揭露如上，然其並非闬 (請先閱讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家糯準（CNS ) A4規格（210X297公釐） l 4 4 32t3n6d,i /008 A7 B7 五、發明説明（q ) 以限定本發明1任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 〈請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貞工消費合作社印繁 本紙張尺度適用中國國家橾準（CNS)A4規格（210X297公釐}-42 1 6txv f.doc / OOS A7 B7 r ^ 3- (rD ~ — V. Description of the invention (The Shiyang Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives, the printed plough grain 200 has a layer formed on the surface to protect the grains. 200's Polyurethane layer 204. Then, pad redistribution is performed to form a pad redistribution layer 208 on the surface of the polyimide layer 204 on the die 200. Generally, the pad redistribution layer 208 includes more than one layer Conductor layers, such as copper layer 208a, nickel layer 208b, and gold layer 208c as shown in the figure. However, the actual number of layers of this pad redistribution layer 208 and the composition of the conductive material still depend on the actual application. Depending on the requirements of the circuit or component. Then, on the pad redistribution layer 208, an insulator 210 is formed at a distance from the surrounding area, and its cross-sectional shape is like an insulating pillar, and the material can be an insulating tape (Tape) or other Non-metallic material. The insulator 210 can reduce the die pressure on the small grains 200 during the subsequent stamping step, or prevent the coating material from contaminating the grains 200 during the coating step, and the planting ball predetermined area 216. That is, the surface of the die 200 is surrounded by the insulator 210 Then, 'Sawing' the wafer to separate the individual dies 200. After completing the bonding step with another die, the pad redistribution layer on the small dies 200 In 2008, a peripheral portion of the insulator 210 is formed with a wire bonding step or other methods to form a metal wire 214 connected to another die, such as a 'gold wire', and a solder ball 212 is implanted on the predetermined ball planting area 216. Use The above-mentioned pad redistribution step, wire bonding step, and ball-planting step 'between the die and the die, and between the die and the external circuit or component, can flexibly increase the memory space or change the product function. The packaging structure and method provided by the present invention can be applied to various components with different functions, such as dynamic random access memory (DRAM), static random access memory (SRAM), read-only memory (ROM), logic Circuit chip (please read the precautions on the back before filling this page) This paper size applies to Chinese national standard (CNS > A4 specification (210X297 mm) Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs-4-44-3 -Θ- 5 4 2 1 61 w 4443 0 6 V. Various kinds of integrated circuit chips such as LOGIC, flash memory, special application integrated circuit (ASIC) or analog chip (ANALOG). 3A to 3C illustrate a preferred embodiment of the present invention, and further introduces and explains the present invention. Referring to FIG. 3A, a wafer is provided, and the wafer includes some dies 200. Input to the wafer 200 And output lines (I / O) for pad redistribution to form a pad redistribution layer 2M on the die 200. For the steps and detailed structure, refer to FIG. 2A and FIG. 2B. An insulator 210 is formed on the pad redistribution layer 2M_ ± near the peripheral portion. Then, the wafer is subjected to die division to separate the die 200. A wafer 300 is provided, and the wafer 300 includes a plurality of dies 302 separated by dicing lines 304. In this embodiment, the die 302 has a surface larger than that of the die 200. Using an insulating tape or a non-conductive adhesive 306, the crystal grains 200—grains are deposited on the crystal grains 302. Among them, the surface bonded to the crystal grains 302 is the surface that does not include the static pad redistribution layer. Then, gold wires 214 are formed by wire bonding or other methods to connect the die 200 and the die 302. Generally, a die pad 302 (FIG. 3C) is included on the die 302, such as aluminum or other metal pads, for connecting the gold wires 214. Next, a stamping method or a coating method is used to form a stamping material 308 on the surface of the pad redistribution layer 208 on the periphery of the insulator 210 and the exposed surface of the joint surface of the die 302 and the die 200, such as resin. (Resin). The stamper material 308 is formed to have a role of fixing and protecting the gold wire. As shown in FIG. 3B, the area of the pad redistribution layer 208 surrounded by the insulator 210, that is, the predetermined ball-planting area 216 is exposed. Referring to FIG. 3B, a solder ball is implanted in the predetermined implant ball 216. Then, 9 paper sizes are applicable to the Toka Standard (CNS) A4 specification < 210x297 public love) (Please read the precautions on the back before filling out this page). Install ---— — — — — Order ·! --Line 42 1 6Uvr.d〇c / 0084,4430 ^ __ A7 B7 Printed by Zhongjia Standard Bureau of the Ministry of Economic Affairs-Industrial and Consumer Cooperatives. V. Description of the invention ($) Along the cutting line 304 on the wafer 300, The circle 300 is die-cut to form individual packaged products as shown in FIG. 3C. FIG. 4 shows another packaging structure formed according to the method of the present invention. Its formation steps are the same as the above method, and only the stamping step is replaced by a coating step, that is, a coating is used outside the insulator 210. The cloth material 312 'is, for example, a liquid compound fixed and protected. To sum up, the present invention provides a wafer-level wafer size package structure and method, in which the area of the package is only equal to the surface area of the larger die, and the thickness of the package is almost equal to or only slightly larger than the thickness of the wafer. with. In addition, the chip-size package provided by the present invention can improve the heat dissipation efficiency and increase the heat dissipation capacity of the chip due to the use of a bare die package on the backside. In the package structure provided by the present invention, there are three types of conduction signals between the two dies, or the signals between the two dies. 1. The die 302 can be connected by soldering or other methods. The redistribution layer 208 conducts the signal to the solder ball 212, and the solder ball 212 is connected to an external circuit or component. 2. The die 200 can be directly connected to the solder ball 212 through the solder pad redistribution layer 208, and the solder ball 212 can be connected to external circuits or components. 3. The die 302 is connected to the die 200 through the wire redistribution layer 208 of the die 200 via wire bonding or other methods, and then the solder ball is connected through the die redistribution layer 208 of the die 200, and the solder ball is connected by the solder ball. 212 is in conduction with external circuits or components. Although the present invention has been disclosed as above with a preferred embodiment, it is not 闬 (please read the precautions on the back before filling this page) The size of the paper is applicable to China National Wax Standard (CNS) A4 (210X297 mm) l 4 4 32t3n6d, i / 008 A7 B7 V. Description of the invention (q) To limit anyone skilled in the art of the present invention 1, without departing from the spirit and scope of the present invention, they can make some changes and retouches. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling out this page) Printed and printed by Zhengong Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210X297 mm)

Claims (1)

Α Λ Λ ^ 42 1 t'.doc/008 ^ 44_2 h a 一 AB B8 C8 D8 六 經濟部中央標準局真工消費合作杜印策 申請專利範圍 1. 一種圓晶層級之封裝結構，包括： 一第一晶粒； 一銲墊重分佈層，在第一晶粒的第一表面上； 一絕緣體，在該銲墊重分佈層上，靠近週圍的部分； 一第二晶粒，利用一絕緣材料粘貼在該第一晶粒的一 第二表面上； 至少一金屬線，由該第一晶粒之銲墊重分佈層，絕緣 體的外圍連接至該第二晶粒與該第一晶粒的接合面； 一金線固定保護材料，固定住該金屬線，並覆蓋住該 第二晶粒的接合面；以及 複數個錫球，在該銲墊重分佈層上，該絕緣體所包圍 的區域。 2. 如申請專利範圍第1項所述之封裝結構，其中該第 一晶粒之面積小於該第二晶片的面積。 3. 如申請專利範圍第1項所述之封裝結構，其中該第 晶片和該銲墊重分佈層之間，又铦了一聚亞醯胺層Α Λ Λ ^ 42 1 t'.doc / 008 ^ 44_2 ha One AB B8 C8 D8 Sixth Ministry of Economic Affairs Central Standards Bureau real consumer cooperation Du Yinze patent application scope 1. A wafer-level packaging structure, including: A die; a pad redistribution layer on the first surface of the first die; an insulator on the pad redistribution layer, close to the surrounding part; a second die, pasted with an insulating material On a second surface of the first die; at least one metal wire, a pad redistribution layer of the first die, and a periphery of the insulator connected to a joint surface of the second die and the first die A gold wire fixing protection material, which fixes the metal wire and covers the joint surface of the second die; and a plurality of solder balls on the solder pad redistribution layer, the area surrounded by the insulator. 2. The package structure described in item 1 of the scope of patent application, wherein the area of the first die is smaller than the area of the second chip. 3. The package structure according to item 1 of the scope of patent application, wherein a polyimide layer is formed between the second chip and the pad redistribution layer. 4. 如申請專利範圍第1項所述 包括一金線。 5. 如申請專利範圍第1項所述之封裝g 緣體包括一絕緣膠帶或一非金屬。 6. 如申請專利範圍第1項所述之封裝結右 定及保護材料包括一樹脂或一液態化合物。 種晶圓層級的封裝方法，包括： 提供一第一晶片； 12 (請先閲讀背面之注意事項再填寫本頁) 其中該金屬線 其中該絕 其中該固 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I 4Λ 3ΓΤΓ5 ^ 44 S2〇>t& doc/008 A8 B8 C8 D8 申請專利範圍 對該第一晶粒進行銲墊重新分佈； 在該第一晶粒上，靠近週圍部分形成一絕緣體； 利用一絕緣膠帶或不導電膠，將第一晶片粘貼在一第 一晶粒上' 形成至少一金屬線，電性連接該第一晶粒及該第二晶 形成一金屬線之固定保護材料；以及 形成複數個錫球，電性連接該第一晶粒 其中該第一晶 經濟部中央標牟局員工消費合作社印製 8. 如申請專利範圍第7項所述之方法 片之面積小於該第二晶片之表面積。 9. 如申請專利範圍第7項所述之方法，更包括在該第 一晶片形成一銲墊重分佈層的步驟。 10. 如申請專利範圍第7項所述之方法 括一金線。 Π.如申請專利範圍第7項所述之方法，其中該固定保 護材料是利用壓模方式形成的。 12. 如申請專利範圍第11項所述之方法，其中該固定 保護材料包括樹脂。 13. 如申請專利範圍第7項所述之方法，其中該固定保 護材料是利用塗佈方式形成的。 14. 如申請專利範第13項所述之方法，其中該固定保 護材料包括液態化合物。 15. —種晶圓層級的封裝方法，包括： 提供一第一晶圓，該晶圓上包括複數個第一晶粒； 其中該金線包 L---^------i------ΐτ------0 ... (請先閱讀背面之注意事項再填寫本頁) 13 本紙張尺度適用中國國家標準（CNS ) Α4規洛（210X297公釐） Α8 Β8 CS D8 經濟部中央標準局員工消費合作杜印製 六、申請專利範圍 該些第一晶粒進行銲墊重分佈，並在該些第一晶粒上 各形成一銲墊重分佈層； 在該些銲墊重佈層上，形成複數絕緣體，以定義包圍 出一植球預定區； 對該第一晶圓進行晶粒切割，以一一分離該些第一晶 松， 提供一第二晶圓，該第二晶圓包括複數個第二晶粒； 在該些第二晶粒上，各粘貼上一個該些第一晶粒； 形成複數條金屬線，由該些銲墊重分佈層上，該絕緣 體之外圍，連接至所對應之該些第二晶粒； 形成該些金屬線之複數個保護材料層； 在該些植球預定區上形成複數個錫球； 對該第二晶圓進行晶粒切割。 16.如申請專利範圍第15項所述之方法，其中該些第 一晶粒之面積小於該些第二晶粒之面積。 Π.如申請專利範圍第15項所述之方法，其中該固定 保護材料是利用壓模方式形成的。 18. 如申請專利範圍第17項所述之方法，其中該固定 保護材料包括樹脂。 19. 如申請專利範圍第15項所述之方法，其中該固定 保護材料是利用塗怖方式形成的。 20. 如申請專利範第19項所述之方法，其中該固定保 護材料包括液態化合物。 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標牟（CNS〉Α4規格（210Χ297公釐）4. Include a gold wire as described in item 1 of the scope of patent application. 5. The package g edge body according to item 1 of the scope of patent application includes an insulating tape or a non-metal. 6. The package junction and protection material described in item 1 of the patent application scope includes a resin or a liquid compound. A wafer-level packaging method, including: providing a first chip; 12 (Please read the precautions on the back before filling out this page) where the metal wire and the solid paper size are applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) I 4Λ 3ΓΤΓ5 ^ 44 S2〇 &t; t & doc / 008 A8 B8 C8 D8 Application scope of the patent for redistribution of the first die; On the first die, close to the surrounding An insulator is partially formed; using an insulating tape or a non-conductive adhesive, the first wafer is pasted on a first die to form at least one metal wire, and the first die and the second die are electrically connected to form a metal wire. A fixed protective material; and forming a plurality of solder balls electrically connected to the first die, wherein the first die is printed by the Consumer Cooperative of the Central Bureau of Standards and Mobilization of the Ministry of Economic Affairs 8. The method sheet described in item 7 of the scope of patent application The area is smaller than the surface area of the second wafer. 9. The method according to item 7 of the scope of patent application, further comprising the step of forming a pad redistribution layer on the first wafer. 10. The method described in item 7 of the scope of patent application includes a golden thread. Π. The method according to item 7 of the scope of patent application, wherein the fixed protection material is formed by a stamping method. 12. The method according to item 11 of the patent application scope, wherein the fixed protective material comprises a resin. 13. The method according to item 7 of the scope of patent application, wherein the fixed protection material is formed by a coating method. 14. The method according to item 13 of the patent application, wherein the fixed protection material comprises a liquid compound. 15. A wafer-level packaging method, comprising: providing a first wafer, the wafer including a plurality of first dies; wherein the gold wire package L --- ^ ------ i- ----- ΐτ ------ 0 ... (Please read the precautions on the back before filling out this page) 13 This paper size applies to the Chinese National Standard (CNS) Α4 gauge (210X297 mm) Α8 Β8 CS D8 Consumption cooperation by employees of the Central Bureau of Standards of the Ministry of Economic Affairs. Du VI. The scope of patent application: These first grains are redistributed by pads, and a pad redistribution layer is formed on each of the first grains; A plurality of insulators are formed on the redistribution layers of the solder pads to define a predetermined area surrounding the planted balls; the first wafer is die-cut to separate the first crystal pines one by one to provide a second wafer. The second wafer includes a plurality of second dies; each of the first dies is pasted on each of the second dies; a plurality of metal lines are formed and the redistribution layers are distributed by the pads, The periphery of the insulator is connected to the corresponding second crystal grains; forming a plurality of protective material layers of the metal wires; Forming a plurality of solder ball bumping on a predetermined region; the second wafer dicing die. 16. The method according to item 15 of the scope of patent application, wherein the area of the first grains is smaller than the area of the second grains. Π. The method according to item 15 of the scope of patent application, wherein the fixed protective material is formed by a stamping method. 18. A method as described in claim 17 in which the fixed protective material comprises a resin. 19. The method according to item 15 of the scope of patent application, wherein the fixed protective material is formed by painting. 20. The method of claim 19, wherein the fixed protection material comprises a liquid compound. (Please read the precautions on the back before filling this page) This paper size is applicable to China National Standards (CNS> Α4 specifications (210 × 297 mm)
TW088100968A 1999-01-22 1999-01-22 Wafer-level package structure and method TW444306B (en)

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