CN106601669A - Manufacturing method of thin-film transistor array substrate - Google Patents

Manufacturing method of thin-film transistor array substrate Download PDF

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Publication number
CN106601669A
CN106601669A CN201611184209.3A CN201611184209A CN106601669A CN 106601669 A CN106601669 A CN 106601669A CN 201611184209 A CN201611184209 A CN 201611184209A CN 106601669 A CN106601669 A CN 106601669A
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CN
China
Prior art keywords
layer
pixel electrode
film transistor
thin
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201611184209.3A
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Chinese (zh)
Inventor
胡小波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to CN201611184209.3A priority Critical patent/CN106601669A/en
Publication of CN106601669A publication Critical patent/CN106601669A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Abstract

The invention provides a manufacturing method of a thin-film transistor array substrate. The manufacturing method comprises the following steps of successively forming a first metal layer and a second metal layer on a substrate on which a semiconductor layer is formed; forming a light blocking material layer on the second metal layer, and patterning the light blocking material for forming a light blocking layer, wherein the light blocking layer comprises a through hole which faces the semiconductor layer, a source electrode region and a drain electrode region which are arranged at two sides of the through hole, and a pixel electrode region which is adjacent with the drain electrode region; etching the second metal layer and the first metal layer, thereby transferring the pattern of the light blocking layer to the first metal layer and the second metal layer, and forming a source electrode, a drain electrode and a pixel electrode pattern; eliminating the light blocking layer at the pixel electrode region; eliminating the second metal layer of the pixel electrode region for forming a pixel electrode layer; and eliminating the residual light blocking layer. According to the manufacturing method, the source electrode region, the drain electrode region and the pixel electrode region are simultaneously formed through performing one light blocking process, thereby simultaneously forming the source electrode, the drain electrode and the pixel electrode, simplifying process steps of the thin-film transistor array substrate and reducing manufacturing cost of the thin-film transistor array substrate.

Description

A kind of manufacture method of thin-film transistor array base-plate
Technical field
The present invention relates to Liquid crystal production technical field, more particularly to a kind of manufacture method of thin-film transistor array base-plate.
Background technology
With constantly popularizing for liquid crystal display, the display performance of liquid crystal display is proposed it is very high will Ask.At present, in the thin-film transistor array base-plate processing procedure of liquid crystal display, need to carry out optical graving using multiple tracks light shield Journey, however, light shield is relatively costly, cost of the light shield number of times more at most needed for thin film transistor (TFT) processing procedure is higher, and when increasing processing procedure Between and complexity.
The content of the invention
The present invention provides a kind of manufacture method of thin film transistor (TFT), can simplify manufacturing process, reduces cost.
The present invention provides a kind of manufacture method of thin-film transistor array base-plate, the system of the thin-film transistor array base-plate The method of making includes:
First and second metal level is sequentially formed with the substrate for be formed with semiconductor layer;
Photoresist layer is formed in the second metal layer, and patterns the photoresist layer and form photoresist layer;Institute State photoresist layer include the through hole relative with the semiconductor layer, the source area positioned at the through hole both sides, drain region and with it is described The adjacent pixel electrode area in drain region;
Described second and the first metal layer are etched, the pattern of the photoresist layer is transferred to into first and second metal level On, to form source-drain electrode and pixel electrode pattern;
Remove the photoresist layer in the pixel electrode area;
The second metal layer in the pixel electrode area is removed, to form pixel electrode layer;
Remove remaining photoresist layer.
Wherein, the manufacture method also includes after the remaining photoresist layer of the removal:
Going on removing photoresistance layer array base palte to form insulating barrier, and carry out patterned process.
Wherein, the manufacture method is sequentially formed with first and second gold described on the substrate for be formed with semiconductor layer Also include before category layer:
One substrate is provided;
Grid and public electrode are formed on the substrate;
Insulating barrier is formed with the substrate for being formed with grid and public electrode;
Semiconductor layer is formed with the insulating barrier.
Wherein, the mode for being formed by physical vapour deposition (PVD) of first and second metal level is by the first metal and Two metals are sputtered onto respectively on the substrate for being formed with semiconductor layer.
Wherein, first metal is molybdenum titanium, and second metal is copper.
Wherein, the thickness of the first metal layer is 150-500 angstrom, and the thickness of the second metal layer is 2000-5000 Angstrom.
Wherein, the patterning photoresist layer forms photoresist layer includes:
Patterning is carried out to the photoresist layer by intermediate tone mask light shield technique and forms the photoresist layer, its middle position The thickness of the photoresist layer on the source-drain electrode is less than in the thickness of the photoresist layer of the pixel electrode area.
Wherein, in step etching described second and the first metal layer, by the pattern of the photoresist layer be transferred to first and In second metal layer, to form source-drain electrode and pixel electrode pattern in, using fluorine-containing hydrogen peroxide to the described second and first gold medal Category layer is etched.
Wherein, the second metal layer in the pixel electrode area is removed in step, to form pixel electrode layer in, using not containing The hydrogen peroxide of fluorine removes the second metal layer in the pixel electrode area.
Wherein, the pattern line width in the pixel electrode layer is less than 2um.
The manufacture method of the thin-film transistor array base-plate of the present invention is included on the substrate for be formed with semiconductor layer successively It is formed with first and second metal level;Photoresist layer is formed in the second metal layer, and patterns the photoresist Layer forms photoresist layer;The photoresist layer include the through hole relative with the semiconductor layer, the source area positioned at the through hole both sides, Drain region and the pixel electrode area adjacent with the drain region;Described second and the first metal layer are etched, by the photoresist layer Pattern be transferred on first and second metal level, to form source-drain electrode and pixel electrode pattern;Remove the pixel electrode area Photoresist layer;The second metal layer in the pixel electrode area is removed, to form pixel electrode layer;Remove remaining photoresist layer.Cause This, the present invention needs to carry out a light shield technique while forming source area, drain region and pixel electrode area, you can with shape simultaneously Into source electrode, drain electrode and pixel electrode, light shield number of times is saved relative to prior art, simplify thin-film transistor array base-plate Processing step, reduces the cost of manufacture of thin-film transistor array base-plate.
Description of the drawings
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is a kind of flow chart of the manufacture method of thin-film transistor array base-plate provided in an embodiment of the present invention.
Fig. 2 to Fig. 8 is thin film transistor (TFT) in each manufacturing process of the thin-film transistor array base-plate of the embodiment of the present invention The profile of array base palte.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than the embodiment of whole.It is based on Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made Embodiment, belongs to the scope of protection of the invention.
Fig. 1 is referred to, embodiment of the present invention provides a kind of manufacture method of thin-film transistor array base-plate.The thin film The manufacture method of transistor (TFT) array substrate comprises the steps.
See also Fig. 2, step 101, be sequentially formed with the substrate 10 for being formed with semiconductor layer 11 first metal Layer 12 and second metal layer 13.
Wherein, can also comprise the steps before step 101.
One substrate 10 is provided.
In the present embodiment, the substrate 10 is a glass substrate.It is to be appreciated that in other embodiments, it is described Substrate 10 is not limited in as glass substrate.
Grid 14 and public electrode 15 are formed on the substrate 10.
Insulating barrier 16 is formed with being formed with the substrate of grid 14 and public electrode 15.
Semiconductor layer 11 is formed with the insulating barrier.
Wherein, the material of the semiconductor layer be Zinc Oxide (ZnO), indium zinc oxide (InZnO), zinc-tin oxide (ZnSnO), Gallium indium zinc oxide (GaInZnO) is made with the one kind in zirconium indium-zinc oxide (ZrInZnO).
It should be noted that in the present embodiment, first and second metal level 12 and 13 is formed by physics The mode of vapour deposition is respectively sputtered onto the first metal and the second metal on the substrate 10 for being formed with semiconductor layer 11.Wherein, First metal is molybdenum titanium, and second metal is copper.The thickness of the first metal layer 12 can be 150-500 angstrom.Institute The thickness for stating second metal layer 13 can be 2000-5000 angstrom.
Fig. 3 and Fig. 4, step 102, the formation photoresist layer 17 in the second metal layer 13 are seen also, and is schemed Photoresist layer described in case forms photoresist layer.Wherein, the photoresist layer includes the through hole relative with the semiconductor layer 11 171st, positioned at the through hole both sides source area 172, drain region 173 and the pixel electrode area adjacent with the drain region 173 174。
Specifically, in a step 102, the patterning photoresist layer 17 forms photoresist layer includes:
Light shield technique is carried out by intermediate tone mask patterning is carried out to the photoresist layer 17 to form the light Resistance layer, wherein the thickness positioned at the photoresist layer in the pixel electrode area 174 is less than on the source area 172 and drain region 173 The thickness of photoresist layer.
See also Fig. 5, step 103, etching described second and the first metal layer 13 and 12, by the photoresist layer Pattern is transferred on first and second metal level 12 and 13, to form source electrode 18, drain electrode 19 and pixel electrode pattern.
It should be noted that in step 103, using fluorine-containing hydrogen peroxide to described second and the first metal layer 13 and 12 It is etched.Due to having etching action to described first and second metal containing fluorine-containing hydrogen peroxide, can be by not by the light First and second metal level 12 and 13 that resistance layer is blocked is etched away.
See also Fig. 6, step 104, the photoresist layer in the removal pixel electrode area 174.
See also Fig. 7, step 105, the second metal layer 13 in the removal pixel electrode area 174, to form pixel Electrode 20.
It should be noted that in step 105, using not fluorine-containing hydrogen peroxide the of the pixel electrode area 172 is removed Two metal levels 13.
It should be noted that not fluorine-containing hydrogen peroxide to the second metal etch completely, and can not have to first metal Have an impact, so as to define pixel electrode 20.Wherein, the pattern line width in the pixel electrode 20 is less than 2um.
See also Fig. 8, step 106, the remaining photoresist layer of removal.
Further, the manufacture method of the thin-film transistor array base-plate also includes after step 106:
Going on the array base palte of removing photoresistance layer 17 to form insulating barrier, and carry out patterned process.
In the present embodiment, the manufacture method of the thin film transistor (TFT) array is included in the second metal layer 13 and is formed Photoresist layer 17, and pattern the formation photoresist layer of the photoresist layer 17;The photoresist layer includes and the semiconductor layer 11 relative through holes 171, the source area 172 positioned at the through hole both sides, drain region 173 and adjacent with the drain region 173 Pixel electrode area 174;Etch described second and the first metal layer 13 and 12, by the pattern of the photoresist layer be transferred to first and In second metal layer 12 and 13, to form source-drain electrode 19,20 and pixel electrode pattern;Remove the light in the pixel electrode area 174 Resistance layer;The second metal layer 13 in the pixel electrode area 174 is removed, to form pixel electrode 20.Therefore, this enforcement only need into Light shield technique of row to form source area, drain region and pixel electrode area 174 simultaneously, you can to show source electrode 18, leakage simultaneously Pole 19 and pixel electrode 20, relative to prior art light shield number of times is saved, the technique for simplifying thin-film transistor array base-plate Step, reduces the cost of manufacture of thin-film transistor array base-plate.
The present invention additionally provides the manufacture method of thin film transistor (TFT) for above two embodiment, is illustrating concrete preparation side Before method, it should be appreciated that in the present invention, the patterning refers to patterning processes, it may include photoetching process, or, including light Carving technology and etch step, while other technique for forming predetermined pattern can also to be used for including printing, ink-jet etc.;Photoetching work Skill, refers to film forming, exposure, development, and etc. utilization photoresist, mask plate, the exposure machine etc. of technical process the work of figure is formed Skill.Can be according to the corresponding patterning processes of structure choice formed in the present invention.
The display device formed by the manufacture method of embodiment of the present invention thin film transistor (TFT) array, Ke Yiwei:Liquid crystal surface Plate, LCD TV, liquid crystal display, oled panel, OLED TVs, Electronic Paper, DPF, mobile phone etc..
Above disclosed is only a kind of preferred embodiment of the invention, can not limit the power of the present invention with this certainly Sharp scope, one of ordinary skill in the art will appreciate that all or part of flow process of above-described embodiment is realized, and according to present invention power Profit requires made equivalent variations, still falls within the covered scope of invention.

Claims (10)

1. a kind of manufacture method of thin-film transistor array base-plate, it is characterised in that the system of the thin-film transistor array base-plate The method of making includes:
First and second metal level is sequentially formed with the substrate for be formed with semiconductor layer;
Photoresist layer is formed in the second metal layer, and patterns the photoresist layer and form photoresist layer;The light Resistance layer include the through hole relative with the semiconductor layer, the source area positioned at the through hole both sides, drain region and with the drain electrode Adjacent pixel electrode area of area;
Described second and the first metal layer are etched, the pattern of the photoresist layer is transferred on first and second metal level, with Form source-drain electrode and pixel electrode pattern;
Remove the photoresist layer in the pixel electrode area;
The second metal layer in the pixel electrode area is removed, to form pixel electrode layer;
Remove remaining photoresist layer.
2. the manufacture method of thin-film transistor array base-plate as claimed in claim 1, it is characterised in that the manufacture method exists Described removal also includes after remaining photoresist layer:
Going on removing photoresistance layer array base palte to form insulating barrier, and carry out patterned process.
3. the manufacture method of thin-film transistor array base-plate as claimed in claim 1, it is characterised in that the manufacture method exists Described being sequentially formed with the substrate for be formed with semiconductor layer before first and second metal level also includes:
One substrate is provided;
Grid and public electrode are formed on the substrate;
Insulating barrier is formed with the substrate for being formed with grid and public electrode;
Semiconductor layer is formed with the insulating barrier.
4. the manufacture method of thin-film transistor array base-plate as claimed in claim 1, it is characterised in that it is described first and second First metal and the second metal are sputtered onto to be formed with respectively and are partly led by the mode for being formed by physical vapour deposition (PVD) of metal level On the substrate of body layer.
5. the manufacture method of thin-film transistor array base-plate as claimed in claim 4, it is characterised in that first metal is Molybdenum titanium, second metal is copper.
6. the manufacture method of the thin-film transistor array base-plate as described in claim 4 or 5, it is characterised in that first gold medal The thickness of category layer is 150-500 angstrom, and the thickness of the second metal layer is 2000-5000 angstrom.
7. the manufacture method of thin-film transistor array base-plate as claimed in claim 1, it is characterised in that described in the patterning Photoresist layer forms photoresist layer to be included:
Patterning is carried out to the photoresist layer by intermediate tone mask light shield technique and forms the photoresist layer, wherein positioned at institute The thickness for stating the photoresist layer of pixel electrode area is less than the thickness of the photoresist layer on the source-drain electrode.
8. the manufacture method of thin-film transistor array base-plate as claimed in claim 1, it is characterised in that described in step etching Second and the first metal layer, the pattern of the photoresist layer is transferred on first and second metal level, with formed source-drain electrode and In pixel electrode pattern, described second and the first metal layer are etched using fluorine-containing hydrogen peroxide.
9. the manufacture method of thin-film transistor array base-plate as claimed in claim 1, it is characterised in that remove in step described The second metal layer in pixel electrode area, to form pixel electrode layer in, the pixel electrode is removed using not fluorine-containing hydrogen peroxide The second metal layer in area.
10. the manufacture method of thin-film transistor array base-plate as claimed in claim 1, it is characterised in that the pixel electrode Pattern line width in layer is less than 2um.
CN201611184209.3A 2016-12-20 2016-12-20 Manufacturing method of thin-film transistor array substrate Pending CN106601669A (en)

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Application Number Priority Date Filing Date Title
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111477638A (en) * 2020-04-28 2020-07-31 Tcl华星光电技术有限公司 Array substrate, manufacturing method thereof and display device
CN114171457A (en) * 2021-12-07 2022-03-11 深圳市华星光电半导体显示技术有限公司 Display panel and preparation method thereof

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CN105679773A (en) * 2016-01-29 2016-06-15 深圳市华星光电技术有限公司 Array substrate and preparation method thereof
CN105977265A (en) * 2016-07-13 2016-09-28 深圳市华星光电技术有限公司 Array substrate and manufacturing method thereof

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Publication number Priority date Publication date Assignee Title
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US20120193624A1 (en) * 2011-02-01 2012-08-02 Samsung Mobile Display Co., Ltd. Thin-Film Transistor Array Substrate and Method of Fabricating the Same
KR20120116649A (en) * 2011-04-13 2012-10-23 엘지디스플레이 주식회사 Liquid crystal display device and method of manufacturing the same
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111477638A (en) * 2020-04-28 2020-07-31 Tcl华星光电技术有限公司 Array substrate, manufacturing method thereof and display device
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CN114171457A (en) * 2021-12-07 2022-03-11 深圳市华星光电半导体显示技术有限公司 Display panel and preparation method thereof

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