CN106571333A - 制造半导体装置的方法 - Google Patents

制造半导体装置的方法 Download PDF

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Publication number
CN106571333A
CN106571333A CN201610876433.2A CN201610876433A CN106571333A CN 106571333 A CN106571333 A CN 106571333A CN 201610876433 A CN201610876433 A CN 201610876433A CN 106571333 A CN106571333 A CN 106571333A
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China
Prior art keywords
layer
dielectric layer
dielectric
metal oxide
conductive material
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CN201610876433.2A
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English (en)
Inventor
邓志霖
蔡荣训
郑凱方
黄心岩
陈海清
包天
包天一
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN106571333A publication Critical patent/CN106571333A/zh
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Abstract

一种制造半导体装置的方法，包括：于基板上形成多个高介电系数金属栅极结构。高介电系数金属栅极结构被多个间隙所隔开。高介电系数金属栅极结构各包含第一介电层于高介电系数金属栅极结构的上表面。以第一导电材料填充间隙。透过回蚀制程来于各间隙中移除部分的第一导电材料。使用旋转涂布沉积制程来形成金属氧化层。于高介电系数金属栅极结构上且于第一导电材料上形成金属氧化层。于金属氧化层上形成第二介电层。在第二介电层中蚀刻开口。开口被蚀刻贯穿第二介电层且贯穿金属氧化层。以第二导电材料填充开口。

Description

制造半导体装置的方法
技术领域
本揭露实施例是有关于半导体技术，且特别是有关于制造半导体装置的方法。
背景技术
半导体集成电路(integrated circuit，IC)产业已历经快速地成长。集成电路材料与设计的技术进步已产生了几个世代的集成电路，其中每一世代相较于前一世代具有更小且更复杂的电路。然而，这样的进步增加了加工与制造集成电路的复杂度，且为了实现这样的进步，集成电路的加工与制造也需要取得同样的进展。在集成电路演变的过程中，随着几何尺寸(如使用制造制程所可以创建的最小元件(或导线))减少，功能密度(如每单位晶片面积内互连元件的数量)已广泛增加。
可形成多层互连结构作为半导体制造的一部分。除了其他的元件以外，互连结构包含金属导线与介层窗/接触以提供电性连接至晶体管元件，如栅极、源极与漏极。金属导线与介层窗透过层间介电(interlayer dielectric，ILD)材料彼此电性绝缘。现有的半导体制造技术可使用氧碳化硅(silicon oxycarbide，SiOC)来形成部分的层间介电质。然而，使用氧碳化硅来形成层间介电质可能会导致层间介电质中的孔洞被捕获(trapped)，且会因为不期望的氧化而增加了电阻系数。如此之下，降低了半导体装置的效能。
所以，虽然形成层间介电质的传统方法与材料已普遍满足它们的预期目的，但它们并没有在各方面完全令人满意。
发明内容
本揭露提出制造半导体装置的方法，包含：于基板上形成多个栅极结构，栅极结构被多个间隙所隔开；以导电材料填充多个间隙；于栅极结构上且于填充间隙的导电材料上形成金属氧化层；于金属氧化层上形成介电层；以及形成一个或多个导电接触延伸贯穿介电层且贯穿金属氧化层。
附图说明
从以下结合所附附图所做的详细描述，可对本揭露的态样有更佳的了解。需注意的是，根据业界的标准实务，各特征并未依比例绘示。事实上，为了使讨论更为清楚，各特征的尺寸都可任意地增加或减少。
图1至图18是根据本揭露的一些实施例的半导体装置于各种制造阶段的图解的剖面侧视图；
图19是绘示根据本揭露的一些实施例的制造半导体装置的方法的流程图。
具体实施方式
本揭露提供了许多不同的实施例或例子，用以实作此揭露的不同特征。为了简化本揭露，一些元件与布局的具体例子会在以下说明。当然，这些仅仅是例子而不是用以限制本揭露。例如，若在后续说明中提到了第一特征形成在第二特征上面，这可包括第一特征与第二特征是直接接触的实施例；这也可以包括第一特征与第二特征之间还形成其他特征的实施例，这使得第一特征与第二特征没有直接接触。此外，本揭露可能会在各种例子中重复图示符号及/或文字。此重复是为了简明与清晰的目的，但本身并不决定所讨论的各种实施例及/或设置之间的关系。
再者，在空间上相对的用语，例如底下、下面、较低、上面、较高等，是用来容易地解释在图示中一个元件或特征与另一个元件或特征之间的关系。这些空间上相对的用语除了涵盖在图示中所绘的方向，也涵盖了装置在使用或操作上不同的方向。这些装置也可被旋转(例如旋转90度或旋转至其他方向)，而在此所使用的空间上相对的描述同样也可以有相对应的解释。
需要形成电互连以电性互连半导体装置的各种微电子元件(如源极/漏极、栅极等)以作为半导体制造的一部分。一般而言，电互连，如金属导线或介层窗，透过层间介电材料彼此电性绝缘。传统的半导体制造技术使用氧碳化硅作为层间介电质的材料。然而，使用氧碳化硅作为层间介电质的材料可能导致一些问题。举例来说，使用化学气相沉积(chemical vapor deposition，CVD)或原子层沉积(atomic layer deposition，ALD)制程来形成氧碳化硅材料。作为半导体按比例缩减制程的延续(如小于5纳米的技术节点)，这些制程可能不具有足够的间隙填充效果。如此之下，孔洞可能形成于层间介电层内，这会降低半导体装置效能。此外，氧碳化硅材料的形成也涉及含氧气体。氧气可氧化下方的金属层(简称氧侵蚀)，且这可能导致电阻系数增加，这也是不受欢迎的。此外，氧碳化硅的形成可能遇到其他问题，例如因为受限的蚀刻选择比而减少了制程视窗，又例如因为需要许多步骤(如研磨/平坦化制程)来形成氧碳化硅层而增加了成本。这些问题可能随着元件尺寸越来越小而加剧。
为了解决上述讨论的使用氧碳化硅来形成层间介电质的这些问题，本揭露旨在使用旋转涂布金属氧化沉积制程来形成部分的层间介电质。本揭露的各种态样现在将参照图1至图19来更详细地讨论。此处讨论的实施例是使用N5(5纳米技术节点)中段(mid-end-of-line，MEOL)制程。
图1至图18是根据本揭露的各种态样的半导体装置50于各种制造阶段的图解的剖面侧视图。在所示的实施例中，于5纳米或更低的技术节点制造半导体装置50。半导体装置50可包含集成电路晶片、***单晶片(system on chip，SoC)或其部分，且可包含各种被动与主动微电子元件，如电阻、电容、电感、二极管、金氧半导体场效晶体管(metal-oxidesemiconductor field effect transistors，MOSFET)、互补式金氧半导体(complementarymetal-oxide semiconductor，CMOS)晶体管、双极接面晶体管(bipolar junctiontransistors，BJT)、横向扩散金氧半导体(laterally diffused MOS，LDMOS)晶体管、高功率金氧半导体晶体管或其他种类的晶体管。
半导体装置50包含基板60。在一些实施例中，基板60为掺杂p型掺杂物，如硼，的硅基板(如p型基板)。可选地，基板60可为其他合适的半导体材料。举例来说，基板60可为掺杂n型掺杂物，如磷或砷，的硅基板(如n型基板)。基板60可包含其他元素半导体，如锗或钻石。基板60可选择性地包含化合物半导体和/或合金半导体。再者，基板60可包含磊晶层(epitaxial layer，epi layer)，可应变以增进效能，且可包含绝缘层上覆硅(silicon-on-insulator，SOI)结构。
于基板60中形成多个已掺杂的区域。举例来说，于基板60中形成晶体管的多个源极/漏极70。在一些实施例中，这些源极/漏极70可透过一个或多个离子布植制程而形成。于基板60中也形成介电绝缘结构，如浅沟槽隔离(shallow trench isolation，STI)或深沟槽隔离(deep trench isolation，DTI)，但为求简化，在此没有具体地绘示出它们。
于基板60上形成多个栅极结构80。在所述的实施例中，栅极结构80是高介电系数金属栅极(high-k metal gate，HKMG)结构。不像传统的栅极结构具有多晶栅极电极，高介电系数金属栅极结构具有包含金属材料的栅极电极。举例来说，在一些实施例中，金属栅极电极可包含功函数金属，如氮化钛(titanium nitride，TiN)、钨(tungsten，W)、氮化钨(tungsten nitride，WN)或钨铝(tungsten aluminum，WAl)。金属栅极电极也可包含铝、钛、钨或铜来做为填充金属。
也不像传统的栅极结构具有二氧化硅栅极介电质，高介电系数金属栅极结构具有高介电系数栅极介电质。高介电系数介电材料为介电系数大于二氧化硅的介电系数(约等于4)的材料。在一些实施例中，高介电系数金属栅极结构的栅极介电质可包含氧化铪(hafnium oxide，HfO2)，其介电系数的范围为约18至约40，或在替代的实施例中，高介电系数金属栅极结构的栅极介电质可包含氧化锆(ZrO2)、氧化钇(Y2O3)、氧化镧(La2O5)、氧化钆(Gb2O5)、氧化钛(TiO2)、氧化钽(Ta2O5)、氧化铪铒(HfErO)、氧化铪镧(HfLaO)、氧化铪钇(HfYO)、氧化铪钆(HfGbO)、氧化铪铝(HfAlO)、氧化铪锆(HfZrO)、氧化铪钛(HfTiO)、氧化铪钽(HfTaO)或氧化锶钛(SrTiO)。
高介电系数金属栅极结构80的形成可能涉及栅极取代制程，其中首先形成假性(dummy)栅极电极(也可能是假性栅极介电质)，接着移除假性栅极电极，且假性栅极电极随后被金属栅极电极(也可能是高介电系数栅极介电质)所取代。作为例示，形成高介电系数金属栅极结构的细节详述于2012年4月5日提申的美国专利申请号13/440,848，标题为Cost-effective gate replacement process，作者为Zhu等人，其为2014年6月17日公告的美国专利号8,753,931，其所揭露的内容以引用的方式并入本文。
栅极间隔物90设置于栅极结构80的侧壁上。栅极间隔物可包含合适的介电材料。在所述的实施例中，栅极间隔物90包含氧碳化硅。在替代的实施例中，栅极间隔物90可包含其他合适的介电材料，如二氧化硅、碳化硅、氮氧化硅或其组合物。
于基板60上且于栅极间隔物90的侧壁上设置层间介电层100。在所述的实施例中，层间介电层100包含氧碳化硅。在替代的实施例中，层间介电层100可包含其他合适的低介电系数介电材料。于层间介电层100上设置层间介电层110。在所述的实施例中，层间介电层110包含二氧化硅。在图1所示的制造阶段中，已执行平坦化制程，例如化学机械研磨(chemical mechanical polishing，CMP)制程，来平面化与平坦化层间介电层110与高介电系数金属栅极结构80的表面。
现在请参照图2，栅极结构80被回蚀(etch back)。换句话说，透过回蚀制程来移除部分的每一高介电系数金属栅极结构80，如此可于高介电系数金属栅极结构80上方形成开口或沟槽120。
现在请参照图3，于层间介电层110上且于高介电系数金属栅极结构80上形成介电层130。也于开口120中形成介电层130。介电层130的形成也可称为再填充制程。在所示的实施例中，介电层130包含氮化硅。透过原子层沉积制程来形成氮化硅，原子层沉积制程为共形的。共形的原子层沉积制程可能导致在部分的介电层130中的接缝140形成于高介电系数金属栅极结构80上方。
现在请参照图4，对介电层130执行平坦化/研磨制程，如化学机械研磨制程。化学机械研磨制程的结果，移除了部分的介电层130，且介电层130的剩余部分具有实质上平面或平坦的表面，虽然接缝140在此时可能仍然存在。
现在请参照图5，执行一个或多个蚀刻制程来移除设置于各高介电系数金属栅极结构80上的部分的介电层130。也移除部分的栅极间隔物90、层间介电层100与层间介电层110。结果，于高介电系数金属栅极结构80上形成开口150。
现在请参照图6，于各个开口150中形成非晶硅层160。换句话说，于介电层130上(与部分的栅极间隔物90与层间介电层100上)形成非晶硅层160。透过于介电层130上且于层间介电层110上沉积非晶硅材料且执行化学机械研磨制程于被沉积的非晶硅材料直到非晶硅材料与层间介电层110共平面，可形成非晶硅层160。
现在请参照图7，于层间介电层110上且于非晶硅层160上形成层间介电层200。层间介电层200可包含低介电系数介电材料。于层间介电层200上形成硬光罩层210。在一些实施例中，硬光罩层210可包含氮化钛。于硬光罩层210上形成介电层220。在一些实施例中，介电层220可包含二氧化硅。接着于介电层220上形成非晶硅层230。因图案化的目的而使用这些层210-230。
现在请参照图8，执行图案化的制程来移除设置于相邻的高介电系数金属栅极结构80之间的层间介电层110，也移除设置于被移除的层间介电层110下方的部分的层100。结果，于相邻的高介电系数金属栅极结构80之间形成间隙250。换句话说，高介电系数金属栅极结构80彼此至少被间隙250所隔开。非晶硅层160仍存在。源极/漏极70透过间隙250而暴露，且在之后的制程中将于一个或多个源极/漏极70上形成导电接触，以便提供电互连至源极/漏极。于其后可移除硬光罩层210、介电层220与非晶硅层230。
现在请参照图9，于高介电系数金属栅极结构80上形成导电材料300。透过合适的沉积制程可形成导电材料300。导电材料300填充间隙250。因此，导电材料300是与源极/漏极70电性与物理接触。在一些实施例中，导电材料300包含钴。在一些其他实施例中，导电材料300可包含钨或钌。
现在请参照图10，对导电材料300执行研磨/平坦化制程，如化学机械研磨制程。除了移除部分的导电材料300，化学机械研磨制程也移除了非晶硅层160与层间介电层200(与部分的层间介电层110)。在化学机械研磨制程的最后，填充间隙250的导电材料300的部分的表面、层间介电层110的表面与设置于高介电系数金属栅极结构80上的与介电层130的表面互为共平面。在此时也因为研磨，大部分移除了先前存在于层130内的接缝。
现在请参照图11，蚀刻掉填充于各个间隙250中的部分的导电材料300。这可称为钴回蚀制程。回蚀制程形成凹口320(或开口)。在一些实施例中，回蚀制程具有大于约100埃的蚀刻深度(如凹口320的深度)。执行回蚀制程来避免或减少漏电的可能性。举例来说，如果没有回蚀导电材料300，则从高介电系数金属栅极结构80的金属栅极电极到导体(之后的制程所形成者)的漏电路径将会更短，这意味着漏电流将更可能发生。于此，凹口320的蚀刻深度被配置的足够深(如大于约100埃)以便最小化此漏电风险。
现在请参照图12，执行沉积制程350来于层间介电层110、高介电系数金属栅极结构80与导电材料300上形成金属氧化层370。沉积制程350是旋转涂布沉积制程。在一些实施例中，以范围从约500每分钟旋转数(revolutions-per-minute，RPM)到约3000每分钟旋转数的旋转，且以范围从约20秒到约200秒的周期来执行旋转涂布沉积制程。沉积制程350也可包含通入空气或氮气两者之一的后烘(如在材料370已旋转涂布沉积之后)制程，其中后烘制程以范围从约摄氏50度到约摄氏400度的温度来执行。执行这些制程条件以确保形成后的金属氧化层370具有期望的厚度与品质。在一些实施例中，期望的厚度的范围从约100埃到约1000埃。可理解的是，旋转涂布沉积制程并不涉及含氧气体的使用。
在各种实施例中，金属氧化层370可具有如下的材料组合物：氧化铝、氧化锆、氧化锌、氧化钨、氧化钽、氧化钛或氧化铪。在一些实施例中，金属氧化层370具有如下的特性：介电系数大于约7；漏电流范围从约10-10到10-13安培/平方厘米；以及介电崩溃(dielectricbreakdown，EBD)范围从约5-8毫伏/厘米。
使用沉积制程350的金属氧化层370的形成提供一些优点。举例来说，金属氧化材料的旋转涂布沉积具有良好的间隙填充效果，且确保在金属氧化层370中将不会形成接缝或孔洞。相较之下，与透过沉积制程350的旋转涂布沉积来形成金属氧化层370不同，传统的方法通常透过化学气相沉积或原子层沉积制程来形成氧碳化硅。透过化学气相沉积或原子层沉积制程来形成氧碳化硅可能在氧碳化硅材料内捕获(trap)孔洞。被捕获的孔洞可能使制程控制更困难且可能导致可靠性的问题。
此外，传统的形成氧碳化硅材料的化学气相沉积或原子层沉积制程可能涉及含氧气体(如氧气或二氧化碳)。含氧气体可能透过等离子反应氧化下方的导电材料(如导电材料300)，借此造成电阻系数的增加，这是对于元件效能而言所不期望者。相较之下，于此所执行的沉积制程350没有使用含氧气体，借此消除了介于金属氧化层370与导电材料300之间的介面的氧化的风险。
此外，在传统的制造制程中，氧碳化硅层的表面形貌变化(surface topographyvariation)对后续的制程而言可能太多。所以，透过化学气相沉积或原子层沉积形成氧碳化硅层之后，通常会在氧碳化硅层上执行研磨制程，如化学研磨制程。化学研磨制程使得氧碳化硅层平坦，但它也可能造成过多的氧碳化硅材料被移除。如此之下，化学机械研磨制程之后通常会执行其他的氧碳化硅沉积来确保氧碳化硅是足够厚且具有平坦的表面。换句话说，形成氧碳化硅层的传统方法可能涉及三个单独的步骤：初始的氧碳化硅沉积制程、接续的化学机械研磨制程、接续的其他的氧碳化硅沉积制程。需要执行三个单独的制程来形成氧碳化硅层既昂贵且更耗时。
相较之下，本揭露可在单一制程中形成金属氧化层370—沉积制程370(使用旋转涂布沉积)。旋转涂布沉积的一个优点为金属氧化层的表面380是足够平坦，使得在附加的层可被形成在其上之前，不再需要后续的平坦化制程。换句话说，金属氧化层370的表面380相较于传统方法形成的氧碳化硅层是较平坦的(或具有较少的表面形貌变化)，使得任何后续的化学机械研磨制程为选择性的而非必要性的。因为不需在金属氧化层370上执行化学机械研磨制程，故将不会有任何厚度的损失，且如此也不需要金属氧化材料的额外的沉积。在本方法中，于此的单一制造制程(如沉积制程350)有效地取代涉及氧碳化硅形成的传统制造中的三个单独的制造制程。
现在请参照图13，于金属氧化层370的平坦表面380上形成其他的层间介电层400。透过已知技术中的合适的沉积制程，如化学气相沉积，来形成层间介电层400。层间介电层400可包含合适的介电材料。
现在请参照图14，执行一个或多个蚀刻制程410来于其中一个栅极结构80上形成开口420。开口420延伸贯穿层间介电层400，且贯穿金属氧化层370，但停止于介电层130。换句话说，介电层130在制造的此步骤中作为蚀刻停止层。制造的此步骤也可称为VG图案化步骤(如栅极的图案化导电介层窗/接触)。
由此可见，本揭露的其他优点为其扩大了制程视窗。具体来说，由于介于介电层130与金属氧化层370(相较于传统制程中的介电层130与氧碳化硅层)之间的蚀刻选择比的增加，扩大了制程视窗。更详细地说，如同上面所讨论的，介电层130包含氮化硅。当使用氧碳化硅层而非使用金属氧化层370，必须配置蚀刻制程420使得介于氮化硅材料与氧碳化硅材料之间有足够的蚀刻选择比。换句话说，氮化硅材料与氧碳化硅材料需具有显著地不同的蚀刻速率，使得当氮化硅材料实质上仍未被蚀刻时，氧碳化硅材料能被蚀刻掉。然而，这可证明为困难的，因为氮化硅与氧碳化硅都包含硅，这意味着以配置蚀刻制程420来移除氧碳化硅而不影响氮化硅是困难的。
相较之下，本揭露使用金属氧化物来布植层370。氮化硅与金属氧化物之间没有元件交叠。照此方法，更容易配置蚀刻制程420来移除层370的金属氧化材料，而不影响层130的氮化硅材料。换句话说，改善了介于金属氧化层370与介电层130之间的蚀刻选择比，这允许更大的制程视窗。在一些实施例中，蚀刻选择比可调整至15：1或更高。
现在请参照图15，执行其他的蚀刻制程430来于两个相邻的高介电系数金属栅极结构80之间形成开口440。换句话说，于其中一个源极/漏极70上方形成开口440。开口440延伸贯穿层间介电层400，但停止于金属氧化层370。换句话说，金属氧化层370作为此制造步骤中的蚀刻停止层。此制造步骤也可称为VD图案化步骤(如源极/漏极的图案化导电介层窗/接触)。
现在请参照图16，执行额外的蚀刻制程480来使开口420、440更往下延伸。透过开口420而暴露的部分的介电层130被蚀刻掉，所以此时开口420延伸贯穿介电层130，借此使高介电系数金属栅极结构80暴露。透过开口440而暴露的部分的金属氧化层370也被蚀刻掉，所以此时开口440延伸贯穿金属氧化层370，借此使导电材料300暴露。
现在请参照图17，执行沉积制程500来于层间介电层400上形成导电材料510。也形成导电材料510来填充开口420、440。所以，导电材料510与栅极结构80(先前透过开口420而暴露者)物理及电性接触，且导电材料510与导电材料300(先前透过开口440而暴露者)物理及电性接触。在一些实施例中，导电材料510包含钴。在一些其他实施例中，导电材料510可包含钨或钌。
现在请参照图18，可执行研磨制程550来移除导电材料510与层间介电层400的多余的部分，且平坦化导电材料510的剩余的部分的表面。结果，形成导电接触510A、510B，其与金属氧化层370具有共平面的表面。导电接触510A的下方提供电性连接至高介电系数金属栅极结构80，且导电接触510B的下方提供电性连接至源极/漏极70。
图19是绘示根据本揭露的各种态样的制造半导体装置的方法900的流程图。执行方法900的一个或多个步骤作为制造制程的一部分，其半导体技术节点为5纳米技术节点或更小。
方法900包含步骤910：于基板上形成多个栅极结构。栅极结构被多个间隙所隔开。在一些实施例中，栅极结构为高介电系数金属栅极结构。在一些实施例中，分别形成栅极结构来于栅极结构的上表面具有氮化硅层。
方法900包含步骤920：以导电材料填充间隙。在一些实施例中，导电材料包含钴。
方法900包含步骤930：在每个间隙中回蚀部分的导电材料。
方法900包含步骤940：于栅极结构上且于填充间隙的导电材料上形成金属氧化层。在一些实施例中，使用旋转涂布沉积制程来执行金属氧化层的形成。旋转涂布沉积制程没有使用含氧气体。在一些实施例中，金属氧化层的形成包含形成氧化铝、氧化锆、氧化锌、氧化钨、氧化钽、氧化钛或氧化铪以作为金属氧化材料。
方法900包含步骤950：于金属氧化层上形成介电层。在一些实施例中，介电层包含低介电系数介电材料且形成介电层作为部分的层间介电层。在一些实施例中，执行于金属氧化层上介电层的形成并没有研磨金属氧化层的表面。换句话说，于金属氧化层的表面上形成介电层之前，金属氧化层的表面不需研磨。
方法900包含步骤960：形成一个或多个导电接触延伸贯穿介电层且贯穿金属氧化层。在一些实施例中，一个或多个导电接触的形成包含于栅极结构上蚀刻开口。开口被蚀刻贯穿氮化硅层。在一些实施例中，配置蚀刻来对于金属氧化层与氮化硅层具有不同的蚀刻选择比。
基于上述讨论，可见本揭露提供优于传统形成层间介电质的方法与装置的优点。然而，可理解的是，其他实施例可能提供额外的优点，且并非所有的优点必然在此揭露，且并非所有的实施例需要有特定的优点。一个优点为旋转涂布金属氧化沉积没有使用含氧气体，这减少了不经意地氧化下方的金属材料的风险。其他优点为相较于传统使用化学气相沉积与原子层沉积方法来形成使用氧碳化硅材料的层间介电质，旋转涂布金属氧化沉积具有较佳的间隙填充效果。所以，原本氧碳化硅材料会具有孔洞被捕获于金属氧化材料内部，但本揭露的实施例则没有孔洞被捕获于金属氧化材料内部。又一其他优点为能以执行单一制造制程(旋转涂布金属氧化沉积)来取代已知地执行三个单独的制程(氧碳化硅沉积、氧碳化硅的化学机械研磨、后续的氧碳化硅沉积)。这导致制造成本与耗时的减少。再一优点为相较于氮化硅层与氧碳化硅，介于氮化硅层(位于栅极上方)与金属氧化物之间的蚀刻选择比可增加。这帮助扩大制程视窗。
本揭露的一态样涉及制造半导体装置的方法。于基板上形成多个栅极结构。栅极结构被多个间隙所隔开。以导电材料填充间隙。于栅极结构上且于填充间隙的导电材料上形成金属氧化层。于金属氧化层上形成介电层。形成一个或多个导电接触延伸贯穿介电层且贯穿金属氧化层。
本揭露的其他态样涉及半导体装置的制造方法。于基板上形成多个高介电系数金属栅极结构。高介电系数金属栅极结构被多个间隙所隔开。高介电系数金属栅极结构各包含第一介电层于高介电系数金属栅极结构的上表面。以第一导电材料填充间隙。透过回蚀制程于各间隙中移除部分的第一导电材料。使用旋转涂布沉积制程来形成金属氧化层。于高介电系数金属栅极结构上且于第一导电材料上形成金属氧化层。于金属氧化层上形成第二介电层。在第二介电层中蚀刻开口。开口被蚀刻贯穿第二介电层且贯穿金属氧化层。以第二导电材料填充开口。
本揭露的又一其他态样涉及半导体装置。于基板上形成多个栅极结构。栅极结构被多个间隙所隔开。第一介电材料设置于基板上且部分地填充间隙。于各间隙中，导电材料设置于第一介电材料上。金属氧化材料设置于导电材料上。
以上概述了数个实施例的特征，因此熟悉此技艺者可以更了解本揭露的态样。熟悉此技艺者应了解到，其可轻易地把本揭露当作基础来设计或修改其他的制程与结构，借此实现和在此所介绍的这些实施例相同的目标及/或达到相同的优点。熟悉此技艺者也应可明白，这些等效的建构并未脱离本揭露的精神与范围，并且他们可以在不脱离本揭露精神与范围的前提下做各种的改变、替换与变动。

Claims (1)

1.一种制造半导体装置的方法，其特征在于，包含：
形成多个栅极结构于一基板上，所述多个栅极结构被多个间隙所隔开；
以一导电材料填充所述多个间隙；
形成一金属氧化层于所述多个栅极结构上且于填充所述多个间隙的该导电材料上；
形成一介电层于该金属氧化层上；以及
形成一或多个导电接触延伸贯穿该介电层且贯穿该金属氧化层。
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CN108807182B (zh) * 2017-04-28 2023-11-03 台湾积体电路制造股份有限公司 半导体装置的制造方法

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US20190131240A1 (en) 2019-05-02
TW201714209A (zh) 2017-04-16

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