CN106569775B - A kind of binary arithmetic subtraction circuit - Google Patents
A kind of binary arithmetic subtraction circuit Download PDFInfo
- Publication number
- CN106569775B CN106569775B CN201610967882.8A CN201610967882A CN106569775B CN 106569775 B CN106569775 B CN 106569775B CN 201610967882 A CN201610967882 A CN 201610967882A CN 106569775 B CN106569775 B CN 106569775B
- Authority
- CN
- China
- Prior art keywords
- logic unit
- compound logic
- drain electrode
- compound
- source electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Abstract
The invention discloses a kind of binary arithmetic subtraction circuits, and including four phase inverters and three compound logic units, three compound logic units are respectively：Compound logic unit I, compound logic unit II and meet logic unit III；Wherein, each compound logic unit is made of four NMOS transistors and four PMOS transistors；Compound logic unit I is identical with compound logic unit II structures, and realizes exclusive or function；Compound logic unit III realizes " or with non-" logic.The present invention is realized by using improved combo logic circuitry unit (I III modules as depicted), significantly reduces the number and circuit scale of MOS transistor, is very suitable for miniaturized circuit design.In addition, whole CMOS subtraction circuit disclosed by the invention is smaller in the parasitic capacitance of charge and discharge electrical nodes, power consumption is relatively low, can be used as arithmetical unit for circuits such as multidigit subtractions.
Description
Technical field
The invention belongs to technical field of integrated circuits, be related to subtraction circuit, especially a kind of low-power consumption miniaturization two into
Arithmetic subtraction circuit processed.
Background technology
Binary subtracter is the important module unit of the circuit systems such as digital integrated electronic circuit, processor.With integrated electricity
The progress of road designing technique and technology feature size, system on chip scale is increasing, area, power consumption to each modular circuit etc.
It is it is required that more stringent.A kind of basic unit of the full subtracter as arithmetical operation, be widely used it is general, however, current existing complete
Subtract device module there are the shortcomings of complicated, area is big, power consumption is high, it is particularly disadvantageous in terms of multidigit subtraction is realized in cascade.Fig. 1 institutes
What is shown is current existing subtraction circuit, and agent structure includes 38 mosfet transistors and 1 resistance altogether.On the one hand electricity
Line structure is more complicated, chip area is larger, process costs are high；On the other hand, in circuit there are quiescent current, power consumption is larger.
Shown in Fig. 2 is 1 binary system full subtracter for using traditional basic logical gate circuit design, although being realized using whole CMOS,
Agent structure includes 40 transistors, and longest signal path undergoes 6 grades of gate delays, and area, power consumption and delay are larger.
Invention content
The shortcomings that it is an object of the invention to overcome the above-mentioned prior art, provides a kind of binary arithmetic subtraction circuit.
The purpose of the present invention is achieved through the following technical solutions：
This binary arithmetic subtraction circuit, including four phase inverters and three compound logic units, described three compound
Logic unit is respectively：Compound logic unit I, compound logic unit II and meet logic unit III；Wherein, it is each compound to patrol
Unit is collected to be made of four NMOS transistors and four PMOS transistors；Compound logic unit I and compound logic unit II knots
Structure is identical, and realizes exclusive or function；Compound logic unit III realizes " or with non-" logic.
Further, above-mentioned compound logic unit I by NMOS transistor N1, N2, N3 and N4 and PMOS transistor P1, P2,
P3 and P4 compositions；The compound logic unit II by NMOS transistor N4, N5, N6 and N7 and PMOS transistor P4, P5, P6 and
P7 is formed；It is described meet logic unit III by NMOS transistor N8, N9, N10 and N11 and PMOS transistor P8, P9, P10 and
P11 is formed.
Further, more than binary arithmetic subtraction circuit further includes output Li, minuend Ai, subtrahend Bi, low level is to one's own department or unit
Borrow Si-1With one's own department or unit S is borrowed to high-orderi；Compound logic unit I realizes minuend AiWith subtrahend BiExclusive or, i.e. M=Ai⊕
Bi, wherein M is the output of compound logic unit I, and ⊕ is exclusive or；Four phase inverters are utilized respectively minuend Ai, subtrahend Bi, low level
S is borrowed to one's own department or uniti-1Inversion signal Av is generated with the output M of compound logic unit Ii、Bvi、Svi-1And Mv；Compound logic unit
II also realizes exclusive or function, generates the output L of compound logic unit IIi, and Li=M ⊕ Si-1。
Further, in above-mentioned compound logic unit I, the grid of P0 and N3 are connected to Ai, the grid of P1 and N1 is connected to Bi,
The grid of P2 and N2 is connected to Avi, the grid of P3 and N0 is connected to Bvi, wherein, AviAnd BviA is represented respectivelyiAnd BiReverse phase letter
Number；P0 and P1 source electrodes are all connected to power supply, and the drain electrode of P0 and P1 and the source electrode of P2 and P3 link together, the drain electrode of P2 and P3 and
The drain electrode of N2 and N3 is connected together as the output M of compound logic unit I；The source electrode of N0 and N1 is connected to ground, the drain electrode of N0
It is connected with the source electrode of N2, the drain electrode of N1 is connected with the source electrode of N3.
Further, the source electrode and drain electrode of any one of above-mentioned P0-P3 and N0-N3 metal-oxide-semiconductors can exchange；P0 and P1
It is connected, can exchanged with parallel way；P2 is also connected with P3 with parallel way, can be exchanged；P0 and P2/P3, P1 and P3/P2 energy
It is enough to exchange simultaneously；N0 and N2 are connected in a series arrangement, can be exchanged；N1 and N3 is also connected in a series arrangement, can be exchanged；N0 and
N1/N3, N2 and N3/N1 can be exchanged.
Further, in above-mentioned compound logic unit II, the grid of P4 and N5 are connected to Si-1, the grid of P5 and N7 is connected to
The grid of the output M, P6 and N6 of module I are connected to Svi-1, the grid of P7 and N4 is connected to Mv, wherein, Mv exports M for module I
Inversion signal；P4 and P5 source electrodes are all connected to power supply, and the drain electrode of P4 and P5 and the source electrode of P6 and P7 link together, P6 and P7
Drain electrode the output L of the logic unit is connected together as with the drain electrode of N6 and N7i；The source electrode of N4 and N5 is connected to ground, N4
Drain electrode be connected with the source electrode of N6, the drain electrode of N5 is connected with the source electrode of N7.
Further, the source electrode and drain electrode of any one of above-mentioned P4-P7 and N4-N7 metal-oxide-semiconductors can exchange；P4 and P5
It is connected, can exchanged with parallel way；P6 is also connected with P7 with parallel way, and the two can exchange；P4 and P6/P7, P5 and P7/
P6 can be exchanged simultaneously；N4 and N6 are connected in a series arrangement, can be exchanged；N5 and N7 is also connected in a series arrangement, can be mutual
It changes；N4 and N5/N7, N6 and N7/N5 can be exchanged simultaneously.
Further, in above-mentioned compound logic unit III, the grid of P8 and N10 are connected to Bvi, the grid of P9 and N9 connects
Grid to the output M, P10 and N11 of compound logic unit I is connected to Ai, the grid of P11 and N8 is connected to Svi-1, wherein,
Svi-1Represent Si-1Inversion signal；N8 and N9 source electrodes are connected to ground, and the drain electrode of N8 and N9 and the source electrode of N10 and N11 are connected to
Together, the drain electrode of N10 and N11 and the drain electrode of P10 and P11 are connected together as the output S of compound logic unit IIIi, P8 and
The source electrode of P9 is connected to power supply, and the drain electrode of P8 is connected with the source electrode of P10, and the drain electrode of P9 is connected with the source electrode of P11.
Further, any one of above-mentioned P8-P11 and N8-N11 metal-oxide-semiconductors, source electrode and drain electrode can exchange；N8
It is connected, can be exchanged with parallel way with N9；N10 is also connected with N11 with parallel way, and the two can also exchange；N8 and N10/
N11, N9 and N11/N10 can be exchanged simultaneously；P8 and P10 are connected in a series arrangement, can be exchanged；P9 and P11 is also with series connection side
Formula connects, and the two can also exchange；P8 and P9/P11, P10 and P11/P9 can be exchanged simultaneously.
Further, above-mentioned NMOS transistor uses identical size；PMOS transistor is made in same N traps, has phase
Same size, NMOS transistor and PMOS transistor take minimum dimension to be designed.
Compared with prior art, the invention has the advantages that：
Transistor size, power consumption and the transmission delay in the present invention and other structures subtracter are compared such as table first
Shown in 1, table 1 is to have carried out circuit simulation verification under 0.18 μm of CMOS technology, 1V supply voltages：
1 present invention of table is compared with the parameter of prior art construction
The present invention and the transistor size in other structures subtracter, power consumption and transmission delay are compared in table 1, compared to figure
The structure of the prior art in 1 and Fig. 2, circuit structure provided by the invention is simple, including phase inverter, it is only necessary to 32 MOS crystalline substances
Body pipe (16 PMOS transistors and 16 NMOS transistors) can be realized, and can minimum dimension be taken to be designed, phase
Than other structures, significantly improved in area and power consumption.In terms of transmission delay, although whole CMOS disclosed by the invention
Impedance of the compound logic module on charge and discharge path is higher (be two metal-oxide-semiconductors series connection), but due to node parasitic capacitance compared with
It is small, so transmission delay is smaller.The present invention reduces while simplifying circuit structure, reducing chip area, reduction production cost
Power consumption can preferably meet the needs of low-power consumption Miniaturized Integrated Circuit development.
Description of the drawings
Fig. 1 is existing binary digit subtraction circuit；
Fig. 2 is traditional subtraction circuit structure based on basic logic；
Fig. 3 minimizes subtraction circuit structure for low-power consumption disclosed by the invention；
Fig. 4 present invention discloses the simulation results of circuit.
Specific embodiment
In order to express clearer by the object, technical solutions and advantages of the present invention, below in conjunction with the accompanying drawings to the present invention
It is further described in more detail.Here, the embodiment of the present invention and explanation are only explanation of the invention, not as to this hair
Bright restriction.
Technical term explanation according to the present invention
NMOS：N-channel metal oxide semiconductor FET, N-channel MOS field
Effect transistor；
PMOS：P-channel metal oxide semiconductor FET, P-channel metal-oxide-semiconductor field
Effect transistor；
The present invention circuit structure and principle be：
Referring to Fig. 3：The binary arithmetic subtraction circuit of the present invention includes four phase inverters and three compound logic units, institute
Stating three compound logic units is respectively：Compound logic unit I, compound logic unit II and meet logic unit III；Wherein,
Each compound logic unit is made of four NMOS transistors and four PMOS transistors；It compound logic unit I and compound patrols
It is identical to collect unit II structures, and realizes exclusive or function；Compound logic unit III realizes " or with non-" logic.It is described compound to patrol
Unit I is collected to be made of NMOS transistor N1, N2, N3 and N4 and PMOS transistor P1, P2, P3 and P4；The compound logic list
First II is made of NMOS transistor N4, N5, N6 and N7 and PMOS transistor P4, P5, P6 and P7；It is described to meet logic unit
III is made of NMOS transistor N8, N9, N10 and N11 and PMOS transistor P8, P9, P10 and P11.
In addition binary arithmetic subtraction circuit of the invention further includes output Li, minuend Ai, subtrahend Bi, low level is to one's own department or unit
Borrow Si-1With one's own department or unit S is borrowed to high-orderi；Compound logic unit I realizes minuend AiWith subtrahend BiExclusive or, i.e. M=Ai⊕
Bi, wherein M is the output of compound logic unit I, and ⊕ is exclusive or；Four phase inverters are utilized respectively minuend Ai, subtrahend Bi, low level
S is borrowed to one's own department or uniti-1Inversion signal Av is generated with the output M of compound logic unit Ii、Bvi、Svi-1And Mv；Compound logic unit
II also realizes exclusive or function, generates the output L of compound logic unit IIi, and Li=M ⊕ Si-1。
The connection relation of each device of the present invention described further below：
Compound logic unit I
In compound logic unit I：The grid of P0 and N3 is connected to Ai, the grid of P1 and N1 is connected to Bi, the grid of P2 and N2
It is connected to Avi, the grid of P3 and N0 is connected to Bvi, wherein, AviAnd BviA is represented respectivelyiAnd BiInversion signal；P0 and P1 sources
Pole is all connected to power supply, and the drain electrode of P0 and P1 and the source electrode of P2 and P3 link together, the leakage to drain with N2 and N3 of P2 and P3
Pole is connected together as the output M of compound logic unit I；The source electrode of N0 and N1 is connected to ground, the drain electrode of N0 and the source electrode of N2
It is connected, the drain electrode of N1 is connected with the source electrode of N3.Wherein：The source electrode and drain electrode of any one of P0-P3 and N0-N3 metal-oxide-semiconductor
It can exchange；P0 is connected with P1 with parallel way, can be exchanged；P2 is also connected with P3 with parallel way, can be exchanged；P0 and
P2/P3, P1 and P3/P2 can be exchanged simultaneously；N0 and N2 are connected in a series arrangement, can be exchanged；N1 and N3 is also in a series arrangement
Connection, can exchange；N0 and N1/N3, N2 and N3/N1 can be exchanged.
Compound logic unit II
In compound logic unit II, the grid of P4 and N5 are connected to Si-1, the grid of P5 and N7 is connected to the output of module I
The grid of M, P6 and N6 are connected to Svi-1, the grid of P7 and N4 is connected to Mv, wherein, Mv is the inversion signal that module I exports M；
P4 and P5 source electrodes are all connected to power supply, and the drain electrode of P4 and P5 and the source electrode of P6 and P7 link together, the drain electrode of P6 and P7 and N6
Drain electrode with N7 is connected together as the output L of the logic uniti；The source electrode of N4 and N5 is connected to ground, the drain electrode of N4 and N6
Source electrode be connected, the drain electrode of N5 is connected with the source electrode of N7.Wherein, the source electrode of any one of P4-P7 and N4-N7 metal-oxide-semiconductor
It can be exchanged with drain electrode；P4 is connected with P5 with parallel way, can be exchanged；P6 is also connected with P7 with parallel way, and the two can
It exchanges；P4 and P6/P7, P5 and P7/P6 can be exchanged simultaneously；N4 and N6 are connected in a series arrangement, can be exchanged；N5 and N7 also with
Series system connects, can be interchangeable；N4 and N5/N7, N6 and N7/N5 can be exchanged simultaneously.
Compound logic unit III
In compound logic unit III, the grid of P8 and N10 are connected to Bvi, the grid of P9 and N9 is connected to compound logic list
The grid of the output M, P10 and N11 of first I are connected to Ai, the grid of P11 and N8 is connected to Svi-1, wherein, Svi-1Represent Si-1's
Inversion signal；N8 and N9 source electrodes are connected to ground, and the drain electrode of N8 and N9 and the source electrode of N10 and N11 link together, N10 and N11
Drain electrode the output S of compound logic unit III is connected together as with the drain electrode of P10 and P11i, the source electrode of P8 and P9 connects
To power supply, the drain electrode of P8 is connected with the source electrode of P10, and the drain electrode of P9 is connected with the source electrode of P11.Wherein, P8-P11 and N8-N11
Any one of metal-oxide-semiconductor, source electrode and drain electrode can exchange；N8 is connected with N9 with parallel way, can be exchanged；N10 and N11
Also it is connected with parallel way, the two can also exchange；N8 and N10/N11, N9 and N11/N10 can be exchanged simultaneously；P8 and P10 with
Series system connects, and can exchange；P9 and P11 is also connected in a series arrangement, and the two can also exchange；P8 and P9/P11, P10 and
P11/P9 can be exchanged simultaneously.
All transistors of the above-mentioned subtraction circuit of the present invention take same manufacture craft, wherein, NMOS transistor
With identical size, PMOS transistor is made in same N traps, is of the same size, and all MOS transistors can be taken most
Small size is designed.
It can to sum up obtain：Li=Ai⊕Bi⊕Si-1, Si=Avi Bi+(Ai⊙Bi)Si-1.Wherein, " ⊙ " represents inclusive OR logic.
Therefore, LiAnd SiSame Ai、Bi、Si-1Relationship between three inputs is as shown in table 2, realizes 1 binary system and subtracts function entirely.
2 circuit input/output relation of the present invention of table
With reference to Fig. 3, based on 0.18 μm of CMOS technology, circuit simulation, circuit of the present invention have been carried out under 1.0V supply voltages
Input-output wave shape as shown in figure 4, consistent with the theoretical analysis result in table 2.
The present invention provides a kind of binary arithmetic powered down roads entirely, and not only device count is few, but also all metal-oxide-semiconductors can all be adopted
Minimum dimension is taken to be designed, chip area can be reduced, reduce cost.In addition, it is realized with traditional basic logic gate circuit
Method and current existing circuit are compared, and circuit disclosed by the invention takes whole CMOS compound logic module to realize, have compared with
Low dynamic power consumption.Fig. 3 shows 1 binary subtraction circuit embodiments of the invention, circuit structure and original based on the present invention
Reason extends multidigit powered down road entirely by cascade, the design of design cycle, operation principle and transistor size with the present invention
1 embodiment it is identical, with the increase of series, power consumption of the invention and area advantage can be more obvious.
The above is presently preferred embodiments of the present invention, is not intended to limit the invention, it is every the present invention spirit and
Within spirit, any equivalent replacement, retouching and improvement for being made etc. are regarded as protection scope of the present invention.
Claims (5)
1. a kind of binary arithmetic subtraction circuit, which is characterized in that including four phase inverters, output Li, minuend Ai, subtrahend Bi、
Low level borrows S to one's own department or uniti-1, one's own department or unit borrow S to high-orderiWith three compound logic units, three compound logic units
Respectively：Compound logic unit I, compound logic unit II and compound logic unit III；Wherein, each compound logic unit is equal
It is made of four NMOS transistors and four PMOS transistors；Compound logic unit I is identical with compound logic unit II structures, and
Realize exclusive or function；Compound logic unit III realizes " or with non-" logic；
The compound logic unit I is made of NMOS transistor N1, N2, N3 and N4 and PMOS transistor P1, P2, P3 and P4；
The compound logic unit II is made of NMOS transistor N4, N5, N6 and N7 and PMOS transistor P4, P5, P6 and P7；It is described
Meet logic unit III to be made of NMOS transistor N8, N9, N10 and N11 and PMOS transistor P8, P9, P10 and P11；
Compound logic unit I realizes minuend AiWith subtrahend BiExclusive or, i.e. M=Ai⊕Bi, wherein M is the defeated of compound logic unit I
Go out, ⊕ is exclusive or；Four phase inverters are utilized respectively minuend Ai, subtrahend Bi, low level borrow S to one's own department or uniti-1With compound logic list
The output M of first I generates inversion signal Avi、Bvi、Svi-1And Mv；Compound logic unit II also realizes exclusive or function, generates compound patrol
Collect the output L of unit IIi, and Li=M ⊕ Si-1；
In compound logic unit I, the grid of P0 and N3 are connected to Ai, the grid of P1 and N1 is connected to Bi, the grid of P2 and N2 connects
To Avi, the grid of P3 and N0 is connected to Bvi, wherein, AviAnd BviA is represented respectivelyiAnd BiInversion signal；P0 and P1 parallel connections connect
It connects, P0 and P1 source electrodes are all connected to power supply, and the drain electrode of P0 and P1 and the source electrode of P2 and P3 link together, P2 and P3 parallel connections connect
It connects, the drain electrode to drain with N2 and N3 of P2 and P3 are connected together as the output M of compound logic unit I；The source electrode of N0 and N1
Ground is connected to, the drain electrode of N0 is connected with the source electrode of N2, and the drain electrode of N1 is connected with the source electrode of N3, and N0 and N2 are connected in a series arrangement,
N1 and N3 are connected in a series arrangement；
In the compound logic unit II, P4 is connected with P5 with parallel way, and P6 is connected with P7 with parallel way, the grid of P4 and N5
Extremely it is connected to Si-1, the grid of output M, P6 and N6 that the grid of P5 and N7 are connected to module I is connected to Svi-1, the grid of P7 and N4
Mv is extremely connected to, wherein, Mv is the inversion signal that module I exports M；P4 and P5 source electrodes are all connected to power supply, the drain electrode of P4 and P5
It links together with the source electrode of P6 and P7, the drain electrode and the drain electrode of N6 and N7 of P6 and P7 are connected together as the logic unit
Export Li；N4 and N6 are connected in a series arrangement, and N5 and N7 are connected in a series arrangement, and the source electrode of N4 and N5 are connected to ground, the leakage of N4
Pole is connected with the source electrode of N6, and the drain electrode of N5 is connected with the source electrode of N7；
In the compound logic unit III, the grid of P8 and N10 are connected to Bvi, the grid of P9 and N9 is connected to compound logic list
The grid of the output M, P10 and N11 of first I are connected to Ai, the grid of P11 and N8 is connected to Svi-1, wherein, Svi-1Represent Si-1's
Inversion signal；N8 is connected with N9 with parallel way, and N10 is connected with N11 with parallel way, N8 and N9 source electrodes are connected to ground, N8
Drain electrode and the source electrode of N10 and N11 with N9 link together, and the drain electrode and the drain electrode of P10 and P11 of N10 and N11 link together
Output S as compound logic unit IIIi, P8 and P10 connect in a series arrangement, and the source electrode of P8 and P9 are connected to power supply, P8's
Drain electrode is connected with the source electrode of P10, and P9 and P11 are connected in a series arrangement, and the drain electrode of P9 is connected with the source electrode of P11.
2. binary arithmetic subtraction circuit according to claim 1, which is characterized in that in the P0-P3 and N0-N3
The source electrode and drain electrode of any one metal-oxide-semiconductor can exchange；P0 is connected with P1 with parallel way, can be exchanged；P2 and P3 is also with simultaneously
Connection mode connects, and can exchange；P0 and P2/P3, P1 and P3/P2 can be exchanged simultaneously；N0 and N2 are connected in a series arrangement, can
It exchanges；N1 and N3 is also connected in a series arrangement, can be exchanged；N0 and N1/N3, N2 and N3/N1 can be exchanged.
3. binary arithmetic subtraction circuit according to claim 1, which is characterized in that in the P4-P7 and N4-N7
The source electrode and drain electrode of any one metal-oxide-semiconductor can exchange；P4 is connected with P5 with parallel way, can be exchanged；P6 and P7 is also with simultaneously
Connection mode connects, and the two can exchange；P4 and P6/P7, P5 and P7/P6 can be exchanged simultaneously；N4 and N6 are connected in a series arrangement,
It can exchange；N5 and N7 is also connected in a series arrangement, can be interchangeable；N4 and N5/N7, N6 and N7/N5 can be exchanged simultaneously.
4. binary arithmetic subtraction circuit according to claim 1, which is characterized in that in the P8-P11 and N8-N11
Any one metal-oxide-semiconductor, source electrode and drain electrode can exchange；N8 is connected with N9 with parallel way, can be exchanged；N10 and N11
It is connected with parallel way, the two can also exchange；N8 and N10/N11, N9 and N11/N10 can be exchanged simultaneously；P8 and P10 is to go here and there
Connection mode connects, and can exchange；P9 and P11 is also connected in a series arrangement, and the two can also exchange；P8 and P9/P11, P10 and
P11/P9 can be exchanged simultaneously.
5. the binary arithmetic subtraction circuit according to claim 1-, which is characterized in that the NMOS transistor uses
Identical size；PMOS transistor is made in same N traps, is of the same size, and NMOS transistor and PMOS transistor are adopted
Minimum dimension is taken to be designed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610967882.8A CN106569775B (en) | 2016-11-04 | 2016-11-04 | A kind of binary arithmetic subtraction circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610967882.8A CN106569775B (en) | 2016-11-04 | 2016-11-04 | A kind of binary arithmetic subtraction circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106569775A CN106569775A (en) | 2017-04-19 |
| CN106569775B true CN106569775B (en) | 2018-07-06 |
Family
ID=58539755
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610967882.8A Active CN106569775B (en) | 2016-11-04 | 2016-11-04 | A kind of binary arithmetic subtraction circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106569775B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5847983A (en) * | 1995-08-24 | 1998-12-08 | Matsushita Electric Industrial Co., Ltd. | Full subtracter |
| CN103699353A (en) * | 2013-12-05 | 2014-04-02 | 西安交通大学 | One-bit full subtracter circuit |
-
2016
- 2016-11-04 CN CN201610967882.8A patent/CN106569775B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5847983A (en) * | 1995-08-24 | 1998-12-08 | Matsushita Electric Industrial Co., Ltd. | Full subtracter |
| CN103699353A (en) * | 2013-12-05 | 2014-04-02 | 西安交通大学 | One-bit full subtracter circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106569775A (en) | 2017-04-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Bazzazi et al. | Design and Implementation of Full Adder Cell with the GDI Technique Based on 0.18 µm CMOS Technology | |
| Chong et al. | A micropower low-voltage multiplier with reduced spurious switching | |
| Vijay et al. | Design of unbalanced ternary logic gates and arithmetic circuits | |
| Nishad et al. | Analysis of low power high performance XOR gate using GDI technique | |
| CN106569775B (en) | A kind of binary arithmetic subtraction circuit | |
| Lee et al. | A 4-bit CMOS full adder of 1-bit hybrid 13T adder with a new SUM circuit | |
| Janwadkar et al. | Design and performance evaluation of hybrid full adder for extensive PDP reduction | |
| Devadas et al. | Design topologies for low power cmos full adder | |
| Verma et al. | New high performance 1-bit full adder using domino logic | |
| US11169779B2 (en) | Full adder cell with improved power efficiency | |
| CN210120546U (en) | CMOS (complementary Metal oxide semiconductor) combinational logic circuit | |
| CN102571071B (en) | Single electron transistor (SET)/metal oxide semiconductor (MOS) mixed structure multiplier unit based on threshold logic | |
| CN111313890B (en) | High-performance approximate full adder gate-level unit | |
| Sahoo et al. | Study of Different Adders Using Full Swing Gate Diffusion Input | |
| CN202435379U (en) | SET/MOS (single-electron transistor/ Metal Oxide Semiconductor) mixed structure multiplier unit based on threshold logic | |
| Rafik et al. | Design and analysis of XOR-XNOR Circuit based Modified Hybrid Full Adder | |
| CN114710150B (en) | CMOS full adder | |
| CN102545881B (en) | Semiconductor field-effect transistor/metal-oxide-semiconductor (SET/MOS) mixed structure 2-bit multiplier based on threshold logic | |
| Maniusha et al. | Low Power and Area Efficieny ALU With Different Type of Low Power in Full Adders | |
| CN202453865U (en) | Threshold logic-based SET/MOS hybrid structure 2 bit multiplier | |
| Mangalam et al. | Design of Energy Efficient Hybrid Logic Full Adders | |
| CN102611429A (en) | Summing device of SET/MOS (Single Electron Transistor/Metal Oxide Semiconductor) mixed structure based on threshold logic | |
| Ghabri et al. | Performance evaluation of reconfigurable ALU based on DG-CNTFET transistors | |
| DK et al. | VLSI Implementation of Braun Multiplier using Full Adder | |
| Kandpal et al. | High performance 20-T based hybrid full adder using 90nm CMOS technology |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |