CN102611429A - Summing device of SET/MOS (Single Electron Transistor/Metal Oxide Semiconductor) mixed structure based on threshold logic - Google Patents
Summing device of SET/MOS (Single Electron Transistor/Metal Oxide Semiconductor) mixed structure based on threshold logic Download PDFInfo
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Abstract
The invention relates to the technical field of an integrated circuit, in particular to a summing device of an SET/MOS (Single Electron Transistor/Metal Oxide Semiconductor) mixed structure based on threshold logic, which is only formed by two threshold logic gates and one phase inverter; and three PMOS (P-channel Metal Oxide Semiconductor) tubes, three NMOS (N-channel Metal Oxide Semiconductor) tubes and three SETs are consumed. Input and output voltages have better compatibility and an output voltage swing is 0.67 V, so as to be good for driving the next grade of the circuit and carry out integrated design with other circuits. The average power consumption of the whole circuit is only 20 nW. Compared with the traditional summing device based on a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) technology, the power consumption of the circuit is obviously reduced and the quantity of tubes is certainly reduced; and therefore, the structure of the circuit is further simplified. The summing device can be used as a basic arithmetic unit and is applied in systems including a digital signal processor, a microprocessor, a microcontroller, a memorizer and the like, so as to be good for reducing the power consumption of the circuit, saving a chip area and improving the integrated level of the circuit.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly a kind of adder of forming by nano-device based on the SET/MOS mixed structure of voting logic.
Background technology
Adder is applied in the critical path of circuit such as digital signal processor, microprocessor, microcontroller, memory as the most basic a kind of ALU usually.The performance of adder has very big influence for the performance of entire circuit.Along with development of semiconductor, integrated circuit develops by leaps and bounds towards the direction of high integration, low-power consumption.Traditional adder based on the CMOS technology need consume bigger power consumption, and circuit structure is comparatively complicated, and integrated level is not high, can not satisfy the requirement of new capability.
Summary of the invention
The purpose of this invention is to provide a kind of adder of the SET/MOS mixed structure based on voting logic, can realize the addition of binary number, output with and carry.
The present invention adopts following scheme to realize: a kind of adder of the SET/MOS mixed structure based on voting logic is characterized in that: comprise one three input Threshold Logic Gate, four an input Threshold Logic Gate and inverters; Three inputs of said three input Threshold Logic Gate and first, second and third input of said four input Threshold Logic Gate link together in twos, and the output of said three input Threshold Logic Gate is connected with the four-input terminal of said four input Threshold Logic Gate, the input of inverter; Said three, four input Threshold Logic Gate are made up of the SET/MOS hybrid circuit, and its threshold value is 1.5, and its output logic is to calculate total input value according to the weighted value of importing; And total input value and said threshold value compared; More than or equal to said threshold value, then be output as 1, otherwise be output as 0.
In an embodiment of the present invention, the voting logic of said three, four input Threshold Logic Gate satisfies logical equation:
Wherein
W iBe input
X iCorresponding weight,
nBe the number of input,
θBe threshold value.
In an embodiment of the present invention, described inverter is made up of the SET/MOS hybrid circuit of single-ended input.
In an embodiment of the present invention, described SET/MOS hybrid circuit comprises: PMOS pipe, its source electrode connects power end
V DdOne NMOS pipe, its drain electrode is connected with the drain electrode of said PMOS pipe; And a SET pipe, it is connected with source electrode that said NMOS manages.
In an embodiment of the present invention, the parameter of said PMOS pipe satisfies: channel width
W pBe 22 nm, channel length
L pBe 66 nm, grid voltage
V PgBe 0.4 V; The parameter of said NMOS pipe satisfies: channel width
W nBe 22 nm, channel length
L nBe 66 nm, grid voltage
V NgBe 0.4 V; The parameter of said SET pipe satisfies: tunnel junctions electric capacity
C s,
C dBe 0.1 aF, tunnel junctions resistance
R s,
R dBe 150 K Ω, back gate voltage
V CtrlBe 0.8 V, back of the body gate capacitance
C CtrlBe 0.1 aF, gate coupled electric capacity
C 1Be 0.033 aF, gate coupled electric capacity
C 2Be 0.02 aF.
Coulomb blockade oscillation effect and multiple-grid input characteristics that the present invention utilizes SET to have, and the characteristics compatible mutually with metal-oxide-semiconductor have realized the adder based on the SET/MOS mixed structure of voting logic.Because the powerful logic function of voting logic, this circuit only is made up of 2 Threshold Logic Gate and 1 inverter, consumes 3 PMOS pipes altogether, 3 NMOS pipes and 3 SET.The average power consumption of entire circuit is merely 20nW.The input and output voltage of this adder has compatible preferably, has bigger output voltage swing (0.67V), helps driving the circuit of next stage, can carry out integrated design with other circuit.Compare with traditional adder based on the CMOS technology, the power consumption of this adder obviously descends, and number of tubes has obtained certain minimizing, and circuit structure has obtained further simplification.This adder can be as a basic arithmetical unit, and at digital signal processor, microprocessor is applied in the systems such as microcontroller and memory, helps reducing circuit power consumption, saves chip area, improves the integrated level of circuit.
Description of drawings
Fig. 1 is multiple-grid input SET/MOS hybrid circuit schematic diagram.
Fig. 2 is the SET/MOS mixed structure
V In-
V OutCharacteristic curve.
Fig. 3 a is the schematic diagram of SET/MOS mixed structure adder.
Fig. 3 b is three input SET/MOS mixed structure circuit theory diagrams.
Fig. 3 c is four input SET/MOS mixed structure circuit theory diagrams.
Fig. 4 is the simulated properties curve of SET/MOS mixed structure adder.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is further specified.
Shown in Fig. 3 a, the present invention provides a kind of adder of the SET/MOS mixed structure based on voting logic, it is characterized in that: comprise one three input Threshold Logic Gate, four an input Threshold Logic Gate and inverters; Three inputs of said three input Threshold Logic Gate and first, second and third input of said four input Threshold Logic Gate link together in twos, and the output of said three input Threshold Logic Gate is connected with the four-input terminal of said four input Threshold Logic Gate, the input of inverter; Said three, four input Threshold Logic Gate are made up of the SET/MOS hybrid circuit, and its threshold value is 1.5, and its output logic is to calculate total input value according to the weighted value of importing; And total input value and said threshold value compared; More than or equal to said threshold value, then be output as 1, otherwise be output as 0.
Specifically, the present invention adopts single-electronic transistor (Single electron transistor SET) carries out the design of adder with the mode that metal-oxide-semiconductor mixes mutually.As typical case's representative of nano electron device of new generation, SET has extra small device size and ultralow circuit power consumption, and being expected to substitute cmos device becomes manufacturing low-power consumption of future generation, the desirable basic device of high density very lagre scale integrated circuit (VLSIC).Single-electronic transistor can be compatible mutually with the CMOS silicon technology, and the SET/MOS hybrid circuit possesses the superior function of SET and metal-oxide-semiconductor, shows extremely low power consumption, extra small device size, stronger driving force and bigger output voltage swing.Simultaneously, the SET/MOS hybrid circuit can not followed traditional method for designing based on Boolean logic, carries out the design of circuit and adopt based on the method for voting logic.The logical process of voting logic is more complicated than Boolean logic, can more effectively realize logic function.Therefore,, be expected to the function of further intensifier circuit, improve the integrated level of circuit based on the method for designing of the SET/MOS mixed structure of voting logic.
The realization of voting logic of the present invention mainly is that the weight calculation according to input goes out total input value, total input value and threshold value is compared draw output logic.If total input value then is output as 1, otherwise is 0 more than or equal to threshold value.The logical equation that voting logic will satisfy is suc as formula shown in (1), and wherein n is the number of input,
W iBe input
X iCorresponding weight,
θBe threshold value.To confirm at first that based on the circuit design of voting logic the voting logic expression formula of circuit, key are to confirm the weight of each input in the circuit and the threshold value of circuit.
(1)
Adder can realize the addition of binary number as basic arithmetic element, output and and carry.The present invention designed is 1 adder, input be designated as (
a,
b,
c i), be output as (
s,
c o).The logic that input and output need be satisfied is suc as formula (2), shown in (3).The method of employing spectral coefficient can be with output
s,
c oBe rewritten as the voting logic expression formula suc as formula (4), shown in (5), wherein
c o' do
c oThe logic negate.
The present invention adopts the SET/MOS hybrid circuit of multiple-grid input to realize the voting logic function, and its structure is as shown in Figure 1.This circuit is managed by 1 PMOS, and the SET of 1 NMOS pipe and 1 multiple-grid input is in series.The PMOS pipe is that entire circuit provides bias current as constant-current source in the circuit.Because the electric current of SET operate as normal is all very little, is generally the nA order of magnitude, so the PMOS pipe should be operated in sub-threshold region.The grid bias of NMOS pipe
V NgFix, its value is slightly larger than the threshold voltage of NMOS pipe
V Th, the drain voltage of SET is fixed as
V Ng-
V ThGrid voltage
V 1,
V 2...,
V nBe capacitively coupled on the Coulomb island.The input coupling capacitance has been formed a capacitor array and has been used to calculate total input voltage.According to the definition of voting logic, just can obtain corresponding output logic with circuit threshold value through more total input voltage.When total input voltage during, be output as high level (logical one) greater than threshold value; When total input voltage during, be output as low level (logical zero) less than threshold value.Through suitable circuit parameter is set, the input and output that the SET/MOS hybrid circuit is corresponding (
V In-
V Out) characteristic curve is as shown in Figure 2.
V OutAlong with
V InVariation and change.When input voltage surpassed certain numerical value (like the 400mV among Fig. 2), output realized the saltus step of from the high level to the low level (low level is to high level).This numerical value is the threshold value of circuit.Through the biasing SET back gate voltage (
V Ctrl), just can obtain different threshold values.Therefore the SET/MOS hybrid circuit of this multiple-grid input can be realized different voting logic functions.
Please continue a with reference to Fig. 3, circuit of the present invention only is made up of 2 Threshold Logic Gate and 1 inverter, and wherein inverter is made up of the SET/MOS hybrid circuit of single-ended input.With
sRealize carry by 1 Threshold Logic Gate (TLG2)
c oRealize by 1 Threshold Logic Gate (TLG1) and an inverter.The circuit diagram of TLG1 and TLG2 such as Fig. 3 b are shown in Fig. 3 c.
The present invention adopts the method for SET and metal-oxide-semiconductor hybrid simulation, utilizes the HSPICE simulator that the adder that the present invention proposes has been carried out the function simulating checking.The model of SET is the macro model (Compact macromodel) widely-used at present, that precision is high.This model with the formal definition of electronic circuit in SPICE.The model of metal-oxide-semiconductor uses the Predicting Technique model (Predictive technology model) of 22 nm that generally acknowledge at present.In this adder circuit, except unit input coupling capacitance (
C 1,
C 2) outside, two Threshold Logic Gate have identical simulation parameter, wherein
C 1Corresponding to TLG1,
C 2Corresponding to TLG2.In circuit, supply voltage
V DdBe set to 0.80V, the breadth length ratio of PMOS pipe and NMOS pipe (
W/
L) all being made as 1/3, main circuit simulation parameter is as shown in table 1.
Table 1
The characteristic curve that emulation obtains is as shown in Figure 4.Input signal
a,
b,
c i All be made as square wave, added waveform satisfies 8 kinds of logical combinations of three inputs, and the high-low level of input is respectively 0.8V and 0V.The output waveform that emulation obtains
FBe low level and high level with 0.07 V and 0.74 V respectively.As can be seen from the figure, this circuit can be realized the function of adder.
The above is merely preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (5)
1. the adder based on the SET/MOS mixed structure of voting logic is characterized in that: comprise one three input Threshold Logic Gate, four an input Threshold Logic Gate and inverters; Three inputs of said three input Threshold Logic Gate and first, second and third input of said four input Threshold Logic Gate link together in twos, and the output of said three input Threshold Logic Gate is connected with the four-input terminal of said four input Threshold Logic Gate, the input of inverter; Said three, four input Threshold Logic Gate are made up of the SET/MOS hybrid circuit, and its threshold value is 1.5, and its output logic is to calculate total input value according to the weighted value of importing; And total input value and said threshold value compared; More than or equal to said threshold value, then be output as 1, otherwise be output as 0.
2. the adder of the SET/MOS mixed structure based on voting logic according to claim 1 is characterized in that: the voting logic of said three, four input Threshold Logic Gate satisfies logical equation:
Wherein
W iBe input
X iCorresponding weight,
nBe the number of input,
θBe threshold value.
3. the adder of the SET/MOS mixed structure based on voting logic according to claim 1, it is characterized in that: described inverter is made up of the SET/MOS hybrid circuit of single-ended input.
4. according to the adder of claim 1 or 3 described SET/MOS mixed structures based on voting logic, it is characterized in that: described SET/MOS hybrid circuit comprises:
One PMOS pipe, its source electrode connects power end
V Dd
One NMOS pipe, its drain electrode is connected with the drain electrode of said PMOS pipe; And
One SET pipe, its source electrode with said NMOS pipe is connected.
5. the adder of the SET/MOS mixed structure based on voting logic according to claim 4 is characterized in that: the parameter of said PMOS pipe satisfies: channel width
W pBe 22 nm, channel length
L pBe 66 nm, grid voltage
V PgBe 0.4 V; The parameter of said NMOS pipe satisfies: channel width
W nBe 22 nm, channel length
L nBe 66 nm, grid voltage
V NgBe 0.4 V; The parameter of said SET pipe satisfies: tunnel junctions electric capacity
C s,
C dBe 0.1 aF, tunnel junctions resistance
R s,
R dBe 150 K Ω, back gate voltage
V CtrlBe 0.8 V, back of the body gate capacitance
C CtrlBe 0.1 aF, gate coupled electric capacity
C 1Be 0.033 aF, gate coupled electric capacity
C 2Be 0.02 aF.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103279322A (en) * | 2013-06-13 | 2013-09-04 | 福州大学 | Threshold logic type carry look ahead adder formed by SET/MOS mixing circuit |
| CN109962707A (en) * | 2019-04-16 | 2019-07-02 | 深圳市致宸信息科技有限公司 | A kind of CMOS combinational logic circuit |
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| US6215159B1 (en) * | 1997-03-26 | 2001-04-10 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device |
| CN102301325A (en) * | 2009-01-27 | 2011-12-28 | 吉林克斯公司 | Digital signal processing block with preadder stage |
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2012
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| US6215159B1 (en) * | 1997-03-26 | 2001-04-10 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device |
| CN102301325A (en) * | 2009-01-27 | 2011-12-28 | 吉林克斯公司 | Digital signal processing block with preadder stage |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103279322A (en) * | 2013-06-13 | 2013-09-04 | 福州大学 | Threshold logic type carry look ahead adder formed by SET/MOS mixing circuit |
| CN103279322B (en) * | 2013-06-13 | 2016-01-13 | 福州大学 | The threshold logic type carry lookahead adder that SET/MOS hybrid circuit is formed |
| CN109962707A (en) * | 2019-04-16 | 2019-07-02 | 深圳市致宸信息科技有限公司 | A kind of CMOS combinational logic circuit |
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