CN106558505B - 设置有整体传导接线的电子器件及其制造方法 - Google Patents

设置有整体传导接线的电子器件及其制造方法 Download PDF

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Publication number
CN106558505B
CN106558505B CN201610109735.7A CN201610109735A CN106558505B CN 106558505 B CN106558505 B CN 106558505B CN 201610109735 A CN201610109735 A CN 201610109735A CN 106558505 B CN106558505 B CN 106558505B
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package block
integrated circuit
circuit chip
additional
support substrate
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CN106558505A (zh
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Y·因布斯
L·施瓦茨
D·奥彻雷
L·马雷夏尔
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STMicroelectronics International NV
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STMicroelectronics Grenoble 2 SAS
STMicroelectronics Alps SAS
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  • Engineering & Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
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Abstract

一种电子器件，包括具有前安装面并且包括电连接网络的支撑衬底。集成电路芯片安装到所述安装面上并且电连接到所述电连接网络。主封装块嵌入有集成电路芯片并且在所述支撑衬底的所述安装面上的集成电路芯片上方且围绕其进行延伸。在主封装块中提供开口从而至少部分地不遮盖电触头。从导电材料制成的附加接线具有电连接到电触头的端部。在主封装块上方的附加封装块嵌入有附加接线。

Description

设置有整体传导接线的电子器件及其制造方法
相关申请与交叉引用
本申请要求对提交于2015年9月30日的法国专利申请No.1559251的优先权，其披露通过引用而并入。
技术领域
本发明涉及电子器件领域。
背景技术
已知的电子器件，通常具有平行六面体的形状，包括包含电连接网络的支撑衬底，安装在支撑衬底的面中的一个上的集成电路芯片以及其中嵌入有芯片的封装块。芯片通过诸如布置在支撑衬底和芯片之间的焊球的电连接元件，或者通过嵌入在封装块中的电连接接线连接到支撑衬底的网络。
这种电子器件通常经由连接着支撑衬底的电连接网络和印刷电路板的电连接网络的诸如焊球的电连接元件而安装在印刷电路板上。
当芯片生成将被传送的射频信号或者处理接收到的射频信号时，在印刷电路板上制造发送或接收天线。电信号跟随非常长的电阻路径，其包括印刷电路板的电连接网络的线、在印刷电路板和支撑衬底之间的电连接元件、支撑衬底的电连接网络的线以及在支撑衬底之间的电连接元件。这种路径同样取决于制造过程所导致的互连的质量。
上述的安排造成了不利之处，明显地当用于在数量级为1GHz及其上以及甚至远高于1GHz的频率处的射频信号的传输的天线的必要尺寸较小时。
发明内容
提出了一种电子器件，其包括具有前安装面并且包括电连接网络的支撑衬底，以及至少一个集成电路芯片，安装在所述支撑衬底的所述安装面上并且电连接到所述电连接网络。
该器件还包括封装块，其包括主封装块，其中嵌入有芯片并且在所述支撑衬底的所述安装面上的芯片上方且围绕其进行延伸，以及在主封装块上方的附加封装块。
所述器件进一步包括至少一个附加接线，其从嵌入在所述附加封装块中的导电材料制成，所述附加传导接线电连接到所述芯片以及/或所述电连接网络。
附加传导接线的端部中的至少一个可以在距芯片的***一距离处连接到所述支撑衬底的所述安装面上的至少一个电触头。
附加传导接线的端部中的至少一个可以连接到在所述芯片的前面上的至少一个电触头。
器件可以包括在所述支撑衬底的所述安装面上的电触头上方的柱体，其通过所述主封装块，所述附加传导接线的一个端部固定到这个柱体。
器件可以包括在所述芯片的前面上的电触头上方的柱体，其通过所述主封装块，所述附加传导接线的一个端部固定到这个柱体。
所述附加接线的端部中的一个可以固定到所述主封装块。
所述附加传导接线可以构成无线电天线或电连接。
还提供了一种制造电子器件的方法，其中获得了主电子器件，其包括支撑衬底，安装在支撑衬底的前安装面上的集成电路芯片，以及在所述支撑衬底的所述安装面上的芯片上方且围绕其进行延伸的主封装块，封装块具有与支撑衬底相平行的前面。
所述方法包括制作至少一个通过主电子器件的所述主封装块的孔，从其前面开始，一直到有至少部分未覆盖的所述支撑衬底的所述安装面和/或芯片的前面的电触头；将至少一个附加导电接线装配在主封装块上方并且其位置使得这个附加接线的端部中的一个连接到所述电触头；并且在所述主电子器件的所述主封装块上制造附加封装块，附加传导接线被嵌入在这个附加封装块中。
该方法可以包括：在所述孔中制作由导电材料制成的柱体；并且将附加传导接线的一个端部固定到这个柱体。
该方法可以包括：将附加传导接线的端部中的至少一个直接固定到所述电触头上方。
该方法可以包括：将附加传导接线的端部中的一个固定到所述主封装块。
附图说明
现在通过由附图所示出的实施例对电子器件及其制造方法进行描述，其中：
图1表示了电子器件的横截面；
图2描述了来自图1的电子器件的顶视图；
图3以横截面表示了来自图1的电子器件的制造中的步骤；
图4以横截面表示了来自图1的电子器件的制造中的另一个步骤；
图5以横截面表示了来自图1的电子器件的制造中的另一个步骤；
图6以横截面表示了来自图1的电子器件的制造中的另一个步骤；
图7以横截面表示了来自图1的电子器件的制造中的另一个步骤；
图8表示了另一个电子器件的横截面；
图9表示了另一个电子器件的横截面；并且
图10表示了另一个电子器件的横截面。
具体实施方式
如图1和图2所示出的，根据一个实施例，一种最终的电子器件1包括包含有集成电连接网络3的支撑衬底2，安装在支撑衬底2的前安装面5上的集成电路芯片4，以及在支撑衬底2的安装面5上的芯片4上方并且围绕其的最终封装块6，因此电子器件1采取了平行六面体的形状。
根据所提出的一个变形的实施例，借助有选择地连接芯片4和电连接网络3的诸如焊球的电连接元件7，集成电路芯片4被安装在支撑衬底2的安装面5上。根据另一个变形的实施例，芯片4可以被胶合到支撑衬底2的安装面5并且通过嵌入在封装块6中的电连接接线而连接到电连接网络3。
封装块6包括其中嵌入有芯片4并且在支撑衬底2的安装面5上的芯片4上方并且围绕其进行延伸的主封装块8，从而使得前面9与支撑衬底2平行。
主封装块8具有从前面9延伸通过其的孔10和孔11，安排在网络3的前电触头12和前电触头13上方，安排在支撑衬底2的前面5上，距离芯片4有一距离。通孔10和通孔11例如安排在芯片4的任意侧。
通孔10和通孔11包含形成在电触头12和电触头13上并且具有前面16和前面17的金属电连接柱体14和金属电连接柱体15。
最终的封装块6包括在主封装块8的顶部上的附加封装块18，遮盖主封装块8的前面9以及传导柱体14和传导柱体15的前面16和前面17，这个附加封装块18具有平行于衬底板的前面19。
最终的电子器件1进一步包括集成的附加电接线20，其嵌入在附加封装块18中并且具有通过将其分别焊接到柱体14和柱体15的前面16和前面17而固定的端部21和端部22。电接线20在最终封装块6的界面9和前面19之间且有一距离处延伸。
电子器件1可以具有外部的电子连接元件23，诸如焊球，其放置在布置在与安装面5相对的支撑衬底2的后面25上的电连接网络3的电触头24上。
电子器件1可以用下述的方式进行制造，利用了在微电子学中采用的惯用手段。
如图3所示出的，获得了预先制备的主电子器件26，其包括提供有集成连接网络3的支撑衬底2，芯片4，连接元件7和主封装块8。
如图4所示出的，制造通过主封装块8的孔10和孔11从而不遮盖前电触头12和前电触头13。
如图5所示出的，例如通过生长金属沉积而在孔10和孔11中产生柱体14和柱体15。柱体14和柱体15的高度可以小于等于或者大于孔10和孔11的深度。
如图6所示出的，电接线20放置在主封装块8的顶部上，其端部焊接到柱体14和柱体15的前表面16和前表面17。可以将标准的接线接合机用于此。柱体14和柱体15的硬度有必要与接收焊接到前表面16和前表面17的电接线20的端部相容。电接线20的直径可以在例如15微米和50微米之间。电接线20可以用金或者基于银、铜或铝的合金制成。
如图7所示出的，在主封装块8的顶部上制造附加封装块18从而嵌入电接线20。
装配外部电连接元件23。
最终获得了在图1中示出的电子器件1。
如图2所示，电子器件1可以包括多个嵌入在附加块18中的例如平行的电接线20，连接到通过主封装块8的布置在相对应的电触头12和电触头13上的相对应的柱体14和柱体15。在参照图3到图7所描述的相续操作期间可以同时制造各个孔和各个柱体并且同时执行电接线的放置。
根据图8中示出的另一个实施例，电子器件27与电子器件1的区别仅在于电连接柱体14和电连接柱体15的存在。此时，电接线20的端部部分与通孔10和通孔11相结合并且电接线20的端部直接固定到电触头12和电触头13。此外，附加封装块18填充了通孔10和通孔11。
结果是，为了制造电子器件27，参照图7描述的步骤被省略。电接线20在制造了孔10和孔11之后直接安装。孔10和孔11以及放置电接线20的接线接合机的头有必要具有适于这个放置的相应。
根据在图9中示出的另一个实施例，电子器件28与电子器件1的区别之处在于在位于这个芯片4上方的通孔11中，电子连接柱体15制造在芯片4的前面30的特定的电触头29的顶部上。该特定的电触头29可以是已知为TSV(硅通孔技术)的形成通过集成电路芯片4的衬底的电连接的结果。
根据另一个实施例，电接线20的端部可以连接到制造在芯片4的前面30上的两个电触头上的各个柱体。
如在图8示例中的，在参照图9所描述的这些示例中，柱体可以省略。
根据图10所示出的另一个实施例，电子器件31与电子器件1的区别之处在于附加传导接线20的端部21并不固定到柱体而是通过嵌入在附加封装块18中的胶体滴32固定到主封装块8的前面9因此附加传导接线20的这个端部21为电悬浮的。这个布置还可以构成参照图9描述的电子器件28的变形的实施例。
已经描述的电子器件可以在共同的支撑晶片上集体地制造，如在微电子领域所已知的。可以通过扩散例如环氧树脂的液体材料并接着而对该材料进行硬化来获得主封装块和附加封装块。
根据一个应用示例，电接线20可以构成用于在非常高的频率(具有1GHz及其上的数量级，或者甚至远高于1GHz)处传输/接收射频信号的无线电天线，其通过经由支撑衬底2的电连接网络的短的电连接路径连接到芯片4。
根据另一个应用示例，电触头中的一个可以不连接到电组件并且因此为电悬浮的。
根据另一个应用示例，电接线20可以构成芯片4的电路的特定电连接，或者直接地或者经由电连接网络3或经由借助于电连接网络的芯片4的特定外部电连接。

Claims (20)

1.一种电子器件，包括：
支撑衬底，具有安装面并且包括电连接网络，
集成电路芯片，安装在所述支撑衬底的所述安装面上并且电连接到所述电连接网络，
封装块，包括主封装块和在所述主封装块上方的附加封装块，所述集成电路芯片被嵌入在所述主封装块中并且所述主封装块在所述支撑衬底的所述安装面上的所述集成电路芯片上方且围绕所述集成电路芯片延伸；以及
由导电材料制成的传导接线，所述传导接线能够在所述集成电路芯片和所述主封装块上方被自支撑，并且被嵌入在所述附加封装块中，所述传导接线被电连接到所述电连接网络和所述集成电路芯片中的至少一个。
2.根据权利要求1所述的器件，其中所述传导接线的一个端部在距所述集成电路芯片的***的一距离处连接到所述支撑衬底的所述安装面上的电触头。
3.根据权利要求1所述的器件，其中所述传导接线的一个端部被连接到在所述集成电路芯片的前面上的至少一个电触头。
4.根据权利要求1所述的器件，进一步包括在所述支撑衬底的所述安装面上的电触头上方的柱体，所述柱体延伸通过所述主封装块，其中所述传导接线的一个端部被固定到所述柱体。
5.根据权利要求1所述的器件，其中所述传导接线中的一个端部被固定到所述主封装块的上表面。
6.根据权利要求1所述的器件，其中所述传导接线为无线电天线。
7.根据权利要求1所述的器件，其中所述传导接线为电连接。
8.一种电子器件，包括：
支撑衬底，具有安装面并且包括电连接网络，
集成电路芯片，安装在所述支撑衬底的所述安装面上并且电连接到所述电连接网络，
封装块，包括主封装块和在所述主封装块上方的附加封装块，所述集成电路芯片被嵌入在所述主封装块中并且所述主封装块在所述支撑衬底的所述安装面上的所述集成电路芯片上方且围绕所述集成电路芯片延伸，
由导电材料制成的传导接线，所述传导接线被嵌入在所述附加封装块中，所述传导接线被电连接到所述集成电路芯片和所述电连接网络中的至少一个，以及
柱体，在所述集成电路芯片的前面上的电触头上方，所述柱体延伸通过所述主封装块，其中所述传导接线的一个端部固定到所述柱体。
9.一种制造电子器件的方法，包括按顺序执行的以下步骤：
制作延伸到主封装块中的孔，所述主封装块封装包括支撑衬底和安装在所述支撑衬底的前安装面上的集成电路芯片的主电子器件，所述孔至少部分地不遮盖电触头；
将至少一个附加传导接线装配在所述主封装块上方并且处在一位置使得所述附加传导接线的一个端部被电连接到所述电触头；以及
在所述主封装块上制作附加封装块，所述附加封装块嵌入有所述附加传导接线。
10.根据权利要求9所述的方法，进一步包括：
在所述孔中制作由导电材料制成的柱体；
其中所述装配包括将所述附加传导接线的所述一个端部固定到所述柱体。
11.根据权利要求10所述的方法，其中所述电触头为在所述支撑衬底的所述前安装面上的触头。
12.根据权利要求10所述的方法，其中所述电触头为在集成电路芯片上的触头。
13.根据权利要求9所述的方法，其中所述电触头为在支撑衬底的前安装面上的触头，所述附加传导接线的所述一个端部延伸到所述孔中用于与所述电触头进行接触。
14.根据权利要求9所述的方法，进一步包括将所述附加传导接线的另一个端部固定到所述主封装块。
15.一种电子器件，包括：
嵌入有集成电路芯片的主封装块，所述主封装块包括至少部分地不遮盖电触头的开口；
能够在所述集成电路芯片和所述主封装块上方被自支撑的传导接线，被定位为使得所述传导接线的一个端部电连接到所述电触头；以及
在所述主封装块上的附加封装块，所述附加封装块嵌入有所述传导接线。
16.根据权利要求15所述的器件，进一步包括填充所述开口的传导柱体，所述传导接线的所述一个端部与所述传导柱体进行接触。
17.根据权利要求15所述的器件，其中所述电触头为在所述集成电路芯片上的触头。
18.根据权利要求15所述的器件，其中所述电触头为在支撑衬底上的触头，所述集成电路芯片被安装到所述支撑衬底。
19.根据权利要求15所述的器件，其中所述传导接线为天线。
20.一种电子器件，包括：
嵌入有集成电路芯片的主封装块，所述主封装块包括至少部分地不遮盖电触头的开口；
在所述主封装块上方的传导接线，被定位为使得所述传导接线的一个端部电连接到所述电触头；以及
在所述主封装块上的附加封装块，所述附加封装块嵌入有所述传导接线，其中所述附加封装块的材料填充所述开口，所述传导接线的所述一个端部延伸到所述开口中。
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Publication number Priority date Publication date Assignee Title
FR3041859B1 (fr) * 2015-09-30 2018-03-02 Stmicroelectronics (Grenoble 2) Sas Dispositif electronique muni d'un fil conducteur integre et procede de fabrication
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010057808A1 (en) * 2008-11-24 2010-05-27 Stmicroelectronics (Grenoble) Sas Semiconductor device having stacked components
US20130009320A1 (en) * 2011-07-07 2013-01-10 Samsung Electro-Mechanics Co., Ltd. Semiconductor package and method of manufacturing the same
US20150102500A1 (en) * 2013-10-15 2015-04-16 Stmicroelectronics (Grenoble 2) Sas Electronic system comprising stacked electronic devices comprising integrated-circuit chips
CN205723534U (zh) * 2015-09-30 2016-11-23 意法半导体(格勒诺布尔2)公司 电子器件

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2780551B1 (fr) 1998-06-29 2001-09-07 Inside Technologies Micromodule electronique integre et procede de fabrication d'un tel micromodule
US20040217472A1 (en) 2001-02-16 2004-11-04 Integral Technologies, Inc. Low cost chip carrier with integrated antenna, heat sink, or EMI shielding functions manufactured from conductive loaded resin-based materials
US7042398B2 (en) 2004-06-23 2006-05-09 Industrial Technology Research Institute Apparatus of antenna with heat slug and its fabricating process
TWI380500B (en) * 2007-02-06 2012-12-21 Mutual Pak Technology Co Ltd Integrated circuit device having antenna conductors and the mothod for the same
TWI370530B (en) 2008-05-21 2012-08-11 Advanced Semiconductor Eng Semiconductor package having an antenna
US8125061B2 (en) 2009-09-03 2012-02-28 Advanced Semiconductor Engineering, Inc. Semiconductor package and method of manufacturing the same
US9007273B2 (en) 2010-09-09 2015-04-14 Advances Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US8637963B2 (en) 2011-10-05 2014-01-28 Sandisk Technologies Inc. Radiation-shielded semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010057808A1 (en) * 2008-11-24 2010-05-27 Stmicroelectronics (Grenoble) Sas Semiconductor device having stacked components
US20130009320A1 (en) * 2011-07-07 2013-01-10 Samsung Electro-Mechanics Co., Ltd. Semiconductor package and method of manufacturing the same
US20150102500A1 (en) * 2013-10-15 2015-04-16 Stmicroelectronics (Grenoble 2) Sas Electronic system comprising stacked electronic devices comprising integrated-circuit chips
CN205723534U (zh) * 2015-09-30 2016-11-23 意法半导体(格勒诺布尔2)公司 电子器件

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US10103079B2 (en) 2018-10-16

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