CN106531056B - CMOS logic unit, logic circuit, gate driving circuit and display device - Google Patents
CMOS logic unit, logic circuit, gate driving circuit and display device Download PDFInfo
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- CN106531056B CN106531056B CN201710034194.0A CN201710034194A CN106531056B CN 106531056 B CN106531056 B CN 106531056B CN 201710034194 A CN201710034194 A CN 201710034194A CN 106531056 B CN106531056 B CN 106531056B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
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Abstract
The present invention provides a kind of CMOS (complementary metal oxide semiconductor) logic unit, logic circuit, gate driving circuit and display device.The CMOS logic unit, including CMOS driving unit, further include: output voltage compensation unit, it is connect respectively with the output end of the CMOS driving unit and high level end, the output end for controlling the CMOS driving unit when the voltage of the output end of CMOS driving unit output is greater than predetermined voltage is connect with the high level end.The present invention can to avoid existing for existing CMOS driving unit due to the presence of static leakage current cause output level decline phenomenon, can guarantee CMOS driving unit to the driving capability of junior's circuit.
Description
Technical field
The present invention relates to cmos circuit technical field more particularly to a kind of CMOS (Complementary Metal Oxide
Semiconductor, complementary metal oxide semiconductor) logic electric unit, logic circuit, gate driving circuit and display dress
It sets.
Background technique
Existing CMOS driving unit includes the first PMOS tube and the first NMOS tube, when the input of CMOS driving unit terminates
When entering low level, the output end of CMOS driving unit exports high level, and first PMOS tube is there are parasitic diode at this time, this
There are parasitic diodes for one NMOS tube.Existing CMOS driving unit is when its input terminal accesses low level due to the first NMOS
The leakage current of the leakage current and the NMOS parasitic diode of the leakage current of pipe and the PMOS parasitic diode will lead to described
CMOS driving unit is since the presence of static leakage current causes output level to decline, it cannot be guaranteed that the CMOS driving unit is under
The driving capability of grade circuit.
Summary of the invention
The main purpose of the present invention is to provide a kind of CMOS logic unit, logic circuit, gate driving circuit and displays
Device solves existing CMOS logic unit since the presence of static leakage current causes output level to decline, it cannot be guaranteed that described
The problem of CMOS driving unit is to the driving capability of junior's circuit.
In order to achieve the above object, it the present invention provides a kind of CMOS logic unit, including CMOS driving unit, also wraps
It includes:
Output voltage compensation unit is connect, for working as respectively with the output end of the CMOS driving unit and high level end
The voltage of the output end output of the CMOS driving unit controls the output end of the CMOS driving unit when being greater than predetermined voltage
It is connect with the high level end.
When implementation, the output voltage compensation unit includes:
Inversed module, input terminal are connect with the output end of the CMOS driving unit；And
PMOS tube is compensated, grid is connect with the output end of the inversed module, and the first pole is connect with the high level end, the
Two poles are connect with the output end of the CMOS driving unit.
When implementation, the output voltage compensation unit further include:
Compensating electric capacity, first end are connect with the output end of the CMOS driving unit, second end ground connection.
When implementation, the CMOS driving unit includes:
First PMOS tube, grid are connect with the input terminal of the CMOS driving unit, and the first pole and the high level end connect
It connects, the second pole is connect with the output end of the CMOS driving unit；And
First NMOS tube, grid are connect with the input terminal of the CMOS driving unit, and the first pole is connect with low level end, the
Two poles are connect with the output end of the CMOS driving unit.
The present invention also provides a kind of CMOS logic circuits, including N number of cascade CMOS driving unit；N is whole greater than 1
Number；
Other than first order CMOS driving unit, the input terminal of every level-one CMOS driving unit and adjacent upper level CMOS
The output end of driving unit connects；
The input terminal of first order CMOS driving unit is the input terminal of the CMOS logic circuit；
The CMOS logic circuit further include: output voltage compensation element circuit, respectively with high level end and every level-one institute
The output end connection for stating CMOS driving unit, for being greater than in advance when the CMOS driving unit by the voltage that its output end exports
The output end is controlled when constant voltage to connect with the high level end.
When implementation, the output voltage compensation element circuit includes:
First inversed module, input terminal are connect with the output end of (2m-1) grade CMOS driving unit；
Second inversed module, input terminal are connect with the output end of 2m grades of CMOS driving units；And
N number of compensation PMOS tube；
Each compensation PMOS tube is corresponding with CMOS driving unit described in level-one respectively；
The output end of first inversed module and all compensation PMOS tube corresponding with odd level CMOS driving unit
Grid all connects；
The output end of second inversed module and all compensation PMOS tube corresponding with even level CMOS driving unit
Grid all connects；
First pole of each compensation PMOS tube is all connect with the high level end；
Second pole of compensation PMOS tube corresponding with level-one CMOS driving unit and the output end of this grade of CMOS driving unit
Connection；
M is any positive integer, and 2m is less than or equal to N.
When implementation, the output voltage compensation element circuit further includes N number of compensating electric capacity；
Each compensating electric capacity is corresponding with CMOS driving unit described in level-one respectively；
The first end of compensating electric capacity corresponding with level-one CMOS driving unit and the output end of this grade of CMOS driving unit connect
It connects, the second end of N number of compensating electric capacity is all grounded.
When implementation, every level-one CMOS driving unit respectively include:
First PMOS tube, grid are connect with the input terminal of this grade of CMOS driving unit, and the first pole and the high level end connect
It connects, the second pole is connect with the output end of this grade of CMOS driving unit；And
First NMOS tube, grid are connect with the input terminal of this grade of CMOS driving unit, and the first pole is connect with low level end, the
Two poles are connect with the output end of this grade of CMOS driving unit.
The present invention also provides a kind of gate driving circuit, the gate driving circuit includes above-mentioned CMOS logic list
Member, alternatively, the gate driving circuit includes above-mentioned CMOS logic circuit.
The present invention also provides a kind of display devices, including upper gate driving circuit.
Compared with prior art, CMOS logic unit of the present invention, logic circuit, gate driving circuit and display dress
It sets by using output voltage compensation unit when the voltage that the output end of the CMOS driving unit exports is greater than predetermined voltage
Control CMOS driving unit output end connect with high level end, to avoid existing for existing CMOS driving unit due to static state
The presence of leakage current causes output level to decline phenomenon, can guarantee that CMOS driving unit exports high level, maintains to junior's electricity
The driving capability on road.
Detailed description of the invention
Fig. 1 is the structure chart of CMOS logic unit described in the embodiment of the present invention；
Fig. 2 is the circuit diagram of CMOS logic unit described in another embodiment of the present invention；
Fig. 3 is the circuit diagram of a specific embodiment of CMOS logic unit of the present invention；
Fig. 4 is the circuit diagram of a specific embodiment of CMOS logic circuit of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
As shown in Figure 1, (the Complementary Metal Oxide of CMOS described in the embodiment of the present invention
Semiconductor, complementary metal oxide semiconductor) logic unit, including CMOS driving unit 10, further includes:
Output voltage compensation unit 11, respectively with the output end OUT of the CMOS driving unit 10 and output high level VGH
High level end connection, for when the CMOS driving unit 10 output end OUT export voltage be greater than predetermined voltage time control
The output end OUT for making the CMOS driving unit 10 is connect with the high level end of the output high level VGH.
In practical operation, the predetermined voltage is high level, and the specific voltage value of the predetermined voltage can be according to reality
Border situation is selected, is not limited thereto.
COMS logic circuit described in the embodiment of the present invention drives by using output voltage compensation unit 11 in the CMOS
The output end OUT and height of control CMOS driving unit 10 when the voltage of the output end OUT output of moving cell 10 is greater than predetermined voltage
Level terminal connection, to avoid existing for existing CMOS driving unit since the presence of static leakage current causes output level to decline
Phenomenon can guarantee that CMOS driving unit exports high level, maintain the driving capability to junior's circuit.
Specifically, as shown in Fig. 2, the output voltage compensation unit 11 may include:
Inversed module 111, input terminal are connect with the output end OUT of the CMOS driving unit 10；And
PMOS tube MCp is compensated, grid is connect with the output end of the inversed module 111, the first pole and the high electricity of the output
The high level end of flat VGH connects, and the second pole is connect with the output end OUT of the CMOS driving unit 10.
The embodiment of present invention CMOS logic unit as shown in Figure 2 exports high electricity at work, in CMOS driving unit
Usually, compensation PMOS tube MCp conducting is controlled by the inversed module 111, using increased compensation PMOS tube MCp as Leakage Current
Compensation transistor, overturn using strong by 1 (high level) characteristic of compensation PMOS tube and the logic of inversed module 111, compensation works as
CMOS driving unit 10 exports existing static leakage current when high level, compensates loss of charge caused by existing leakage path.
In an embodiment as illustrated in figure 2, compensation PMOS tube MCp is as the compensation crystal between high level VGH and Vout
Pipe, to guarantee that Vout and VGH are consistent and guarantee Vout stable；Vout is the output end OUT of the CMOS driving unit 10
The voltage of output.On the contrary, the output end OUT of CMOS driving unit 10 exports high level, thus institute when Vout is in low level
It states compensation PMOS tube MCp to close, the output end OUT of the CMOS driving unit 10 is prevented to be raised.
Preferably, the output voltage compensation unit can also include:
Compensating electric capacity, first end are connect with the output end of the CMOS driving unit, second end ground connection.
In the preferred case, the output voltage compensation unit further includes compensating electric capacity, for defeated to CMOS driving unit
Voltage out carries out pressure stabilizing.
In practical operation, the CMOS driving unit may include:
First PMOS (P-Metal-Oxide-Semiconductor, p-type Metal-oxide-semicondutor) pipe, grid with
The input terminal of the CMOS driving unit connects, and the first pole is connect with the high level end, and the second pole and CMOS driving are single
The output end connection of member；And
First NMOS (N-Metal-Oxide-Semiconductor, N-type Metal-oxide-semicondutor) pipe, grid with
The input terminal of the CMOS driving unit connects, and the first pole is connect with low level end, the second pole and the CMOS driving unit
Output end connection.
A specific embodiment of CMOS logic unit of the present invention is illustrated below with reference to Fig. 3.
As shown in figure 3, a specific embodiment of CMOS logic unit of the present invention includes CMOS driving unit and defeated
Voltage compensation unit out, wherein
The CMOS driving unit includes:
First PMOS tube Mfp, grid are connect with the input terminal In of the CMOS driving unit, drain electrode and output high level
The high level end of VGH connects, and source electrode is connect with the output end OUT of the CMOS driving unit；And
First NMOS tube Mfn, grid are connect with the input terminal In of the CMOS driving unit, drain electrode and output low level
The low level end of VGL connects, and source electrode is connect with the output end OUT of the CMOS driving unit；
The output voltage compensation unit includes inversed module, compensation PMOS tube MCp and compensating electric capacity Cmp；
The first end of the compensating electric capacity Cmp is connect with the output end OUT of the CMOS driving unit, the compensating electric capacity
The second end of Cmp is connect with ground terminal GND；
The inversed module includes phase inverter F1；
The input terminal of the phase inverter F1 is connect with the output end OUT of the CMOS driving unit；
The grid of the compensation PMOS tube MCp is connect with the output end of the phase inverter F1, drain electrode and the high electricity of the output
The high level end of flat VGH connects, and source electrode is connect with the output end OUT of the CMOS driving unit.
In Fig. 3, Dp is the parasitic PMOS diode of the Mfp when OUT exports high level, when Dn is that OUT exports high level
The parasitic NMOS diode of Mfn；In can access IC (Integrated Circuit, integrated circuit) output voltage signal or
Person's clock signal.
When OUT exports high level since there are static leakage currents (as shown in figure 3, the static leakage current includes flowing through
The conducting electric current Id of Mfp, the first leakage current Il1 for flowing through Mfn, the second leakage current Il2 for flowing through Dp and the third for flowing through Dn leakage
Electric current Il3 (the reverse phase saturation current that Il3 is Dn), although conducting electric current Id can provide electric current, Il1, Il2 and Il3 to OUT
Extract electric current outward at OUT, therefore the voltage Vout that will lead to OUT output cannot keep as VGH, the voltage value of Vout
The gate circuit driving capability deficiency that will lead to rear end is reduced, therefore CMOS logic unit as shown in Figure 3 of the invention is specific
Embodiment increases phase inverter F1 in the rear end OUT, and increases MCp conduct between the high level end and phase inverter F1 of output VGH and let out
The compensation transistor for revealing electric current passes through the logic function of phase inverter F1 using strong 1 characteristic of the logic overturning and MCp of phase inverter F1
Loss of charge caused by compensate lower section leakage path can be connected to control MCp.
CMOS logic circuit described in the embodiment of the present invention includes N number of cascade CMOS driving unit；N is whole greater than 1
Number；
Other than first order CMOS driving unit, the input terminal of every level-one CMOS driving unit and adjacent upper level CMOS
The output end of driving unit connects；
The input terminal of first order CMOS driving unit is the input terminal of the CMOS logic circuit；
The CMOS logic circuit further include: output voltage compensation element circuit, respectively with high level end and every level-one institute
The output end connection for stating CMOS driving unit, for being greater than in advance when the CMOS driving unit by the voltage that its output end exports
The output end is controlled when constant voltage to connect with the high level end.
CMOS logic circuit described in the embodiment of the present invention includes multiple cascade CMOS driving units, and also includes output
Voltage compensation unit circuit, the output voltage compensation element circuit can export high level time control in every level-one CMOS driving unit
The output end for making the CMOS driving unit is connect with high level end, is driven to avoid the CMOS in existing CMOS logic circuit single
It is first existing since the presence of static leakage current causes output level to decline phenomenon, it can guarantee the high electricity of CMOS driving unit output
It is flat, maintain the driving capability to junior's circuit.
Specifically, the output voltage compensation element circuit may include:
First inversed module, input terminal are connect with the output end of the 2nd (m-1) grade CMOS driving unit；
Second inversed module, input terminal are connect with the output end of 2m grades of CMOS driving units；And
N number of compensation PMOS tube；
Each compensation PMOS tube is corresponding with CMOS driving unit described in level-one respectively；
The output end of first inversed module and all compensation PMOS tube corresponding with odd level CMOS driving unit
Grid all connects；
The output end of second inversed module and all compensation PMOS tube corresponding with even level CMOS driving unit
Grid all connects；
First pole of each compensation PMOS tube is all connect with the high level end；
Second pole of compensation PMOS tube corresponding with level-one CMOS driving unit and the output end of this grade of CMOS driving unit
Connection；
M is any positive integer, and 2m is less than or equal to N.
Preferably, the output voltage compensation element circuit further include:
N number of compensating electric capacity；
Each compensating electric capacity is corresponding with CMOS driving unit described in level-one respectively；
The first end of compensating electric capacity corresponding with level-one CMOS driving unit and the output end of this grade of CMOS driving unit connect
It connects, the second end of N number of compensating electric capacity is all grounded.
In the preferred case, the output voltage compensation unit further includes N number of compensating electric capacity, for driving to CMOS at different levels
The voltage of unit output carries out pressure stabilizing.
Specifically, every level-one CMOS driving unit can be with respectively include:
First PMOS tube, grid are connect with the input terminal of this grade of CMOS driving unit, and the first pole and the high level end connect
It connects, the second pole is connect with the output end of this grade of CMOS driving unit；And
First NMOS tube, grid are connect with the input terminal of this grade of CMOS driving unit, and the first pole is connect with low level end, the
Two poles are connect with the output end of this grade of CMOS driving unit.
In the specific implementation, first inversed module can be the first phase inverter, and second inversed module can be
Second phase inverter.
In practical operation, every grade of CMOS driving unit requires one PMOS tube of respective production as output high level
Compensation transistor between the high level line of VGH and this grade of CMOS driving unit, to guarantee the output of this grade of CMOS driving unit
Voltage and VGH are consistent to guarantee output voltage stabilization.
When the series connection of multistage CMOS driving unit together when, can add the first phase inverter and the second phase inverter, described first
The grid connection of the output end of phase inverter and compensation PMOS tube corresponding with odd level CMOS driving unit, second phase inverter
Output end and it is corresponding with even level CMOS driving unit compensation PMOS tube grid connection, the input of first phase inverter
End can be connect with the output end of any odd level CMOS driving unit, and the input terminal of second phase inverter can be with any idol
The output end of several levels CMOS driving unit connects.
In the specific implementation, it can adjust what channel width-over-length ratio did the threshold voltage of the first phase inverter by technological level
It is more slightly lower, as long as then can guarantee the output end for this grade of odd level CMOS driving unit connecting with the input terminal of first phase inverter
The voltage of output be high level (positive polarity) when, and the voltage be greater than first phase inverter threshold voltage when, this can be made
First phase inverter opens compensation PMOS tube corresponding with odd level CMOS driving unit.
In the specific implementation, it can adjust what channel width-over-length ratio did the threshold voltage of the second phase inverter by technological level
It is more slightly lower, as long as then can guarantee the output end for this grade of even level CMOS driving unit connecting with the input terminal of second phase inverter
The voltage of output be high level (positive polarity) when, and the voltage be greater than second phase inverter threshold voltage when, this can be made
Second phase inverter opens compensation PMOS tube corresponding with even level CMOS driving unit.
Those skilled in the art will know that in CMOS logic circuit, the threshold value of the first phase inverter and the second phase inverter
Voltage, less than the driving voltage of driving next stage circuit.
It is loaded due to the compensation PMOS transistor of output end load and the output end of the second phase inverter of the first phase inverter
Compensate PMOS transistor it is more, then first phase inverter output end load and second phase inverter output end load compared with
Greatly, so the fan out capability (carrying load ability) of the first phase inverter and being fanned out to for the second phase inverter should be improved by process means
Ability is to guarantee normally to open each compensation PMOS tube.
In the specific implementation, when the series for the CMOS driving unit for including when the CMOS logic circuit is even number, by the
The input terminal of one phase inverter is connect with the output end of penultimate stage CMOS driving unit, by the input terminal of the second phase inverter and is fallen
The output end connection of number first order CMOS driving unit；When the series for the CMOS driving unit that the CMOS logic circuit includes is
When odd number, the input terminal of the first phase inverter is connect with the output end of grade CMOS driving unit last, by the second phase inverter
Input terminal connect with the output end of penultimate stage CMOS driving unit；It is to consider to export when subsequent CMOS driving unit
It then ensure that the COMS driving unit of front also has reached high level when being high, ensure that CMOS driving unit outputs at different levels
Level height consistency.
A specific embodiment of CMOS logic circuit of the present invention is illustrated below with reference to Fig. 4.
As shown in figure 4, a specific embodiment of CMOS logic circuit of the present invention includes level Four CMOS driving unit
With output voltage compensation element circuit, wherein
The output voltage compensation element circuit includes:
First phase inverter F1, input terminal are connect with the output end OUT3 of third level CMOS driving unit；
Second phase inverter F2, input terminal are connect with the output end OUT4 of fourth stage CMOS driving unit；
First compensation PMOS tube MCp1 corresponding with first order CMOS driving unit；
Second compensation PMOS tube MCp2 corresponding with second level CMOS driving unit；
Third corresponding with third level CMOS driving unit compensates PMOS tube MCp3；
Fourth compensation PMOS tube MCp4 corresponding with fourth stage CMOS driving unit；
First compensating electric capacity Cmp1, first end are connect with the output end OUT1 of first order CMOS driving unit, second end with
Ground terminal GND connection；
Second compensating electric capacity Cmp2, first end are connect with the output end OUT2 of second level CMOS driving unit, second end with
Ground terminal GND connection；
Third compensating electric capacity Cmp3, first end are connect with the output end OUT3 of third level CMOS driving unit, second end with
Ground terminal GND connection；And
4th compensating electric capacity Cmp4, first end are connect with the output end OUT4 of fourth stage CMOS driving unit, second end with
Ground terminal GND connection；
The output end of the first phase inverter F1 and the grid for compensating PMOS tube MCp1 with first and third compensate PMOS tube
The grid of MCp3 connects；
The output end of the second phase inverter F2 and the grid for compensating PMOS tube MCp2 with second and the 4th compensation PMOS tube
The grid of MCp4 connects；
The drain electrode of the first compensation PMOS tube MCp1, the drain electrode of the second compensation PMOS tube MCp2, the third are mended
High level end of the drain electrode of the drain electrode and the 4th compensation PMOS tube MCp4 of repaying PMOS tube MCp3 all with output high level VGH connects
It connects；
The source electrode of the first compensation PMOS tube MCp1 is connect with the output end OUT1 of first order CMOS driving unit；
The source electrode of the second compensation PMOS tube MCp1 is connect with the output end OUT2 of second level CMOS driving unit；
The source electrode of the third compensation PMOS tube MCp3 is connect with the output end OUT3 of third level CMOS driving unit；
The source electrode of the 4th compensation PMOS tube MCp4 is connect with the output end OUT4 of fourth stage CMOS driving unit；
The first order CMOS driving unit includes:
First PMOS tube Mfp1, grid are connect with the input terminal IN1 of the first order CMOS driving unit, drain electrode with it is described
The high level end connection of high level VGH is exported, source electrode is connect with the output end OUT1 of the first order CMOS driving unit；With
And
First NMOS tube Mfn1, grid are connect with the input terminal IN1 of the first order CMOS driving unit, drain electrode and output
The low level end of low level VGL connects, and source electrode is connect with the output end OUT1 of the first order CMOS driving unit；
The second level CMOS driving unit includes:
Second PMOS tube Mfp2, grid are connect with the input terminal IN2 of the second level CMOS driving unit, drain electrode with it is described
The high level end connection of high level VGH is exported, source electrode is connect with the output end OUT2 of the second level CMOS driving unit；With
And
Second NMOS tube Mfn2, grid are connect with the input terminal IN2 of the second level CMOS driving unit, drain electrode and output
The low level end of low level VGL connects, and source electrode is connect with the output end OUT2 of the second level CMOS driving unit；
The third level CMOS driving unit includes:
Third PMOS tube Mfp3, grid are connect with the input terminal IN3 of the third level CMOS driving unit, drain electrode with it is described
The high level end connection of high level VGH is exported, source electrode is connect with the output end OUT3 of the third level CMOS driving unit；With
And
Third NMOS tube Mfn3, grid are connect with the input terminal IN3 of the third level CMOS driving unit, drain electrode and output
The low level end of low level VGL connects, and source electrode is connect with the output end OUT3 of the third level CMOS driving unit；
The fourth stage CMOS driving unit includes:
4th PMOS tube Mfp4, grid are connect with the input terminal IN4 of the fourth stage CMOS driving unit, drain electrode with it is described
The high level end connection of high level VGH is exported, source electrode is connect with the output end OUT4 of the fourth stage CMOS driving unit；With
And
4th NMOS tube Mfn4, grid are connect with the input terminal IN4 of the fourth stage CMOS driving unit, drain electrode and output
The low level end of low level VGL connects, and source electrode is connect with the output end OUT4 of the fourth stage CMOS driving unit；
Present invention CMOS logic circuit as shown in Figure 4 at work,
When IN1 accesses low level, OUT1 and OUT3 export high level, so that F1 exports low level so that MCp1 and
MCp3 is connected, so that OUT1 is controlled and OUT3 accesses VGH, to improve driving capability；
When IN1 accesses high level, OUT2 and OUT4 export high level, so that F2 exports low level so that MCp2 and
MCp4 is connected, so that OUT2 is controlled and OUT4 accesses VGH, to improve driving capability.
In practical operation, CMOS logic circuit of the present invention generally comprises 4-6 grades of CMOS driving units, from first
Grade CMOS driving unit postpones smaller, therefore the output voltage compensation element circuit between two-stage CMOS driving unit to the end
The first phase inverter, input terminal and the afterbody being connect including input terminal with the output end of penultimate stage CMOS driving unit
The second phase inverter and compensation transistor corresponding with every level-one CMOS driving unit of the output end connection of CMOS driving unit
?.
In the specific implementation, multistage CMOS driving unit can also input terminal in parallel namely CMOS driving unit at different levels
It is connected with each other, so that the signal of CMOS driving unit output end at different levels output is synchronous, then passes through output voltage compensation unit electricity
Road guarantees the driving capability of the CMOS driving unit at different levels.
Gate driving circuit described in the embodiment of the present invention, including above-mentioned CMOS logic unit, alternatively, including above-mentioned
CMOS logic circuit.
Display device described in the embodiment of the present invention includes above-mentioned gate driving circuit.
The above is a preferred embodiment of the present invention, it is noted that for those skilled in the art
For, without departing from the principles of the present invention, it can also make several improvements and retouch, these improvements and modifications
It should be regarded as protection scope of the present invention.
Claims (5)
1. a kind of CMOS logic circuit, which is characterized in that including N number of cascade CMOS driving unit；N is the integer greater than 1；
Other than first order CMOS driving unit, the input terminal of every level-one CMOS driving unit and adjacent upper level CMOS are driven
The output end of unit connects；
The input terminal of first order CMOS driving unit is the input terminal of the CMOS logic circuit；
The CMOS logic circuit further include: output voltage compensation element circuit, respectively and described in high level end and every level-one
The output end of CMOS driving unit connects, for making a reservation for when the CMOS driving unit is greater than by the voltage that its output end exports
The output end is controlled when voltage to connect with the high level end；
The output voltage compensation element circuit includes:
First inversed module, input terminal are connect with the output end of (2m-1) grade CMOS driving unit；
Second inversed module, input terminal are connect with the output end of 2m grades of CMOS driving units；And
N number of compensation PMOS tube；
Each compensation PMOS tube is corresponding with CMOS driving unit described in level-one respectively；
The grid of the output end of first inversed module and all compensation PMOS tube corresponding with odd level CMOS driving unit
All connect；
The grid of the output end of second inversed module and all compensation PMOS tube corresponding with even level CMOS driving unit
All connect；
First pole of each compensation PMOS tube is all connect with the high level end；
Second pole of compensation PMOS tube corresponding with level-one CMOS driving unit is connect with the output end of this grade of CMOS driving unit；
M is any positive integer, and 2m is less than or equal to N.
2. CMOS logic circuit as described in claim 1, which is characterized in that the output voltage compensation element circuit further includes
N number of compensating electric capacity；
Each compensating electric capacity is corresponding with CMOS driving unit described in level-one respectively；
The first end of compensating electric capacity corresponding with level-one CMOS driving unit is connect with the output end of this grade of CMOS driving unit, institute
The second end for stating N number of compensating electric capacity is all grounded.
3. the CMOS logic circuit as described in any claim in claims 1 or 2, which is characterized in that every level-one CMOS drives
Moving cell respectively include:
First PMOS tube, grid are connect with the input terminal of this grade of CMOS driving unit, and the first pole is connect with the high level end, the
Two poles are connect with the output end of this grade of CMOS driving unit；And
First NMOS tube, grid are connect with the input terminal of this grade of CMOS driving unit, and the first pole is connect with low level end, the second pole
It is connect with the output end of this grade of CMOS driving unit.
4. a kind of gate driving circuit, which is characterized in that the gate driving circuit includes such as any power in claims 1 to 3
Benefit requires the CMOS logic circuit.
5. a kind of display device, which is characterized in that including gate driving circuit as claimed in claim 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710034194.0A CN106531056B (en) | 2017-01-18 | 2017-01-18 | CMOS logic unit, logic circuit, gate driving circuit and display device |
Applications Claiming Priority (1)
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| CN106531056A (en) | 2017-03-22 |
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