CN106531056A - CMOS logic unit and logic circuit, gate drive circuit and display device - Google Patents
CMOS logic unit and logic circuit, gate drive circuit and display device Download PDFInfo
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- CN106531056A CN106531056A CN201710034194.0A CN201710034194A CN106531056A CN 106531056 A CN106531056 A CN 106531056A CN 201710034194 A CN201710034194 A CN 201710034194A CN 106531056 A CN106531056 A CN 106531056A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
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Abstract
The invention provides a CMOS (complementary metal oxide semiconductor) logic unit and logic circuit, a gate drive circuit and a display device. The CMOS logic unit comprises a CMOS drive unit and further comprises an output voltage compensation unit which is connected with the output end of the CMOS drive unit and a high level end and used for controlling the output end of the CMOS drive unit to be connected with the high level end when the voltage output by the output end of the CMOS drive unit is larger than the predetermined voltage. According to the CMOS logic unit and logic circuit, the gate drive circuit and the display device, the phenomenon that the output level is reduced due to the existence of static leakage currents of existing CMOS drive units can be avoided, and the drive capability of the CMOS drive unit to a lower-level circuit can be ensured.
Description
Technical field
The present invention relates to cmos circuit technical field, more particularly to a kind of CMOS (Complementary Metal Oxide
Semiconductor, complementary metal oxide semiconductors (CMOS)) logic electric unit, logic circuit, gate driver circuit and display dress
Put.
Background technology
Existing CMOS driver elements include the first PMOS and the first NMOS tube, when the input of CMOS driver elements is terminated
When entering low level, the outfan of CMOS driver elements output high level, now first PMOS there is parasitic diode, this
There is parasitic diode in one NMOS tube.Existing CMOS driver elements are when its input accesses low level due to a NMOS
The leakage current of the leakage current and the NMOS parasitic diodes of the leakage current of pipe and the PMOS parasitic diodes can cause described
CMOS driver elements cause output level to decline due to the presence of static leakage current, it is impossible to ensure the CMOS driver elements under
The driving force of level circuit.
The content of the invention
Present invention is primarily targeted at providing a kind of CMOS logic unit, logic circuit, gate driver circuit and display
Device, solves existing CMOS logic unit as the presence of static leakage current causes output level to decline, it is impossible to ensure described
Problem of the CMOS driver elements to the driving force of subordinate's circuit.
In order to achieve the above object, the invention provides a kind of CMOS logic unit, including CMOS driver elements, also wrap
Include：
Output voltage compensation unit, is connected with the outfan of the CMOS driver elements and high level end respectively, for working as
The voltage of the outfan output of the CMOS driver elements controls the outfan of the CMOS driver elements when being more than predetermined voltage
It is connected with the high level end.
During enforcement, the output voltage compensation unit includes：
Inversed module, input are connected with the outfan of the CMOS driver elements；And,
Compensation PMOS, grid are connected with the outfan of the inversed module, and the first pole is connected with the high level end, the
Two poles are connected with the outfan of the CMOS driver elements.
During enforcement, the output voltage compensation unit also includes：
Compensating electric capacity, first end are connected with the outfan of the CMOS driver elements, the second end ground connection.
During enforcement, the CMOS driver elements include：
First PMOS, grid are connected with the input of the CMOS driver elements, and the first pole is connected with the high level end
Connect, the second pole is connected with the outfan of the CMOS driver elements；And,
First NMOS tube, grid are connected with the input of the CMOS driver elements, and the first pole is connected with low level end, the
Two poles are connected with the outfan of the CMOS driver elements.
Present invention also offers a kind of CMOS logic circuit, including the CMOS driver elements of N number of cascade；N is whole more than 1
Number；
Input and adjacent upper level CMOS in addition to first order CMOS driver element, per one-level CMOS driver element
The outfan connection of driver element；
The input of first order CMOS driver element is the input of the CMOS logic circuit；
The CMOS logic circuit also includes：Output voltage compensation element circuit, respectively with high level end and per one-level institute
The outfan connection of CMOS driver elements is stated, for being more than in advance by the voltage that its outfan is exported when the CMOS driver elements
Determine during voltage, to control the outfan to be connected with the high level end.
During enforcement, the output voltage compensation element circuit includes：
First inversed module, input are connected with the outfan of (2m-1) level CMOS driver element；
Second inversed module, input are connected with the outfan of 2m level CMOS driver elements；And,
N number of compensation PMOS；
Each compensation PMOS is corresponding with CMOS driver elements described in one-level respectively；
The outfan of first inversed module and all compensation PMOS corresponding with odd level CMOS driver elements
Grid all connects；
The outfan of second inversed module and all compensation PMOS corresponding with even level CMOS driver elements
Grid all connects；
First pole of each compensation PMOS is all connected with the high level end；
Second pole of compensation PMOS corresponding with one-level CMOS driver element and the outfan of this grade of CMOS driver element
Connection；
M is arbitrary positive integer, and 2m is less than or equal to N.
During enforcement, the output voltage compensation element circuit also includes N number of compensating electric capacity；
Each compensating electric capacity is corresponding with CMOS driver elements described in one-level respectively；
The first end of compensating electric capacity corresponding with one-level CMOS driver element is connected with the outfan of this grade of CMOS driver element
Connect, the second end of N number of compensating electric capacity is all grounded.
During enforcement, include per one-level CMOS driver element respectively：
First PMOS, grid are connected with the input of this grade of CMOS driver element, and the first pole is connected with the high level end
Connect, the second pole is connected with the outfan of this grade of CMOS driver element；And,
First NMOS tube, grid are connected with the input of this grade of CMOS driver element, and the first pole is connected with low level end, the
Two poles are connected with the outfan of this grade of CMOS driver element.
Present invention also offers a kind of gate driver circuit, the gate driver circuit includes above-mentioned CMOS logic list
Unit, or, the gate driver circuit includes above-mentioned CMOS logic circuit.
Present invention also offers a kind of display device, including upper gate driver circuit.
Compared with prior art, CMOS logic unit of the present invention, logic circuit, gate driver circuit and display dress
Put by using output voltage compensation unit the CMOS driver elements outfan export voltage be more than predetermined voltage when
The outfan of control CMOS driver elements is connected with high level end, with avoid the presence of existing CMOS driver elements due to static state
The presence of leakage current causes output level to decline phenomenon, can guarantee that CMOS driver elements output high level, maintains to subordinate's electricity
The driving force on road.
Description of the drawings
Fig. 1 is the structure chart of the CMOS logic unit described in the embodiment of the present invention；
Fig. 2 is the circuit diagram of the CMOS logic unit described in another embodiment of the present invention；
Fig. 3 is the circuit diagram of a specific embodiment of CMOS logic unit of the present invention；
Fig. 4 is the circuit diagram of a specific embodiment of CMOS logic circuit of the present invention.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than the embodiment of whole.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
As shown in figure 1, CMOS (the Complementary Metal Oxide described in the embodiment of the present invention
Semiconductor, complementary metal oxide semiconductors (CMOS)) logical block, including CMOS driver elements 10, also include：
Output voltage compensation unit 11, respectively with the outfan OUT of the CMOS driver elements 10 and output high level VGH
High level end connection, for when the CMOS driver elements 10 outfan OUT export voltage be more than predetermined voltage time control
The outfan OUT for making the CMOS driver elements 10 is connected with the high level end of the output high level VGH.
In practical operation, the predetermined voltage is high level, and the concrete magnitude of voltage of the predetermined voltage can be according to reality
Border situation is selected, and is not limited thereto.
COMS logic circuits described in the embodiment of the present invention are by being driven in the CMOS using output voltage compensation unit 11
The voltage of the outfan OUT outputs of moving cell 10 controls the outfan OUT and height of CMOS driver elements 10 when being more than predetermined voltage
Level terminal connects, to avoid that existing CMOS driver elements are present as the presence of static leakage current causes output level to decline
Phenomenon, can guarantee that CMOS driver elements output high level, maintains the driving force to subordinate's circuit.
Specifically, as shown in Fig. 2 the output voltage compensation unit 11 can include：
Inversed module 111, input are connected with the outfan OUT of the CMOS driver elements 10；And,
Compensation PMOS MCp, grid are connected with the outfan of the inversed module 111, and the first pole and the output are high electric
The high level end connection of flat VGH, the second pole is connected with the outfan OUT of the CMOS driver elements 10.
The embodiment of present invention CMOS logic unit as shown in Figure 2 is operationally, high electric in the output of CMOS driver elements
At ordinary times, turned on by 111 control and compensation PMOS MCp of inversed module, using increased compensation PMOS MCp as Leakage Current
Compensation transistor, using compensation PMOS strong by 1 (high level) characteristic and inversed module 111 logic upset, compensation work as
The static leakage current existed during the output high level of CMOS driver elements 10, compensates the loss of charge that existing leakage path is caused.
In an embodiment as illustrated in figure 2, PMOS MCp is compensated as the compensation crystal between high level VGH and Vout
Pipe, ensures Vout stable to ensure Vout and VGH to be consistent；Vout is the outfan OUT of the CMOS driver elements 10
The voltage of output.Conversely, when Vout is in low level, the outfan OUT output high level of CMOS driver elements 10, so as to institute
State compensation PMOS MCp to close, prevent the outfan OUT of the CMOS driver elements 10 to be driven high.
Preferably, the output voltage compensation unit can also include：
Compensating electric capacity, first end are connected with the outfan of the CMOS driver elements, the second end ground connection.
In the preferred case, the output voltage compensation unit also includes compensating electric capacity, for defeated to CMOS driver elements
The voltage for going out carries out voltage stabilizing.
In practical operation, the CMOS driver elements can include：
First PMOS (P-Metal-Oxide-Semiconductor, p-type Metal-oxide-semicondutor) manage, grid with
The input connection of the CMOS driver elements, the first pole are connected with the high level end, and the second pole drives single with the CMOS
The outfan connection of unit；And,
First NMOS (N-Metal-Oxide-Semiconductor, N-type Metal-oxide-semicondutor) manage, grid with
The input connection of the CMOS driver elements, the first pole is connected with low level end, the second pole and the CMOS driver elements
Outfan connects.
A specific embodiment of CMOS logic unit of the present invention is illustrated with reference to Fig. 3.
As shown in figure 3, a specific embodiment of CMOS logic unit of the present invention includes CMOS driver elements and defeated
Go out voltage compensation unit, wherein,
The CMOS driver elements include：
First PMOS Mfp, grid are connected with the input In of the CMOS driver elements, are drained and output high level
The high level end connection of VGH, source electrode are connected with the outfan OUT of the CMOS driver elements；And,
First NMOS tube Mfn, grid are connected with the input In of the CMOS driver elements, are drained and output low level
The low level end connection of VGL, source electrode are connected with the outfan OUT of the CMOS driver elements；
The output voltage compensation unit includes inversed module, compensation PMOS MCp and compensating electric capacity Cmp；
The first end of compensating electric capacity Cmp is connected with the outfan OUT of the CMOS driver elements, the compensating electric capacity
Second end of Cmp is connected with ground terminal GND；
The inversed module includes phase inverter F1；
The input of the phase inverter F1 is connected with the outfan OUT of the CMOS driver elements；
The grid of compensation PMOS MCp is connected with the outfan of the phase inverter F1, is drained and the high electricity of the output
The high level end connection of flat VGH, source electrode are connected with the outfan OUT of the CMOS driver elements.
In figure 3, Dp is the parasitic PMOS diodes of the Mfp when OUT exports high level, when Dn is that OUT exports high level
The parasitic NMOS diodes of Mfn；In can access the voltage signal that IC (Integrated Circuit, integrated circuit) exports or
Person's clock signal.
When OUT exports high level due to there is static leakage current (as shown in figure 3, the static leakage current includes flowing through
Conducting electric current Id of Mfp, the first leakage current Il1 for flowing through Mfn, the second leakage current Il2 for flowing through Dp and the three leakages for flowing through Dn
Electric current Il3 (anti-phase saturation currents of the Il3 for Dn), although conducting electric current Id can provide electric current, but Il1, Il2 and Il3 to OUT
Electric current is outwards extracted at OUT, therefore the voltage Vout of OUT outputs can be caused to remain VGH, the magnitude of voltage of Vout
Reduction can cause not enough to the gate circuit driving force of rear end, therefore present invention CMOS logic unit as shown in Figure 3 is concrete
Embodiment increases phase inverter F1 in OUT rear ends, and increases MCp between the high level end of output VGH and phase inverter F1 as letting out
The compensation transistor of dew electric current, using logic upset and strong 1 characteristic of MCp of phase inverter F1, by the logic work(of phase inverter F1
The loss of charge that lower section leakage path is caused can be compensated to control MCp conductings.
CMOS logic circuit described in the embodiment of the present invention includes the CMOS driver elements of N number of cascade；N is whole more than 1
Number；
Input and adjacent upper level CMOS in addition to first order CMOS driver element, per one-level CMOS driver element
The outfan connection of driver element；
The input of first order CMOS driver element is the input of the CMOS logic circuit；
The CMOS logic circuit also includes：Output voltage compensation element circuit, respectively with high level end and per one-level institute
The outfan connection of CMOS driver elements is stated, for being more than in advance by the voltage that its outfan is exported when the CMOS driver elements
Determine during voltage, to control the outfan to be connected with the high level end.
CMOS logic circuit described in the embodiment of the present invention includes the CMOS driver elements of multiple cascades, and also includes output
Voltage compensation unit circuit, the output voltage compensation element circuit can export high level time control in every one-level CMOS driver element
The outfan for making the CMOS driver elements is connected with high level end, single to avoid the CMOS in existing CMOS logic circuit from driving
Unit exist as the presence of static leakage current causes output level to decline phenomenon, can guarantee that the high electricity of CMOS driver elements output
It is flat, maintain the driving force to subordinate's circuit.
Specifically, the output voltage compensation element circuit can include：
First inversed module, input are connected with the outfan of the 2nd (m-1) level CMOS driver element；
Second inversed module, input are connected with the outfan of 2m level CMOS driver elements；And,
N number of compensation PMOS；
Each compensation PMOS is corresponding with CMOS driver elements described in one-level respectively；
The outfan of first inversed module and all compensation PMOS corresponding with odd level CMOS driver elements
Grid all connects；
The outfan of second inversed module and all compensation PMOS corresponding with even level CMOS driver elements
Grid all connects；
First pole of each compensation PMOS is all connected with the high level end；
Second pole of compensation PMOS corresponding with one-level CMOS driver element and the outfan of this grade of CMOS driver element
Connection；
M is arbitrary positive integer, and 2m is less than or equal to N.
Preferably, the output voltage compensation element circuit also includes：
N number of compensating electric capacity；
Each compensating electric capacity is corresponding with CMOS driver elements described in one-level respectively；
The first end of compensating electric capacity corresponding with one-level CMOS driver element is connected with the outfan of this grade of CMOS driver element
Connect, the second end of N number of compensating electric capacity is all grounded.
In the preferred case, the output voltage compensation unit also includes N number of compensating electric capacity, for driving to CMOS at different levels
The voltage of unit output carries out voltage stabilizing.
Specifically, can include respectively per one-level CMOS driver element：
First PMOS, grid are connected with the input of this grade of CMOS driver element, and the first pole is connected with the high level end
Connect, the second pole is connected with the outfan of this grade of CMOS driver element；And,
First NMOS tube, grid are connected with the input of this grade of CMOS driver element, and the first pole is connected with low level end, the
Two poles are connected with the outfan of this grade of CMOS driver element.
In the specific implementation, first inversed module can be the first phase inverter, and second inversed module can be
Second phase inverter.
In practical operation, every grade of CMOS driver element is required for one PMOS of respective production as output high level
Compensation transistor between the high level line of VGH and this grade of CMOS driver element, to ensure the output of this grade of CMOS driver element
Voltage is consistent so as to ensure output voltage stabilization with VGH.
When multistage CMOS driver elements are connected together, the first phase inverter and the second phase inverter can be added, described first
The grid connection of the outfan of phase inverter and compensation PMOS corresponding with odd level CMOS driver elements, second phase inverter
Outfan and it is corresponding with even level CMOS driver elements compensation PMOS grid connection, the input of first phase inverter
End can be connected with the outfan of arbitrary odd level CMOS driver elements, and the input of second phase inverter can be with arbitrary idol
The outfan connection of several levels CMOS driver element.
In the specific implementation, can adjust what the threshold voltage of the first phase inverter was done by channel width-over-length ratio by technological level
It is more slightly lower, as long as then can guarantee that the outfan of this grade of odd level CMOS driver element being connected with the input of first phase inverter
The voltage of output be high level (positive polarity) when, and the voltage more than first phase inverter threshold voltage when, this can be made
First phase inverter opens compensation PMOS corresponding with odd level CMOS driver elements.
In the specific implementation, can adjust what the threshold voltage of the second phase inverter was done by channel width-over-length ratio by technological level
It is more slightly lower, as long as then can guarantee that the outfan of this grade of even level CMOS driver element being connected with the input of second phase inverter
The voltage of output be high level (positive polarity) when, and the voltage more than second phase inverter threshold voltage when, this can be made
Second phase inverter opens compensation PMOS corresponding with even level CMOS driver elements.
Those skilled in the art will know that, in CMOS logic circuit, the threshold value of the first phase inverter and the second phase inverter
Voltage, less than the driving voltage for driving next stage circuit.
The outfan loading of the compensation PMOS transistor and the second phase inverter that are loaded due to the outfan of the first phase inverter
Compensation PMOS transistor it is more, then first phase inverter outfan load and second phase inverter outfan load compared with
Greatly, so the fan out capability (carrying load ability) of the first phase inverter and being fanned out to for the second phase inverter should be improved by process meanses
Ability with guarantee by each compensation PMOS normally open.
In the specific implementation, when the series of the CMOS driver elements for including when the CMOS logic circuit is even number, by the
The input of one phase inverter is connected with the outfan of penultimate stage CMOS driver element, by the input of the second phase inverter and
The outfan connection of number first order CMOS driver element；The series of the CMOS driver elements included when the CMOS logic circuit is
During odd number, the input of the first phase inverter is connected with the outfan of level CMOS driver element last, by the second phase inverter
Input be connected with the outfan of penultimate stage CMOS driver element；It is to consider that CMOS driver elements that ought be below are exported
For it is high when then ensure that COMS driver elements above have also reached high level, it is ensured that CMOS driver elements at different levels output
Level height concordance.
A specific embodiment of CMOS logic circuit of the present invention is illustrated with reference to Fig. 4.
As shown in figure 4, a specific embodiment of CMOS logic circuit of the present invention includes level Four CMOS driver element
With output voltage compensation element circuit, wherein,
The output voltage compensation element circuit includes：
First phase inverter F1, input are connected with the outfan OUT3 of third level CMOS driver elements；
Second phase inverter F2, input are connected with the outfan OUT4 of fourth stage CMOS driver elements；
The first compensation PMOS MCp1 corresponding with first order CMOS driver element；
The second compensation PMOS MCp2 corresponding with second level CMOS driver elements；
The 3rd compensation PMOS MCp3 corresponding with third level CMOS driver elements；
The 4th compensation PMOS MCp4 corresponding with fourth stage CMOS driver elements；
First compensating electric capacity Cmp1, first end are connected with the outfan OUT1 of first order CMOS driver element, the second end with
Ground terminal GND connects；
Second compensating electric capacity Cmp2, first end are connected with the outfan OUT2 of second level CMOS driver elements, the second end with
Ground terminal GND connects；
3rd compensating electric capacity Cmp3, first end are connected with the outfan OUT3 of third level CMOS driver elements, the second end with
Ground terminal GND connects；And,
4th compensating electric capacity Cmp4, first end are connected with the outfan OUT4 of fourth stage CMOS driver elements, the second end with
Ground terminal GND connects；
The outfan of the first phase inverter F1 and the grid with the first compensation PMOS MCp1 and the 3rd compensation PMOS
The grid connection of MCp3；
The outfan of the second phase inverter F2 and the grid with the second compensation PMOS MCp2 and the 4th compensation PMOS
The grid connection of MCp4；
The drain electrode of the first compensation PMOS MCp1, the drain electrode of the second compensation PMOS MCp2, the described 3rd mend
The drain electrode of the drain electrode and the 4th compensation PMOS MCp4 of repaying PMOS MCp3 is all connected with the high level end of output high level VGH
Connect；
The source electrode of the first compensation PMOS MCp1 is connected with the outfan OUT1 of first order CMOS driver element；
The source electrode of the second compensation PMOS MCp1 is connected with the outfan OUT2 of second level CMOS driver elements；
The source electrode of the 3rd compensation PMOS MCp3 is connected with the outfan OUT3 of third level CMOS driver elements；
The source electrode of the 4th compensation PMOS MCp4 is connected with the outfan OUT4 of fourth stage CMOS driver elements；
The first order CMOS driver element includes：
First PMOS Mfp1, grid are connected with the input IN1 of the first order CMOS driver element, drain with it is described
The high level end connection of output high level VGH, source electrode are connected with the outfan OUT1 of the first order CMOS driver element；With
And,
First NMOS tube Mfn1, grid are connected with the input IN1 of the first order CMOS driver element, are drained and output
The low level end connection of low level VGL, source electrode are connected with the outfan OUT1 of the first order CMOS driver element；
The second level CMOS driver elements include：
Second PMOS Mfp2, grid are connected with the input IN2 of the second level CMOS driver elements, drain with it is described
The high level end connection of output high level VGH, source electrode are connected with the outfan OUT2 of the second level CMOS driver elements；With
And,
Second NMOS tube Mfn2, grid are connected with the input IN2 of the second level CMOS driver elements, are drained and output
The low level end connection of low level VGL, source electrode are connected with the outfan OUT2 of the second level CMOS driver elements；
The third level CMOS driver elements include：
3rd PMOS Mfp3, grid are connected with the input IN3 of the third level CMOS driver elements, drain with it is described
The high level end connection of output high level VGH, source electrode are connected with the outfan OUT3 of the third level CMOS driver elements；With
And,
3rd NMOS tube Mfn3, grid are connected with the input IN3 of the third level CMOS driver elements, are drained and output
The low level end connection of low level VGL, source electrode are connected with the outfan OUT3 of the third level CMOS driver elements；
The fourth stage CMOS driver elements include：
4th PMOS Mfp4, grid are connected with the input IN4 of the fourth stage CMOS driver elements, drain with it is described
The high level end connection of output high level VGH, source electrode are connected with the outfan OUT4 of the fourth stage CMOS driver elements；With
And,
4th NMOS tube Mfn4, grid are connected with the input IN4 of the fourth stage CMOS driver elements, are drained and output
The low level end connection of low level VGL, source electrode are connected with the outfan OUT4 of the fourth stage CMOS driver elements；
Present invention CMOS logic circuit as shown in Figure 4 operationally,
When IN1 access low level when, OUT1 and OUT3 output high level, so as to F1 export low level so that MCp1 and
MCp3 is turned on, and all accesses VGH so as to control OUT1 and OUT3, so as to improve driving force；
When IN1 access high level when, OUT2 and OUT4 output high level, so as to F2 export low level so that MCp2 and
MCp4 is turned on, and all accesses VGH so as to control OUT2 and OUT4, so as to improve driving force.
In practical operation, CMOS logic circuit of the present invention generally comprises 4-6 level CMOS driver elements, from first
Level CMOS driver elements are less to postponing between last two-stage CMOS driver element, therefore the output voltage compensation element circuit
Including the first phase inverter, input and afterbody that input is connected with the outfan of penultimate stage CMOS driver element
Second phase inverter and compensation transistor corresponding with every one-level CMOS driver element of the outfan connection of CMOS driver elements
.
In the specific implementation, multistage CMOS driver elements can also be in parallel, namely the input of CMOS driver elements at different levels
It is connected with each other so that the signal synchronization of CMOS driver elements outfan outputs at different levels, then by output voltage compensation unit electricity
Road is ensureing the driving force of the CMOS driver elements at different levels.
Gate driver circuit described in the embodiment of the present invention, including above-mentioned CMOS logic unit, or, including above-mentioned
CMOS logic circuit.
Display device described in the embodiment of the present invention includes above-mentioned gate driver circuit.
The above is the preferred embodiment of the present invention, it is noted that for those skilled in the art
For, on the premise of without departing from principle of the present invention, some improvements and modifications can also be made, these improvements and modifications
Should be regarded as protection scope of the present invention.
Claims (10)
1. a kind of CMOS logic unit, including CMOS driver elements, it is characterised in that also include：
Output voltage compensation unit, is connected with the outfan of the CMOS driver elements and high level end respectively, for when described
The voltage of the outfan output of CMOS driver elements controls outfan and the institute of the CMOS driver elements when being more than predetermined voltage
State the connection of high level end.
2. CMOS logic unit as claimed in claim 1, it is characterised in that the output voltage compensation unit includes：
Inversed module, input are connected with the outfan of the CMOS driver elements；And,
Compensation PMOS, grid are connected with the outfan of the inversed module, and the first pole is connected with the high level end, the second pole
It is connected with the outfan of the CMOS driver elements.
3. CMOS logic unit as claimed in claim 2, it is characterised in that the output voltage compensation unit also includes：
Compensating electric capacity, first end are connected with the outfan of the CMOS driver elements, the second end ground connection.
4. the CMOS logic unit as described in any claim in claims 1 to 3, it is characterised in that the CMOS drives
Unit includes：
First PMOS, grid are connected with the input of the CMOS driver elements, and the first pole is connected with the high level end, the
Two poles are connected with the outfan of the CMOS driver elements；And,
First NMOS tube, grid are connected with the input of the CMOS driver elements, and the first pole is connected with low level end, the second pole
It is connected with the outfan of the CMOS driver elements.
5. a kind of CMOS logic circuit, it is characterised in that including the CMOS driver elements of N number of cascade；N is the integer more than 1；
In addition to first order CMOS driver element, drive with adjacent upper level CMOS per the input of one-level CMOS driver element
The outfan connection of unit；
The input of first order CMOS driver element is the input of the CMOS logic circuit；
The CMOS logic circuit also includes：Output voltage compensation element circuit, respectively with high level end and per described in one-level
The outfan connection of CMOS driver elements, for making a reservation for when the CMOS driver elements are more than by the voltage that its outfan is exported
Control the outfan to be connected with the high level end during voltage.
6. CMOS logic circuit as claimed in claim 5, it is characterised in that the output voltage compensation element circuit includes：
First inversed module, input are connected with the outfan of (2m-1) level CMOS driver element；
Second inversed module, input are connected with the outfan of 2m level CMOS driver elements；And,
N number of compensation PMOS；
Each compensation PMOS is corresponding with CMOS driver elements described in one-level respectively；
The grid of the outfan of first inversed module and all compensation PMOSs corresponding with odd level CMOS driver elements
All connect；
The grid of the outfan of second inversed module and all compensation PMOSs corresponding with even level CMOS driver elements
All connect；
First pole of each compensation PMOS is all connected with the high level end；
Second pole of compensation PMOS corresponding with one-level CMOS driver element is connected with the outfan of this grade of CMOS driver element；
M is arbitrary positive integer, and 2m is less than or equal to N.
7. CMOS logic circuit as claimed in claim 6, it is characterised in that the output voltage compensation element circuit also includes
N number of compensating electric capacity；
Each compensating electric capacity is corresponding with CMOS driver elements described in one-level respectively；
The first end of compensating electric capacity corresponding with one-level CMOS driver element is connected with the outfan of this grade of CMOS driver element, institute
The second end for stating N number of compensating electric capacity is all grounded.
8. the CMOS logic circuit as described in any claim in claim 5 to 7, it is characterised in that drive per one-level CMOS
Moving cell includes respectively：
First PMOS, grid are connected with the input of this grade of CMOS driver element, and the first pole is connected with the high level end, the
Two poles are connected with the outfan of this grade of CMOS driver element；And,
First NMOS tube, grid are connected with the input of this grade of CMOS driver element, and the first pole is connected with low level end, the second pole
It is connected with the outfan of this grade of CMOS driver element.
9. a kind of gate driver circuit, it is characterised in that the gate driver circuit is included such as arbitrary power in Claims 1-4
Profit requires described CMOS logic unit, or, the gate driver circuit is included as in claim 5 to 8, arbitrary right will
Seek described CMOS logic circuit.
10. a kind of display device, it is characterised in that including gate driver circuit as claimed in claim 9.
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