CN106505071B - thin film transistor array substrate and manufacturing method thereof - Google Patents
thin film transistor array substrate and manufacturing method thereof Download PDFInfo
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- CN106505071B CN106505071B CN201610909125.5A CN201610909125A CN106505071B CN 106505071 B CN106505071 B CN 106505071B CN 201610909125 A CN201610909125 A CN 201610909125A CN 106505071 B CN106505071 B CN 106505071B
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- 239000010409 thin film Substances 0.000 title claims abstract description 62
- 239000000758 substrate Substances 0.000 title claims abstract description 61
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 24
- 238000005224 laser annealing Methods 0.000 claims description 16
- 238000001259 photo etching Methods 0.000 claims description 7
- 229920001621 AMOLED Polymers 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 7
- 239000013078 crystal Substances 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
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Abstract
The invention provides a thin film transistor array substrate and a manufacturing method thereof. According to the thin film transistor array substrate, the current conduction direction of the channel of the TFT in the display area is perpendicular to the ELA laser scanning direction, so that grains of the channel of the TFT in the display area are arranged relatively disorderly in the current conduction direction, the off-state current of the TFT in the display area is reduced, and the display area has good potential holding capacity; meanwhile, the current conduction direction of the channel of the TFT in the driving circuit area is set to be parallel to the ELA laser scanning direction, so that grains of the channel of the TFT in the driving circuit area are arranged in order in the current conduction direction, the off-state current of the TFT in the driving circuit area is improved, and the field mobility and the output current characteristic of the TFT in the driving circuit area are improved; the thin film transistor array substrate can meet different characteristic requirements of the display area TFT and the drive circuit area TFT, so that the overall display effect of the display panel is improved.
Description
Technical Field
the invention relates to the technical field of display, in particular to a thin film transistor array substrate and a manufacturing method thereof.
background
thin Film Transistors (TFTs) are the main driving elements in Liquid Crystal Displays (LCDs) and Active Matrix Organic electroluminescent displays (AMOLEDs), and are directly related to the development of high performance flat panel displays. The active layer of the thin film transistor is made of various materials, Low Temperature Polysilicon (LTPS) is a preferred material, because atoms of the Low Temperature polysilicon are regularly arranged, the carrier mobility is high, and for a voltage-driven liquid crystal display device, the Low Temperature polysilicon thin film transistor has high mobility, and can realize deflection driving of liquid crystal molecules by using a thin film transistor with a small volume, thereby reducing the volume occupied by the thin film transistor to a great extent, increasing the light transmission area and obtaining higher brightness and resolution; for the current-driven active matrix driving type organic electroluminescent display device, the low-temperature polycrystalline silicon thin film transistor can better meet the requirement of driving current.
as shown in fig. 1, the conventional thin film transistor array substrate is composed of a display area 100 and a driving circuit area 200, where the display area 100 is provided with a display area TFT, and the driving circuit area 200 is provided with a driving circuit area TFT. As shown in fig. 2, the display region TFT and the driving circuit region TFT in the thin film transistor array substrate of fig. 1 are shown, and as can be seen from fig. 2, the display region TFT includes a first active layer 300 and a first gate electrode 400 which are stacked up and down and separated by an insulating layer, the first active layer 300 is U-shaped and includes a first vertical portion 310 and a second vertical portion 320 which are parallel to each other, and a transverse connecting portion 330 which respectively connects corresponding ends of the first vertical portion 310 and the second vertical portion 320, the first gate electrode 400 is respectively vertically intersected with the first vertical portion 310 and the second vertical portion 320, a region of the first vertical portion 310 which is intersected and overlapped with the first gate electrode 400 forms a first channel 315, and a region of the second vertical portion 320 which is intersected and overlapped with the first gate electrode 400 forms a second channel 325;
A first source contact region 311 is disposed at an end of the first vertical portion 310 away from the transverse connection portion 330, and a first drain contact region 321 is disposed at an end of the second vertical portion 320 away from the transverse connection portion 330;
when the display region TFT operates, current in the first active layer 300 flows between the first source contact region 311 and the first drain contact region 321, i.e., along a U-shaped channel, and thus, current conduction directions in the first channel 315 and the second channel 325 are parallel to the extending directions of the first upright portion 310 and the second upright portion 320;
The driving circuit region TFT comprises a second active layer 500 and a second gate electrode 600 which are stacked up and down and separated by an insulating layer, the second active layer 500 is in a vertical strip shape, the second gate electrode 600 is vertically crossed with the second active layer 500, and a third channel 550 is formed in a region of the second active layer 500, which is crossed and overlapped with the second gate electrode 600;
a second source contact region 510 and a second drain contact region 520 are respectively disposed at two ends of the second active layer 500;
When the driving circuit region TFT is operated, a current in the second active layer 500 flows between the second source contact region 510 and the second drain contact region 520, i.e., flows in an extending direction of the second active layer 500, and thus, a current conduction direction in the third channel 550 is parallel to the extending direction of the second active layer 500;
in the thin film transistor array substrate, the extending directions of the first and second vertical portions 310 and 320 of the first active layer 300 are parallel to the extending direction of the second active layer 500, and thus it can be seen that the current conduction directions in the first and second channels 315 and 325 of the first active layer 300 and the current conduction direction in the third channel 550 of the second active layer 500 are parallel to each other.
In the above method for manufacturing the thin film transistor array substrate, the manufacturing process of the first active layer 300 of the display region TFT and the second active layer 500 of the driving circuit region TFT includes: an amorphous silicon (a-Si) layer is deposited on a glass substrate, a low-temperature polysilicon layer is obtained through an Excimer Laser Annealing (ELA) process, and then the low-temperature polysilicon layer is subjected to patterning processing, and a first active layer 300 of the display region TFT and a second active layer 500 of the driving circuit region TFT are formed at the same time.
In the above method for manufacturing the tft array substrate, when the amorphous silicon is crystallized by the ELA process, the ELA laser scanning direction is generally set to be parallel to the current conducting directions in the first channel 315, the second channel 325, and the third channel 550, and the polycrystalline silicon crystallized from the amorphous silicon after the ELA process generally has the characteristics shown in fig. 3, that is, the crystal grains are arranged more orderly in the ELA laser scanning direction (gray arrow direction), and the crystal grains are arranged less orderly in the direction perpendicular to the ELA laser scanning direction. For a TFT device, in the channel of the active layer, the ordered arrangement of crystal grains in the current conduction direction can reduce the obstruction of carriers in the transmission process, improve the mobility, and increase the on-state current, but the off-state current can also increase due to the ordered arrangement of grain boundaries. Therefore, according to the existing method for manufacturing the thin film transistor array substrate, the ELA laser scanning direction is parallel to the current conduction direction in the first channel 315, the second channel 325 and the third channel 550, so that the obtained crystal grains in the first channel 315, the second channel 325 and the third channel 550 can be orderly arranged in the current conduction direction, and thus, the display region TFT and the driving circuit region TFT both have large on-state current and off-state current.
For the display panel, the TFT in the driving circuit region is used for the logic circuit, and needs to have a large on-state current; however, the TFT in the display region needs to have a better potential holding capability and a lower off-state current, that is, the TFT array substrate prepared according to the prior art cannot meet the requirement.
disclosure of Invention
the invention aims to provide a thin film transistor array substrate, wherein a display area has better potential holding capacity, and a driving circuit area has better field mobility and output current characteristics.
the invention also aims to provide a manufacturing method of the thin film transistor array substrate, which has simple manufacturing process, and the manufactured thin film transistor array substrate has better potential holding capacity in a display area and better field mobility and output current characteristics in a driving circuit area.
in order to achieve the above object, the present invention first provides a thin film transistor array substrate, including a display area and a driving circuit area arranged at the periphery of the display area, wherein the display area is provided with a display area TFT, and the driving circuit area is provided with a driving circuit area TFT;
The active layer of the display area TFT and the active layer of the driving circuit area TFT are both made of low-temperature polycrystalline silicon; the current conduction direction of the channel of the display area TFT is perpendicular to the current conduction direction of the channel of the driving circuit area TFT.
The display area TFT comprises a first active layer and a first grid electrode which are stacked up and down and are separated by an insulating layer, the first active layer is U-shaped and comprises a first vertical part and a second vertical part which are parallel to each other and a transverse connecting part which is respectively connected with the corresponding ends of the first vertical part and the second vertical part, the first grid electrode is respectively and vertically crossed with the first vertical part and the second vertical part, a first channel is formed in the area of the first vertical part, which is crossed and overlapped with the first grid electrode, and a second channel is formed in the area of the second vertical part, which is crossed and overlapped with the first grid electrode;
a first source electrode contact region is arranged at one end, far away from the transverse connecting part, of the first vertical part, and a first drain electrode contact region is arranged at one end, far away from the transverse connecting part, of the second vertical part;
When the display region TFT is operated, current in the first active layer flows between the first source electrode contact region and the first drain electrode contact region, namely flows along a U-shaped channel, so that the current conduction directions in the first channel and the second channel are parallel to the extension directions of the first vertical part and the second vertical part;
The driving circuit region TFT comprises a second active layer and a second grid electrode which are vertically stacked and separated by an insulating layer, the second active layer is in a straight strip shape, the second grid electrode is vertically crossed with the second active layer, and a third channel is formed in the region, crossed and overlapped with the second grid electrode, of the second active layer;
A second source contact region and a second drain contact region are respectively arranged at two ends of the second active layer;
When the driving circuit region TFT is operated, a current in the second active layer flows between the second source contact region and the second drain contact region, that is, along an extending direction of the second active layer, and thus a current conduction direction in the third channel is parallel to the extending direction of the second active layer;
In the thin film transistor array substrate, the extending directions of the first and second vertical portions of the first active layer are perpendicular to the extending direction of the second active layer, so that the current conduction directions in the first and second channels of the first active layer are perpendicular to the current conduction direction in the third channel of the second active layer.
the thin film transistor array substrate is applied to an LCD display panel or an AMOLED display panel.
the invention also provides a manufacturing method of the thin film transistor array substrate, the thin film transistor array substrate comprises a display area and a driving circuit area arranged at the periphery of the display area, the display area is internally provided with a display area TFT, the driving circuit area is internally provided with a driving circuit area TFT, the current conduction direction of a channel of the display area TFT is vertical to the current conduction direction of a channel of the driving circuit area TFT, and the manufacturing method of the thin film transistor array substrate comprises the following steps:
depositing an amorphous silicon layer;
crystallizing the amorphous silicon layer by adopting an excimer laser annealing method to convert the amorphous silicon layer into a low-temperature polycrystalline silicon layer;
when the amorphous silicon layer is crystallized by adopting an excimer laser annealing method, the laser scanning direction is vertical to the current conduction direction of the channel of the TFT in the display area and is parallel to the current conduction direction of the channel of the TFT in the driving circuit area;
and carrying out graphical processing on the low-temperature polycrystalline silicon layer by adopting a photoetching technology, and simultaneously forming an active layer of the display area TFT and an active layer of the driving circuit area TFT.
The display area TFT comprises a first active layer and a first grid electrode which are stacked up and down and are separated by an insulating layer, the first active layer is U-shaped and comprises a first vertical part and a second vertical part which are parallel to each other and a transverse connecting part which is respectively connected with the corresponding ends of the first vertical part and the second vertical part, the first grid electrode is respectively and vertically crossed with the first vertical part and the second vertical part, a first channel is formed in the area of the first vertical part, which is crossed and overlapped with the first grid electrode, and a second channel is formed in the area of the second vertical part, which is crossed and overlapped with the first grid electrode;
a first source electrode contact region is arranged at one end, far away from the transverse connecting part, of the first vertical part, and a first drain electrode contact region is arranged at one end, far away from the transverse connecting part, of the second vertical part;
when the display region TFT is operated, current in the first active layer flows between the first source electrode contact region and the first drain electrode contact region, namely, flows along a U-shaped channel, so that the current conduction directions in the first channel and the second channel are parallel to the extension directions of the first vertical portion and the second vertical portion.
the driving circuit region TFT comprises a second active layer and a second grid electrode which are vertically stacked and separated by an insulating layer, the second active layer is in a straight strip shape, the second grid electrode is vertically crossed with the second active layer, and a third channel is formed in the region, crossed and overlapped with the second grid electrode, of the second active layer;
A second source contact region and a second drain contact region are respectively arranged at two ends of the second active layer;
When the driving circuit region TFT operates, a current in the second active layer flows between the second source contact region and the second drain contact region, that is, along an extending direction of the second active layer, and thus, a current conduction direction in the third channel is parallel to the extending direction of the second active layer.
in the thin film transistor array substrate, the extending directions of the first and second vertical portions of the first active layer are perpendicular to the extending direction of the second active layer, so that the current conduction directions in the first and second channels of the first active layer are perpendicular to the current conduction direction in the third channel of the second active layer.
when the amorphous silicon layer is crystallized by the excimer laser annealing method, the laser scanning direction is perpendicular to the extending direction of the first vertical portion and the second vertical portion and is parallel to the extending direction of the second active layer, namely, the laser scanning direction is perpendicular to the current conduction direction in the first channel and the second channel of the first active layer and is parallel to the current conduction direction in the third channel of the second active layer.
And when the low-temperature polycrystalline silicon layer is subjected to graphical processing by adopting a photoetching technology, a first active layer of the display area TFT and a second active layer of the driving circuit area TFT are formed at the same time.
The manufacturing method of the thin film transistor array substrate is applied to the manufacturing method of the LCD display panel or the manufacturing method of the AMOLED display panel.
the invention has the beneficial effects that: according to the thin film transistor array substrate provided by the invention, the current conduction direction of the channel of the TFT in the display area is set to be vertical to the ELA laser scanning direction, so that the crystal grains of the channel of the TFT in the display area are arranged relatively disorderly in the current conduction direction, the off-state current of the TFT in the display area is reduced, and the display area has better potential holding capacity; meanwhile, the current conduction direction of the channel of the TFT in the driving circuit area is set to be parallel to the ELA laser scanning direction, so that grains of the channel of the TFT in the driving circuit area are arranged in order in the current conduction direction, the off-state current of the TFT in the driving circuit area is improved, and the field mobility and the output current characteristic of the TFT in the driving circuit area are improved; the thin film transistor array substrate can meet different characteristic requirements of the display area TFT and the drive circuit area TFT, so that the overall display effect of the display panel is improved. The manufacturing method of the thin film transistor array substrate provided by the invention has the advantages that the manufacturing process is simple, the manufactured thin film transistor array substrate has better potential holding capacity in the display area, and better field mobility and output current characteristics in the driving circuit area, and the whole display effect of a panel can be improved when the thin film transistor array substrate is applied to the display panel.
For a better understanding of the nature and technical aspects of the present invention, reference should be made to the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are provided for purposes of illustration and description and are not intended to limit the invention.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
in the drawings, there is shown in the drawings,
Fig. 1 is a schematic structural diagram of a conventional thin film transistor array substrate;
Fig. 2 is a schematic structural diagram of a display region TFT and a driving circuit region TFT in the thin film transistor array substrate of fig. 1;
FIG. 3 is a schematic diagram showing the arrangement of crystal grains of polycrystalline silicon crystallized from amorphous silicon after excimer laser annealing;
FIG. 4 is a schematic structural diagram of a TFT array substrate according to the present invention;
Fig. 5 is a schematic structural diagram of a display region TFT and a driving circuit region TFT in the thin film transistor array substrate of the present invention.
Detailed Description
to further illustrate the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Referring to fig. 4, the present invention first provides a thin film transistor array substrate, including a display area 10 and a driving circuit area 20 disposed at the periphery of the display area 10, wherein a display area TFT is disposed in the display area 10, and a driving circuit area TFT is disposed in the driving circuit area 20;
the active layer of the display area TFT and the active layer of the driving circuit area TFT are both made of low-temperature polycrystalline silicon; the current conduction direction of the channel of the display area TFT is perpendicular to the current conduction direction of the channel of the driving circuit area TFT.
In the thin film transistor array substrate, the active layer of the display region TFT and the active layer of the driving circuit region TFT are formed in the same process, and the process includes:
step 1, depositing an amorphous silicon layer;
step 2, crystallizing the amorphous silicon layer by adopting an excimer laser annealing method to convert the amorphous silicon layer into a low-temperature polycrystalline silicon layer;
step 3, carrying out graphical processing on the low-temperature polycrystalline silicon layer by adopting a photoetching technology, and simultaneously forming an active layer of the display area TFT and an active layer of the driving circuit area TFT;
In the step 2, when the amorphous silicon layer is crystallized by an excimer laser annealing method, the laser scanning direction is perpendicular to the current conduction direction of the channel of the display region TFT and parallel to the current conduction direction of the channel of the drive circuit region TFT; therefore, in the channel of the display area TFT, the crystal grains are arranged relatively disorderly in the current conduction direction, and the off-state current of the display area TFT is reduced, so that the display area 10 has better potential holding capacity; in the channel of the TFT in the driving circuit region, the grains are arranged relatively in order in the current conduction direction, so that the off-state current of the TFT in the driving circuit region is increased, thereby improving the field mobility and the output current characteristics of the TFT in the driving circuit region 20.
Preferably, as shown in fig. 5, the display region TFT includes a first active layer 30 and a first gate electrode 40 stacked one on another and separated by an insulating layer (not shown), the first active layer 30 is U-shaped and includes a first vertical portion 31 and a second vertical portion 32 parallel to each other, and a transverse connecting portion 33 respectively connecting corresponding ends of the first vertical portion 31 and the second vertical portion 32, the first gate electrode 40 is perpendicularly intersected with the first vertical portion 31 and the second vertical portion 32, a region of the first vertical portion 31 intersected and overlapped with the first gate electrode 40 forms a first channel 312, and a region of the second vertical portion 32 intersected and overlapped with the first gate electrode 40 forms a second channel 322;
a first source contact region 314 is arranged at one end of the first vertical portion 31 away from the transverse connecting portion 33, and a first drain contact region 324 is arranged at one end of the second vertical portion 32 away from the transverse connecting portion 33;
when the display region TFT is operated, a current in the first active layer 30 flows between the first source contact region 314 and the first drain contact region 324, i.e., along a U-shaped channel, and thus, current conduction directions in the first channel 312 and the second channel 322 are parallel to the extending directions of the first upright portion 31 and the second upright portion 32;
the driving circuit region TFT comprises a second active layer 50 and a second grid electrode 60 which are stacked up and down and are separated by an insulating layer, the second active layer 50 is in a straight strip shape, the second grid electrode 60 is vertically crossed with the second active layer 50, and a third channel 55 is formed in the area, crossed and overlapped with the second grid electrode 60, of the second active layer 50;
A second source contact region 51 and a second drain contact region 52 are respectively disposed at two ends of the second active layer 50;
when the driving circuit region TFT is operated, a current in the second active layer 50 flows between the second source contact region 51 and the second drain contact region 52, that is, along the extending direction of the second active layer 50, and thus, the current conduction direction in the third channel 55 is parallel to the extending direction of the second active layer 50;
in the thin film transistor array substrate, the first and second vertical portions 31 and 32 of the first active layer 30 extend in a direction perpendicular to the second active layer 50, so that the current conduction directions in the first and second channels 312 and 322 of the first active layer 30 are perpendicular to the current conduction direction in the third channel 55 of the second active layer 50.
in the above preferred embodiment of the TFT array substrate, the first active layer 30 of the display region TFT and the second active layer 50 of the driving circuit region TFT are formed in the same process, where the process includes:
step 10, depositing an amorphous silicon layer;
step 20, crystallizing the amorphous silicon layer by adopting an excimer laser annealing method to convert the amorphous silicon layer into a low-temperature polycrystalline silicon layer;
Step 30, carrying out graphical processing on the low-temperature polycrystalline silicon layer by adopting a photoetching technology, and simultaneously forming a first active layer 30 of the display area TFT and a second active layer 50 of the driving circuit area TFT;
In the step 20, when the amorphous silicon layer is crystallized by the excimer laser annealing method, the laser scanning direction is perpendicular to the extending direction of the first vertical portion 31 and the second vertical portion 32 and parallel to the extending direction of the second active layer 50, that is, the laser scanning direction is perpendicular to the current conducting direction in the first channel 312 and the second channel 322 of the first active layer 30 and parallel to the current conducting direction in the third channel 55 of the second active layer 50. Therefore, in the first channel 312 and the second channel 322 of the first active layer 30, the crystal grain arrangement of the polysilicon is relatively disordered in the current conduction direction, so that the display region TFT has smaller on-state current and off-state current, and the display region 10 has better potential retention capability; in the third channel 55 of the second active layer 50, the grains are arranged relatively in order in the current conduction direction, so that the TFT in the driving circuit region has a large on-state current and an off-state current, and the field mobility and the output current characteristics of the driving circuit region 20 are improved.
specifically, the thin film transistor array substrate of the present invention can be applied to an LCD display panel or an AMOLED display panel.
According to the thin film transistor array substrate, the current conduction direction of the channel of the TFT in the display area is perpendicular to the ELA laser scanning direction, so that grains of the channel of the TFT in the display area are arranged relatively disorderly in the current conduction direction, the off-state current of the TFT in the display area is reduced, and the display area 10 has good potential holding capacity; meanwhile, the current conduction direction of the channel of the TFT in the driving circuit area is set to be parallel to the ELA laser scanning direction, so that grains of the channel of the TFT in the driving circuit area are arranged in order in the current conduction direction, the off-state current of the TFT in the driving circuit area is improved, and the field mobility and the output current characteristic of the TFT in the driving circuit area 20 are improved; the thin film transistor array substrate can meet different characteristic requirements of the display area TFT and the drive circuit area TFT, so that the overall display effect of the display panel is improved.
the invention also provides a manufacturing method of the thin film transistor array substrate, the thin film transistor array substrate comprises a display area 10 and a drive circuit area 20 arranged at the periphery of the display area 10, a display area TFT is arranged in the display area 10, a drive circuit area TFT is arranged in the drive circuit area 20, wherein the current conduction direction of a channel of the display area TFT is vertical to the current conduction direction of a channel of the drive circuit area TFT, and the manufacturing method of the thin film transistor array substrate comprises the following steps:
depositing an amorphous silicon layer;
crystallizing the amorphous silicon layer by adopting an excimer laser annealing method to convert the amorphous silicon layer into a low-temperature polycrystalline silicon layer;
when the amorphous silicon layer is crystallized by adopting an excimer laser annealing method, the laser scanning direction is vertical to the current conduction direction of the channel of the TFT in the display area and is parallel to the current conduction direction of the channel of the TFT in the driving circuit area;
and carrying out graphical processing on the low-temperature polycrystalline silicon layer by adopting a photoetching technology, and simultaneously forming an active layer of the display area TFT and an active layer of the driving circuit area TFT.
Preferably, as shown in fig. 5, the display region TFT includes a first active layer 30 and a first gate electrode 40 stacked one on another and separated by an insulating layer (not shown), the first active layer 30 is U-shaped and includes a first vertical portion 31 and a second vertical portion 32 parallel to each other, and a transverse connecting portion 33 respectively connecting corresponding ends of the first vertical portion 31 and the second vertical portion 32, the first gate electrode 40 is perpendicularly intersected with the first vertical portion 31 and the second vertical portion 32, a region of the first vertical portion 31 intersected and overlapped with the first gate electrode 40 forms a first channel 312, and a region of the second vertical portion 32 intersected and overlapped with the first gate electrode 40 forms a second channel 322;
a first source contact region 314 is arranged at one end of the first vertical portion 31 away from the transverse connecting portion 33, and a first drain contact region 324 is arranged at one end of the second vertical portion 32 away from the transverse connecting portion 33;
when the display region TFT is operated, a current in the first active layer 30 flows between the first source contact region 314 and the first drain contact region 324, i.e., along a U-shaped channel, and thus, current conduction directions in the first channel 312 and the second channel 322 are parallel to the extending directions of the first upright portion 31 and the second upright portion 32;
the driving circuit region TFT comprises a second active layer 50 and a second grid electrode 60 which are stacked up and down and are separated by an insulating layer, the second active layer 50 is in a straight strip shape, the second grid electrode 60 is vertically crossed with the second active layer 50, and a third channel 55 is formed in the area, crossed and overlapped with the second grid electrode 60, of the second active layer 50;
A second source contact region 51 and a second drain contact region 52 are respectively disposed at two ends of the second active layer 50;
when the driving circuit region TFT is operated, a current in the second active layer 50 flows between the second source contact region 51 and the second drain contact region 52, that is, along the extending direction of the second active layer 50, and thus, the current conduction direction in the third channel 55 is parallel to the extending direction of the second active layer 50;
In the thin film transistor array substrate, the first and second vertical portions 31 and 32 of the first active layer 30 extend in a direction perpendicular to the second active layer 50, so that the current conduction directions in the first and second channels 312 and 322 of the first active layer 30 are perpendicular to the current conduction direction in the third channel 55 of the second active layer 50.
at this time, in the manufacturing method of the thin film transistor array substrate, when the amorphous silicon layer is crystallized by using the excimer laser annealing method, the laser scanning direction is perpendicular to the extending direction of the first vertical portion 31 and the second vertical portion 32 and is parallel to the extending direction of the second active layer 50, that is, the laser scanning direction is perpendicular to the current conduction direction in the first channel 312 and the second channel 322 of the first active layer 30 and is parallel to the current conduction direction in the third channel 55 of the second active layer 50;
and when the patterning treatment is carried out on the low-temperature polycrystalline silicon layer by adopting the photoetching technology, a first active layer 30 of the display area TFT and a second active layer 50 of the driving circuit area TFT are formed at the same time.
specifically, the manufacturing method of the thin film transistor array substrate of the present invention can be applied to a manufacturing method of an LCD display panel or a manufacturing method of an AMOLED display panel.
According to the manufacturing method of the thin film transistor array substrate, by utilizing the structural characteristics of the thin film transistor array substrate, when the amorphous silicon layer is crystallized by adopting an excimer laser annealing method, the laser scanning direction is set to be vertical to the current conduction direction of the channel of the TFT in the display area and parallel to the current conduction direction of the channel of the TFT in the driving circuit area, the grain arrangement of the obtained channel of the TFT in the display area is relatively disordered in the current conduction direction, the off-state current of the TFT is low, and the display area 10 has better potential holding capacity; the obtained channel of the TFT in the driving circuit area has relatively ordered grain arrangement in the current conduction direction, and the off-state current of the TFT is high, so that the field mobility and the output current characteristic of the driving circuit area 20 are improved.
in summary, the present invention provides a thin film transistor array substrate and a method for fabricating the same. According to the thin film transistor array substrate, the current conduction direction of the channel of the TFT in the display area is perpendicular to the ELA laser scanning direction, so that grains of the channel of the TFT in the display area are arranged relatively disorderly in the current conduction direction, the off-state current of the TFT in the display area is reduced, and the display area has good potential holding capacity; meanwhile, the current conduction direction of the channel of the TFT in the driving circuit area is set to be parallel to the ELA laser scanning direction, so that grains of the channel of the TFT in the driving circuit area are arranged in order in the current conduction direction, the off-state current of the TFT in the driving circuit area is improved, and the field mobility and the output current characteristic of the TFT in the driving circuit area are improved; the thin film transistor array substrate can meet different characteristic requirements of the display area TFT and the drive circuit area TFT, so that the overall display effect of the display panel is improved. The manufacturing method of the thin film transistor array substrate is simple in manufacturing process, the manufactured thin film transistor array substrate is good in potential holding capacity of the display area, good in field mobility and output current characteristics of the driving circuit area, and capable of improving the overall display effect of a panel when applied to the display panel.
As described above, it will be apparent to those skilled in the art that other various changes and modifications may be made based on the technical solution and concept of the present invention, and all such changes and modifications are intended to fall within the scope of the appended claims.
Claims (6)
1. A thin film transistor array substrate is characterized by comprising a display area (10) and a driving circuit area (20) arranged on the periphery of the display area (10), wherein a display area TFT is arranged in the display area (10), and a driving circuit area TFT is arranged in the driving circuit area (20);
the active layer of the display area TFT and the active layer of the driving circuit area TFT are both made of low-temperature polycrystalline silicon; the current conduction direction of the channel of the display area TFT is vertical to the current conduction direction of the channel of the driving circuit area TFT;
the display region TFT comprises a first active layer (30) and a first grid electrode (40) which are arranged in an up-and-down stacking mode and are separated by an insulating layer, the first active layer (30) is in a U shape and comprises a first vertical portion (31) and a second vertical portion (32) which are parallel to each other and a transverse connecting portion (33) which respectively connects the corresponding ends of the first vertical portion (31) and the second vertical portion (32), the first grid electrode (40) is respectively and vertically crossed with the first vertical portion (31) and the second vertical portion (32), a first channel (312) is formed in the region, crossed and overlapped with the first grid electrode (40), of the first vertical portion (31), and a second channel (322) is formed in the region, crossed and overlapped with the first grid electrode (40), of the second vertical portion (32);
A first source contact region (314) is arranged at one end, far away from the transverse connecting portion (33), of the first vertical portion (31), and a first drain contact region (324) is arranged at one end, far away from the transverse connecting portion (33), of the second vertical portion (32);
when the display region TFT is operated, current in the first active layer (30) flows between the first source contact region (314) and the first drain contact region (324), namely, flows along a U-shaped channel, so that the current conduction directions in the first channel (312) and the second channel (322) are parallel to the extension directions of the first upright portion (31) and the second upright portion (32);
the driving circuit region TFT comprises a second active layer (50) and a second grid electrode (60) which are arranged in an up-down stacking mode and are separated by an insulating layer, the second active layer (50) is in a straight strip shape, the second grid electrode (60) is vertically crossed with the second active layer (50), and a third channel (55) is formed in the area, crossed and overlapped with the second grid electrode (60), of the second active layer (50);
A second source contact region (51) and a second drain contact region (52) are respectively arranged at two ends of the second active layer (50);
-when said TFT of the driver circuit region is in operation, a current in said second active layer (50) flows between said second source contact region (51) and said second drain contact region (52), i.e. along the extension direction of said second active layer (50), so that the current conduction direction in said third channel (55) is parallel to the extension direction of said second active layer (50);
In the thin film transistor array substrate, the extending directions of the first and second vertical portions (31, 32) of the first active layer (30) are perpendicular to the extending direction of the second active layer (50), so that the current conduction directions in the first and second channels (312, 322) of the first active layer (30) are perpendicular to the current conduction direction in the third channel (55) of the second active layer (50).
2. The thin film transistor array substrate of claim 1, applied to an LCD display panel or an AMOLED display panel.
3. A manufacturing method of a thin film transistor array substrate comprises a display area (10) and a driving circuit area (20) arranged on the periphery of the display area (10), wherein a display area TFT is arranged in the display area (10), and a driving circuit area TFT is arranged in the driving circuit area (20), wherein the current conduction direction of a channel of the display area TFT is perpendicular to the current conduction direction of a channel of the driving circuit area TFT, and the manufacturing method of the thin film transistor array substrate is characterized by comprising the following steps:
Depositing an amorphous silicon layer;
crystallizing the amorphous silicon layer by adopting an excimer laser annealing method to convert the amorphous silicon layer into a low-temperature polycrystalline silicon layer;
when the amorphous silicon layer is crystallized by adopting an excimer laser annealing method, the laser scanning direction is vertical to the current conduction direction of the channel of the TFT in the display area and is parallel to the current conduction direction of the channel of the TFT in the driving circuit area;
carrying out graphical processing on the low-temperature polycrystalline silicon layer by adopting a photoetching technology, and simultaneously forming an active layer of the display area TFT and an active layer of the driving circuit area TFT;
the display region TFT comprises a first active layer (30) and a first grid electrode (40) which are arranged in an up-and-down stacking mode and are separated by an insulating layer, the first active layer (30) is in a U shape and comprises a first vertical portion (31) and a second vertical portion (32) which are parallel to each other and a transverse connecting portion (33) which respectively connects the corresponding ends of the first vertical portion (31) and the second vertical portion (32), the first grid electrode (40) is respectively and vertically crossed with the first vertical portion (31) and the second vertical portion (32), a first channel (312) is formed in the region, crossed and overlapped with the first grid electrode (40), of the first vertical portion (31), and a second channel (322) is formed in the region, crossed and overlapped with the first grid electrode (40), of the second vertical portion (32);
A first source contact region (314) is arranged at one end, far away from the transverse connecting portion (33), of the first vertical portion (31), and a first drain contact region (324) is arranged at one end, far away from the transverse connecting portion (33), of the second vertical portion (32);
when the display region TFT is operated, current in the first active layer (30) flows between the first source contact region (314) and the first drain contact region (324), namely, flows along a U-shaped channel, so that the current conduction directions in the first channel (312) and the second channel (322) are parallel to the extension directions of the first upright portion (31) and the second upright portion (32);
the driving circuit region TFT comprises a second active layer (50) and a second grid electrode (60) which are arranged in an up-down stacking mode and are separated by an insulating layer, the second active layer (50) is in a straight strip shape, the second grid electrode (60) is vertically crossed with the second active layer (50), and a third channel (55) is formed in the area, crossed and overlapped with the second grid electrode (60), of the second active layer (50);
a second source contact region (51) and a second drain contact region (52) are respectively arranged at two ends of the second active layer (50);
when the driving circuit region TFT is operated, a current in the second active layer (50) flows between the second source contact region (51) and the second drain contact region (52), i.e., along an extending direction of the second active layer (50), and thus, a current conduction direction in the third channel (55) is parallel to the extending direction of the second active layer (50).
4. the method of fabricating the thin film transistor array substrate of claim 3, wherein the first and second vertical portions (31, 32) of the first active layer (30) extend in a direction perpendicular to the second active layer (50) such that a current conduction direction in the first and second channels (312, 322) of the first active layer (30) is perpendicular to a current conduction direction in the third channel (55) of the second active layer (50).
5. The method of claim 4, wherein when the amorphous silicon layer is crystallized by excimer laser annealing, a laser scanning direction is perpendicular to the extending direction of the first and second vertical portions (31, 32) and parallel to the extending direction of the second active layer (50), which is equivalent to the laser scanning direction being perpendicular to the current conduction direction in the first and second channels (312, 322) of the first active layer (30) and parallel to the current conduction direction in the third channel (55) of the second active layer (50).
6. the method of manufacturing the thin film transistor array substrate of claim 3, wherein the method is applied to a method of manufacturing an LCD display panel or a method of manufacturing an AMOLED display panel.
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| CN108320705B (en) | 2018-02-14 | 2021-04-27 | 京东方科技集团股份有限公司 | Pixel unit, manufacturing method thereof and array substrate |
| CN109742088B (en) * | 2018-12-29 | 2021-03-16 | 武汉华星光电技术有限公司 | TFT array substrate |
| CN109727921B (en) * | 2019-01-02 | 2021-12-10 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method and display panel |
| CN113348557A (en) | 2019-10-22 | 2021-09-03 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof, display panel and display device |
| CN113540125B (en) * | 2021-07-13 | 2024-01-05 | 武汉天马微电子有限公司 | Array substrate, display panel and display device |
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