CN106486540A - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN106486540A
CN106486540A CN201610137237.3A CN201610137237A CN106486540A CN 106486540 A CN106486540 A CN 106486540A CN 201610137237 A CN201610137237 A CN 201610137237A CN 106486540 A CN106486540 A CN 106486540A
Authority
CN
China
Prior art keywords
semiconductor regions
type
electrode
semiconductor
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
CN201610137237.3A
Other languages
English (en)
Inventor
高桥仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of CN106486540A publication Critical patent/CN106486540A/zh
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41708—Emitter or collector electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明提供能够抑制导通电压上升的半导体装置。半导体装置具有第1导电型的第1半导体区域、第2导电型的第2半导体区域、第2导电型的第3半导体区域、第1导电型的第4半导体区域、第2导电型的第5半导体区域、栅极电极及第1电极。第3半导体区域设于第1绝缘层与栅极绝缘层之间的一部分，与第1绝缘层相接，第2导电型的载流子浓度高于第2半导体区域。第4半导体区域具有第1部分。第1部分在从第1半导体区域朝向第2半导体区域的第1方向与第3半导体区域并排。第5半导体区域与栅极绝缘层相接。第5半导体区域在相对于第1方向垂直的第2方向与第1部分并排。

Description

半导体装置
[相关申请]
本申请享有以日本专利申请2015-167612号(申请日：2015年8月27日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本发明的实施方式涉及一种半导体装置。
背景技术
在IGBT(Insulated Gate Bipolar Transistor)等半导体装置中，有的装置为了抑制寄生双极晶体管的闭锁(latch up)而具有射极区域被减省的构造。
但，若减省射极区域，则通道密度下降，所以导通电压上升。
发明内容
本发明的实施方式提供一种能够抑制导通电压上升的半导体装置。
实施方式的半导体装置具有第1导电型的第1半导体区域、第2导电型的第2半导体区域、第2导电型的第3半导体区域、第1导电型的第4半导体区域、第2导电型的第5半导体区域、栅极电极、及第1电极。
所述第2半导体区域是设于所述第1半导体区域之上。
所述栅极电极具有隔着栅极绝缘层而被所述第2半导体区域包围的部分。
所述第1电极是与所述栅极电极相隔而设。所述第1电极具有隔着第1绝缘层而被所述第2半导体区域包围的部分。
所述第3半导体区域是设于所述第1绝缘层与所述栅极绝缘层之间的一部分。
所述第3半导体区域是与所述第1绝缘层相接。所述第3半导体区域的第2导电型的载流子浓度高于所述第2半导体区域的第2导电型的载流子浓度。
所述第4半导体区域具有第1部分。所述第1部分在从所述第1半导体区域朝向所述第2半导体区域的第1方向与所述第3半导体区域并排。所述第4半导体区域是设于所述第2半导体区域之上及所述第3半导体区域之上。所述第4半导体区域位于所述栅极电极与所述第1电极之间。
所述第5半导体区域选择性设于所述第4半导体区域之上。所述第5半导体区域是与所述栅极绝缘层相接。所述第5半导体区域在与所述第1方向垂直的第2方向与所述第1部分并排。
附图说明
图1是表示第1实施方式的半导体装置的一部分的立体剖视图。
图2(a)及(b)是表示第1实施方式的半导体装置的制造步骤的步骤剖视图。
图3(a)及(b)是表示第1实施方式的半导体装置的制造步骤的步骤剖视图。
图4是表示第2实施方式的半导体装置的一部分的立体剖视图。
图5是表示第2实施方式的变化例的半导体装置的一部分的立体剖视图。
具体实施方式
以下，一边参照附图一边对本发明的各实施方式进行说明。
另外，附图是示意图或概念图，各部分的厚度与宽度的关系、部分间的大小的比率等并非必须与实际相同。此外，即便在表示相同部分的情况下，也有根据附图不同而相互的尺寸、比率不同地表现的情况。
此外，本申请说明书及各图中，对与已说明的要素相同的要素附加相同符号且适当省略详细说明。
另外，在各实施方式的说明中，使用XYZ正交坐标系。将从p+型集极区域1朝向n-型半导体区域3的方向设为Z方向(第1方向)，将与Z方向垂直且相互正交的2方向设为X方向及Y方向。
在以下说明中，n+、n、n-及p+、p的表述是表示各导电型中的杂质浓度的相对高低。即，n+与n相比表示n型的杂质浓度相对较高，n-与n相比表示n型的杂质浓度相对较低。此外，p+与p相比表示p型的杂质浓度相对较高。
关于以下说明的各实施方式也可将各半导体区域的p型与n型反转而实施各实施方式。
(第1实施方式)
参照图1对第1实施方式的半导体装置的一例进行说明。
图1是表示第1实施方式的半导体装置100的一部分的立体剖视图。
半导体装置100为例如IGBT。
如图1所示，半导体装置100具有p+型(第1导电型)集极区域1(第1半导体区域)、n+型(第2导电型)半导体区域2、n-型半导体区域3(第2半导体区域)、p型基极区域4(第4半导体区域)、n+型射极区域5(第5半导体区域)、n型半导体区域6(第3半导体区域)、栅极电极10、栅极绝缘层11、第1电极20、第1绝缘层21、集极电极31、及射极电极32。
集极电极31是设于半导体装置100的下表面。
p+型集极区域1是设于集极电极31之上，与集极电极31电连接。
n+型半导体区域2是设于p+型集极区域1之上。
n-型半导体区域3是设于n+型半导体区域2之上。
p型基极区域4是设于n-型半导体区域3之上。
n+型射极区域5是选择性设于p型基极区域4之上。
栅极电极10及第1电极20是在n-型半导体区域3之上彼此相隔而设。栅极电极10及第1电极20是在X方向交替地设置。
栅极电极10是在X方向隔着栅极绝缘层11而与p型基极区域4面对面。第1电极20是在X方向隔着第1绝缘层21而与p型基极区域4面对面。此外，栅极电极10及第1电极20具有沿着X-Y面而被n-型半导体区域3包围的部分。
n型半导体区域6是设于栅极绝缘层11与第1绝缘层21之间的一部分。此外，n型半导体区域6在Z方向位于p型基极区域4与n-型半导体区域3之间，且与第1绝缘层21相接。n型半导体区域6也可与p型基极区域4相接，还可以在n型半导体区域6与p型基极区域4之间设置n-型半导体区域3的其他部分。
p型基极区域4具有在Z方向与n型半导体区域6并排的第1部分4a。第1部分4a与第1绝缘层21相接。此外，第1部分4a在X方向与n+型射极区域5并排。
换句话说，在栅极电极10与第1电极20之间，n+型射极区域5仅选择性地设于栅极电极10侧，n型半导体区域6仅选择性地设于第1电极20侧。n+型射极区域5与n型半导体区域6在Z方向不并排。
p型基极区域4、n+型射极区域5、n型半导体区域6、栅极电极10、及第1电极20于X方向设有多个，分别沿着Y方向延伸。
射极电极32设于半导体装置100的上表面，与p型基极区域4及n+型射极区域5电连接。此外，在栅极电极10与射极电极32之间设有绝缘层，将栅极电极10与射极电极32电分离。
第1电极20也可与射极电极32电连接。或者，第1电极20也可与栅极电极10电连接。
在集极电极31，对射极电极32施加有正电压的状态下，通过对栅极电极10施加阈值以上的电压，而IGBT变成导通状态。此时，在p型基极区域4的栅极绝缘层11附近的区域形成通道(反转层)。
接下来，使用图2及图3对第1实施方式的半导体装置100的制造方法的一例进行说明。
图2及图3是表示第1实施方式的半导体装置100的制造步骤的步骤剖视图。
首先，准备在n+型的半导体层2a之上形成有n-型的半导体层3a的半导体衬底。接着，如图2(a)所示，向n-型半导体层3a的表面选择性离子注入n型杂质，而形成n型半导体区域6。
接着，在n-型半导体层3a及n型半导体区域6之上形成n-型的半导体层3b(未图示)。通过向n-型半导体层3b离子注入p型的杂质，而形成p型基极区域4。然后，通过向p型基极区域4的表面选择性离子注入n型杂质，如图2(b)所示，形成n+型射极区域5。
接着，形成贯通p型基极区域4的多个沟槽。沟槽的一部分贯通n+型射极区域5，沟槽的其他部分贯通n型半导体区域6。接着，通过使该沟槽的内壁热氧化而形成绝缘层11a。在该绝缘层11a之上形成导电层，如图3(a)所示，对导电层进行回蚀。通过该步骤而在各个沟槽的内部形成栅极电极10或第1电极20。
接着，形成覆盖所述电极及p型基极区域4的绝缘层11b。通过使绝缘层11a及11b图案化，而形成栅极绝缘层11及第1绝缘层21。接着，在所述绝缘层之上形成金属层，通过使该金属层图案化而形成射极电极32。
接着，对n+型半导体层2a的背面进行研磨，直至n+型半导体层2a变成特定的厚度。然后，如图3(b)所示，向n+型半导体层2a的底面离子注入p型杂质，而形成p+型集极区域1。
之后，通过在p+型集极区域1之下形成集极电极31，而制作图1所示的半导体装置100。
此处，对本实施方式的作用及效果进行说明。
本实施方式的半导体装置100具有选择性设于栅极电极10侧的n+型射极区域5、及选择性设于第1电极20侧的n型半导体区域6。
n+型射极区域5是选择性设于栅极电极10侧，由此流过各个p型基极区域4的电流变小，寄生双极晶体管的闭锁得到抑制。
此时，由于n+型射极区域5并未设于第1电极20侧，所以通道密度下降，半导体装置的导通电压上升。
另一方面，通过设置n型半导体区域6，能够使n型半导体区域6蓄积空穴。此时，通过将n型半导体区域6选择性设于第1电极20侧，能够抑制通过通道流入n-型半导体区域3的电子、与蓄积于n型半导体区域6的空穴的再结合。通过抑制电子与空穴的再结合，能够提高n-型半导体区域3的载流子的密度，从而能够降低半导体装置的导通电压。
即，根据本实施方式，将n+型射极区域5选择性设于栅极电极10侧而产生的导通电压上升，能够通过将n型半导体区域6选择性设于第1电极20侧而得到抑制。
(第2实施方式)
参照图4对第2实施方式的半导体装置的一例进行说明。
图4是表示第2实施方式的半导体装置200的一部分的立体剖视图。
第2实施方式的半导体装置200与半导体装置100比较时，不同点为还具有p+型半导体区域7。此外，在半导体装置200中，第1电极20与栅极电极10电连接。
p+型半导体区域7在Z方向设于n型半导体区域6与n+型半导体区域2之间。n型半导体区域6位于p型基极区域4与p+型半导体区域7之间，且与所述半导体区域相接。
在半导体装置200中，通过对栅极电极10及第1电极20施加阈值以上的正电压，而MOSFET变成导通状态。其中，n+型射极区域5仅选择性设于栅极电极10侧。因此，若对第1电极20施加阈值以上的正电压便会在第1绝缘层21附近形成通道，但电子并不会流过该通道。
使MOSFET成为导通状态后，对栅极电极10及第1电极20施加负电压。通过该动作，在与第1电极20面对面的n型半导体区域6的第1绝缘层21附近的区域，形成与空穴相对的通道。蓄积于n-型半导体区域3的空穴通过该通道而被排出至射极电极32。
根据本实施方式，能够有效地进行使MOSFET导通时的载流子排出。因此，根据本实施方式，除了能获得第1实施方式所述的效果外，还能降低半导体装置的开关损耗。
此外，通过设置p+型半导体区域7，通过形成于n型半导体区域6的通道排出空穴时，能够减小排出路径对空穴的阻力。因此，能够更进一步降低半导体装置的开关损耗。
(变化例)
图5是表示第2实施方式的变化例的半导体装置210的一部分的立体剖视图。
在半导体装置200中，在X方向上2个第1部分4a与2个n+型射极区域5交替设置。相对于此，在变化例的半导体装置210中，在X方向上第1部分4a与n+型射极区域5交替设置。
在本变化例中，也通过对栅极电极10及第1电极20施加负电压，而在n型半导体区域6形成面向空穴的通道。因此，根据本变化例，与第2实施方式同样地，能够降低半导体装置的开关损耗。
关于以上所说明的各实施方式中的各半导体区域之间的杂质浓度的相对高低，例如能够使用SCM(扫描式静电电容显微镜)进行确认。另外，各半导体区域中的载流子浓度可视为与各半导体区域中活化的杂质浓度相等。因此，关于各半导体区域之间的载流子浓度的相对高低也能够使用SCM进行确认。
此外，关于各半导体区域中的杂质浓度，能够通过例如SIMS(二次离子质量分析法)进行测定。
以上，对本发明的若干实施方式进行了说明，但所述实施方式是作为示例而提示的，并不意图限定发明的范围。所述新颖的实施方式能以其他各种形态实施，且可在不脱离发明主旨的范围内进行各种省略、置换、变更。实施方式所包含的例如p+型集极区域1、n+型半导体区域2、n-型半导体区域3、p型基极区域4、n+型射极区域5、栅极电极10、栅极绝缘层11、第1电极20、第1绝缘层21、集极电极31、及射极电极32等各要素的具体构成，本领域技术人员可以根据周知技术适当地进行选择。所述实施方式或其变化包含于发明的范围及主旨，且包含于权力要求所记载的发明及其均等范围内。此外，所述各实施方式能够相互组合而实施。
[符号的说明]
100、200、210 半导体装置
1 p+型集极区域
2 n+型半导体区域
3 n-型半导体区域
4 p型基极区域
5 n+型射极区域
6 n型半导体区域
7 p+型半导体区域
10 栅极电极
11 栅极绝缘层
20 第1电极
21 第1绝缘层
31 集极电极
32 射极电极

Claims (5)

1.一种半导体装置，其特征在于具备：
第1导电型的第1半导体区域；
第2导电型的第2半导体区域，设于所述第1半导体区域之上；
栅极电极，具有隔着栅极绝缘层而被所述第2半导体区域包围的部分；
第1电极，具有隔着第1绝缘层而被所述第2半导体区域包围的部分，且与所述栅极电极相隔而设；
第2导电型的第3半导体区域，设于所述第1绝缘层与所述栅极绝缘层之间的一部分，与所述第1绝缘层相接，且第2导电型的载流子浓度高于所述第2半导体区域的第2导电型的载流子浓度；
第1导电型的第4半导体区域，在从所述第1半导体区域朝所述第2半导体区域的第1方向上具有与所述第3半导体区域并排的第1部分，设于所述第2半导体区域之上及所述第3半导体区域之上，且位于所述栅极电极与所述第1电极之间；以及
第2导电型的第5半导体区域，选择性地设于所述第4半导体区域之上，与所述栅极绝缘层相接，且在相对于所述第1方向垂直的第2方向上与所述第1部分并排。
2.根据权利要求1所述的半导体装置，其特征在于：所述第1电极与所述栅极电极电连接。
3.根据权利要求2所述的半导体装置，其特征在于：还具备在所述第1方向上设于所述第2半导体区域的一部分与所述第3半导体区域之间的第2导电型的第6半导体区域。
4.根据权利要求3所述的半导体装置，其特征在于：所述第1电极与所述第6半导体区域在所述第2方向上并排。
5.根据权利要求1至4中任一项所述的半导体装置，其特征在于：所述第3半导体区域与所述第4半导体区域在所述第1方向上不并排。
CN201610137237.3A 2015-08-27 2016-03-10 半导体装置 Withdrawn CN106486540A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015-167612 2015-08-27
JP2015167612A JP2017045874A (ja) 2015-08-27 2015-08-27 半導体装置

Publications (1)

Publication Number Publication Date
CN106486540A true CN106486540A (zh) 2017-03-08

Family

ID=57706049

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610137237.3A Withdrawn CN106486540A (zh) 2015-08-27 2016-03-10 半导体装置

Country Status (4)

Country Link
US (1) US9543422B1 (zh)
JP (1) JP2017045874A (zh)
CN (1) CN106486540A (zh)
TW (1) TW201709508A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110911471A (zh) * 2018-09-14 2020-03-24 株式会社东芝 半导体装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112018001179T5 (de) 2017-03-06 2019-12-24 Mitsubishi Electric Corporation Siliciumcarbid-halbleitereinheit, leistungswandler, verfahren zur herstellung einer siliciumcarbid-halbleitereinheit und verfahren zur herstellung eines leistungswandlers

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100039844A1 (en) * 2008-08-12 2010-02-18 Hitachi, Ltd. Semiconductor device and power converter using the same
CN104145342A (zh) * 2012-03-16 2014-11-12 富士电机株式会社 半导体装置
US20150091055A1 (en) * 2013-10-01 2015-04-02 Kabushiki Kaisha Toshiba Semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3119931B2 (ja) 1992-03-31 2000-12-25 株式会社東芝 サイリスタ
JP3927111B2 (ja) 2002-10-31 2007-06-06 株式会社東芝 電力用半導体装置
US8550968B2 (en) 2005-11-11 2013-10-08 Bridgestone Corporation Developing roller and imaging apparatus comprising the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100039844A1 (en) * 2008-08-12 2010-02-18 Hitachi, Ltd. Semiconductor device and power converter using the same
CN104145342A (zh) * 2012-03-16 2014-11-12 富士电机株式会社 半导体装置
US20150091055A1 (en) * 2013-10-01 2015-04-02 Kabushiki Kaisha Toshiba Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110911471A (zh) * 2018-09-14 2020-03-24 株式会社东芝 半导体装置

Also Published As

Publication number Publication date
JP2017045874A (ja) 2017-03-02
US9543422B1 (en) 2017-01-10
TW201709508A (zh) 2017-03-01

Similar Documents

Publication Publication Date Title
CN106537598B (zh) 半导体装置
CN105047712B (zh) 纵向型半导体装置及其制造方法
CN102468337B (zh) 半导体器件
CN104205334B (zh) 半导体装置
US9153676B2 (en) Insulated gate bipolar transistor
US9105680B2 (en) Insulated gate bipolar transistor
CN107293579B (zh) 一种具有低导通压降的超结igbt
US8975690B2 (en) Semiconductor device
CN104518015A (zh) 半导体装置
CN107833919A (zh) 半导体装置及其制造方法
CN106449750A (zh) 半导体装置
CN109216446A (zh) 半导体器件及其制造方法
CN107949916A (zh) 半导体元件
CN103477437B (zh) 功率半导体装置
CN108417614A (zh) 半导体装置
CN108321193A (zh) 一种沟槽栅电荷存储型igbt及其制作方法
CN109923663A (zh) 半导体装置
CN204102904U (zh) 半导体装置
CN110164971A (zh) 半导体装置
CN106206733A (zh) 半导体装置
CN110310990A (zh) 半导体装置
CN109216444A (zh) 半导体装置
CN107833918A (zh) 半导体装置
CN207637805U (zh) 竖直沟道半导体器件
CN104425581A (zh) 半导体装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WW01 Invention patent application withdrawn after publication

Application publication date: 20170308

WW01 Invention patent application withdrawn after publication