CN106449613A - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
- Publication number
- CN106449613A CN106449613A CN201610505374.8A CN201610505374A CN106449613A CN 106449613 A CN106449613 A CN 106449613A CN 201610505374 A CN201610505374 A CN 201610505374A CN 106449613 A CN106449613 A CN 106449613A
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- terminal
- semiconductor device
- semiconductor chip
- surface sections
- circuit board
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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Abstract
一种半导体装置,能抑制半导体装置的误操作,并能提高半导体装置的可靠性。在半导体装置(100)中,在层叠基板(140)的绝缘基板(141)上设置有电路板(142a、142b),并且在电路板(142a)上设有半导体芯片,在电路板(142b)上设有半导体芯片。此外,在半导体装置(100)中,将具有与电路板(142a)上的半导体芯片连接的端子部及与该端子部正交的平板部的跨接端子、和具有与电路板(142b)上的半导体芯片连接的端子部及与该端子部正交的平板部的跨接端子,以夹持树脂板的板部的状态配置于层叠基板(140),其中,所述树脂板具有对各半导体芯片的位置进行限定的定位部。
Description
技术领域
本发明涉及一种半导体装置。
背景技术
在功率半导体模块(半导体装置)中,包含IGBT(绝缘栅双极晶体管:InsulatedGate Bipolar Transistor)、MOSFET(金属氧化物半导体场效应晶体管:Metal OxideSemiconductor Field Effect Transistor)、FWD(续流二极管:Free Wheeling Diode)等半导体芯片,并被广泛用作电力转换装置。
在这种半导体装置中,在具有绝缘基板和由形成在该绝缘基板上的铜箔构成的电路图案的层叠基板中,在铜箔上配置有上述半导体芯片,并将上述层叠基板收纳在壳体内。另外,对于壳体内的层叠基板及半导体芯片进行配线,半导体芯片的电极间以及半导体芯片的电极与外部电极端子分别通过线材电连接,并用树脂将壳体内的上述结构封装(例如,参照专利文献1)。
现有技术文献
专利文献
专利文献1:日本专利特开2000-323646号公报
然而,在半导体装置中,根据与半导体芯片电连接的配线的不同,因在该配线中导通而产生的磁场等会对产品特性带来影响,有可能发生误操作。藉此,半导体装置有时可靠性会降低。
发明内容
根据本发明的一个方面,提供一种半导体装置,包括:层叠基板,所述层叠基板具有绝缘基板、第一电路板和第二电路板,其中,所述第一电路板配置于绝缘基板的正面,所述第二电路板与第一电路板并排地配置于正面;第一半导体芯片,所述第一半导体芯片配置于第一电路板;第二半导体芯片,所述第二半导体芯片配置于第二电路板;第一跨接端子,所述第一跨接端子具有第一端子部和第一板构件,其中,所述第一端子部与第一半导体芯片的主电极电连接;第二跨接端子,所述第二跨接端子具有第二端子部和第二板构件,其中,所述第二端子部与第二半导体芯片的主电极电连接;以及树脂板,所述树脂板具有第一定位部、第二定位部及板部,其中,所述第一定位部载置于第一电路板的正面并对第一半导体芯片在第一电路板上的位置进行限定,所述第二定位部载置于第二电路板的正面并对第二半导体芯片在第二电路板上的位置进行限定,所述板部在第一电路板与第二电路板之间被第一板构件和第二板构件夹持。
根据公开的技术,能抑制半导体装置的误操作,并能提高半导体装置的可靠性。
附图说明
图1是实施方式的半导体装置的立体图。
图2是表示实施方式的半导体装置的制造方法的流程图。
图3是在实施方式的半导体装置的绝缘基板上装载了部件的立体图。
图4是实施方式的半导体装置的跨接端子的立体图。
图5是实施方式的半导体装置的装载有树脂板的层叠基板的俯视图。
图6是表示实施方式的半导体装置的树脂板的图。
图7是表示实施方式的半导体装置的装载有树脂板的层叠基板的组装工序的图(之一)。
图8是表示实施方式的半导体装置的装载有树脂板的层叠基板的组装工序的图(之二)。
图9是表示实施方式的半导体装置的装载有树脂板的层叠基板的组装工序的图(之三)。
图10是实施方式的半导体装置的端子块的立体图。
图11是实施方式的半导体装置的印刷基板及端子块的立体图(之一)。
图12是实施方式的半导体装置的印刷基板及端子块的立体图(之二)。
图13是实施方式的半导体装置的壳体的俯视图。
图14是实施方式的半导体装置的壳体的后视图。
图15是实施方式的半导体装置的配线端子的立体图。
图16是实施方式的半导体装置的配线端子及层叠基板的剖视图。
图17是实施方式的半导体装置的主要部分放大图。
图18是实施方式的半导体装置的树脂块的立体图。
图19是表示形成在实施方式的半导体装置内的电路结构的电路图。
(符号说明)
100 半导体装置
110 壳体
112a、112b、112c 收纳部
113a、113b、113c P端子
114a、114b、114c N端子
115a U端子
115b V端子
115c W端子
116、117、118 配线端子
116a、117a、118a 底面部
116b、116c、117b、117c、118b 侧面部
119a、119b 印刷基板
120、130 端子块
121、131 控制端子
140 层叠基板
141 绝缘基板
142a、142b 电路板
143a、143b 导电端子
144a、144b、144c、146a、146b、146c 半导体芯片(半导体元件)
145a、145b 跨接端子
145aa、145ba 平板部
145ab、145bb 端子部
145ac、145bc 台阶部
150 树脂块
200、210 夹具
201、202、203、204、205、206 半导体芯片收纳部
207、208 导电端子收纳部
210a 端子部收纳部
具体实施方式
以下,参照附图,对实施方式进行说明。
[实施方式]
首先,使用图1,对实施方式的半导体装置进行说明。
图1是实施方式的半导体装置的立体图。
半导体装置100包括壳体110和层叠基板140,该层叠基板140分别收纳在壳体110的收纳部112a、112b、112c中。
半导体装置100的正极与P端子(第二外部端子)113a、113b、113c连接,负极与N端子(第一外部端子)114a、114b、114c连接,对各控制端子121、131施加控制信号,以从U端子(第三外部端子)115a、V端子(第三外部端子)115b、W端子115c(第三外部端子)获得与控制信号相应的输出。
另外,关于构成这种半导体装置100的壳体110和收纳在壳体110中的层叠基板140的细节,将在后文进行描述。
在此,使用图2,对半导体装置100的制造方法进行说明。
图2是表示实施方式的半导体装置的制造方法的流程图。
[步骤S11]准备印刷基板119a、119b及端子块120、130(步骤S11a)。此外,准备层叠基板140(步骤S11b)。在步骤S11a中,端子块120、130的控制端子121、131分别被压入印刷基板119a、119b,将印刷基板119a、119b保持于端子块120、130的下表面侧。
在此,使用图3,对层叠基板140进行说明。
图3是在实施方式的半导体装置的绝缘基板上装载了部件的立体图。
层叠基板140在绝缘基板141的下表面配置有由铜等构成的散热板(未图示),在绝缘基板141的上表面配置有由铜箔等构成的电路板142a、142b。
在电路板(第一电路板)142a上,例如由铜构成的导电端子143a配置于图中下侧,半导体芯片(第一半导体芯片)144a、144b、144c(的集电器电极侧)通过锡焊配置成一列。另外,在配置成一列的半导体芯片144a、144b、144c的各发射器电极上,通过锡焊配置有跨接端子(第一跨接端子)145a,以使半导体芯片144a、144b、144c的各发射器电极电连接。
在电路板(第二电路板)142b上,例如由铜构成的导电端子143b配置于图中上侧、即与导电端子143a相反的一侧,半导体芯片(第二半导体芯片)146a、146b、146c(的集电器电极侧)通过锡焊配置成一列。另外,在配置成一列的半导体芯片146a、146b、146c的各发射器电极上,通过锡焊配置有跨接端子(第二跨接端子)145b,以使半导体芯片146a、146b、146c的各发射器电极电连接。
在图示的例子中,半导体芯片144a、144b、144c被电气地并联连接,此外,半导体芯片146a、146b、146c被电气地并联连接。半导体芯片的数量能根据半导体装置的容量增加减少。
在此,使用图3、图4,对跨接端子145a、145b进行说明。图4是实施方式的半导体装置的跨接端子的立体图。
跨接端子145a(145b)具有端子部145ab(145bb)、平板部(板构件)145aa(145ba)、将平板部145aa(145ba)与端子部145ab(145bb)连接的台阶部145ac(145bc)。
端子部145ab(145bb)可根据连接的半导体芯片的个数来进行准备,通过锡焊等的接合件与各半导体芯片接合,并与各半导体芯片电气、机械地连接。端子部145ab(145bb)具有从图中上表面贯穿到下表面侧(连接面)的通孔145ad(145bd)。在半导体装置100中,通过在端子部145ab(145bb)上设置通孔145ad(145bd),从而在用树脂进行封装时,能使树脂进入通孔145ad(145bd)来提高树脂的密接性,使树脂难以剥离。
平板部145aa(145ba)通过台阶部145ac(145bc)而与各端子部145ab(145bb)连接,其中,上述各端子部145ab(145bb)与各半导体芯片电连接。平板部145aa(145ba)的厚度例如为1mm~1.5mm。在图示的例子中,平板部145aa(145ba)的正面与端子部145ab(145bb)的正面大致正交,台阶部145ac(145bc)具有与上述两个正面大致平行的面,跨接端子145a(145b)的一个截面为锯齿形状。
台阶部145ac(145bc)从下侧对后述的配线端子116(117)进行支撑。
如图3所示,跨接端子145a的平板部145aa与跨接端子145b的平板部145ba平行地相向地配置。此外,如图3所示,跨接端子145a沿俯视观察突出到比跨接端子145b更位于图中上侧的位置。此外,如图3所示,跨接端子145b沿俯视观察突出到比跨接端子145a更位于图中下侧的位置。平板部145aa和平板部145ba夹着树脂板147错开地配置。平板部145aa的一端部配置在比平板部145ba的一端部更靠层叠基板140的一端部附近,平板部145ba的另一端部配置在比平板部145aa的另一端部更靠与层叠基板140的一端部相反一侧的另一端部附近。
在跨接端子145a与跨接端子145b之间配置有树脂板147,跨接端子145a和跨接端子145b被支承于上述树脂板147。
在此,使用图3、图5、图6,对树脂板147进行说明。图5是实施方式的半导体装置的装载有树脂板的层叠基板的俯视图,其是从图3中去除了跨接端子145a、145b后的俯视图。图6是表示实施方式的半导体装置的树脂板的图。图6(a)是图3的点划线Y-Y处的树脂板147及平板部145aa、145ba的剖视图的示意图。图6(b)是去除平板部145aa、145ba后的图6(a)的立体图。
树脂板147具有板部147a和定位部147b。如图3所示,板部147a配置在平板部145aa与平板部145ba之间(电路板142b与电路板142a之间)。此外,如图3所示,板部147a沿俯视观察突出到比平板部145ba更靠图中上侧的位置(例如,1mm以上),并突出到比平板部145aa更靠图中下侧的位置(例如1mm以上)。此外,如图6(a)所示,板部147a剖视观察时突出到比平板部145aa、145ba更靠图中上下侧的位置(例如1mm以上)。平板部145aa、板部147a及平板部145ba各自的一端部按顺序错开配置,板部147a的一端部的相邻的两个侧面露出到平板部145aa、145ba之间。平板部145aa、板部147a及平板部145ba的一端部相反一侧的各自的另一端部也同样地按顺序错开配置。
也就是说,在平板部145aa与平板部145ba平行地相向的部分(重合的区域)处,设置有板部147a。
通过将这样的板部147a配置在平板部145aa与平板部145ba之间,从而半导体装置100能确保跨接端子145a与跨接端子145b的爬电距离及空间距离。即,半导体装置100能确保跨接端子145a与跨接端子145b的绝缘性。
定位部147b分别设置在板部147a的相对的面、即电路板142a一侧及电路板142b一侧,并与电路板142a、142b紧密接触。如图5所示,定位部147b俯视观察时为凸形或T字形(台阶形状),并位于半导体芯片144a、144b之间、半导体芯片144b、144c之间、半导体芯片146a、146b之间及半导体芯片146b、146c之间。定位部147b配置成使凸形的台阶部分位于与四边形的各半导体芯片的角部相对应的部分处,用台阶部分的两条边对各半导体芯片的位置(两条边的位置)进行限定(固定)。定位部147b在电路板142a一侧和电路板142b一侧设置于错开的位置,藉此,能使树脂板147不易倾倒。
此外,如图6(a)、图6(b)所示,定位部147b具有供跨接端子145a、145b***的狭缝(***部)147c。跨接端子145a的没有设置台阶部145ac的部分的平板部145aa被***到狭缝147c中。此外,跨接端子145b的没有设置台阶部145bc的部分的平板部145ba被***到狭缝147c中。
这样,通过将跨接端子145a、145b***狭缝147c中,从而在组装时,树脂板147能对跨接端子145a、145b进行支承,以使跨接端子145a、145b不会倾倒。
此外,狭缝147c为能使所***的平板部145aa(145ba)沿上下滑动的大小。
如后所述,跨接端子145a以将平板部145aa***狭缝147c的状态配置于层叠基板140,但由于能使平板部145aa在狭缝147c内滑动,因此,能在保持***的状态下将端子部145ab引导到适当的位置处。此外,跨接端子145b以将平板部145ba***狭缝147c的状态配置于层叠基板140,但由于能使平板部145ba在狭缝147c内滑动,因此,能在保持***的状态下将端子部145bb引导到适当的位置处。也就是说,由于平板部145aa(145ba)在狭缝147c内滑动,因此,能在使树脂板147的定位部147b与电路板142a、142b紧密接触的状态下,使端子部145ab(145bb)移动到适当的位置处。
另外,也可以在板部147a上设置对跨接端子145a、145b进行保持的保持机构,以代替定位部147b的狭缝147c。
另外,定位部147b的形状是一例,不局限于凸形。定位部147b的形状只要是能限定半导体芯片的位置的形状即可。此外,树脂板147也可以不设置定位部147b,而是进一步增厚图5所示的板部147a的厚度,来使板部147a延伸到电路板142a、142b而与电路板142a、142b紧密接触,用板部147a对各半导体芯片的位置(一条边的位置)进行限定。能使用液晶高分子聚合物(LCP)、聚苯硫醚(PPS)等与锡焊相对应的树脂,来作为树脂板147的材料。
使用IGBT、MOSFET或FWD等作为半导体芯片144a、144b、144c、146a、146b、146c。图3示出了使用RC-IGBT(逆导通IGBT:Reverse Conducting IGBT)作为半导体芯片144a等的例子。除了硅酮之外,能使用碳化硅及氮化镓,来作为半导体芯片的基板。半导体芯片144a等各自除了具有主电极(发射器电极及集电器电极)之外,还包括与门端子、感测端子及芯片温度测定用端子连接的多个控制电极144ac、144bc、144cc、146ac、146bc、146cc。
在此,使用图7~图9,对装载有树脂板的层叠基板的组装工序进行说明。图7~图9是表示实施方式的半导体装置的装载有树脂板的层叠基板的组装工序的图。
首先,如图7(a)所示,准备层叠基板140,该层叠基板140在绝缘基板141的下表面配置有由铜等构成的散热板(未图示),在绝缘基板141的上表面(正面)配置有由铜箔等构成的电路板142a、142b。
接着,如图7(b)所示,将夹具200配置于层叠基板140,其中,上述夹具用于对配置在层叠基板140上的电子元器件(导电端子、半导体芯片)进行定位。在夹具200的供半导体芯片配置的位置处设置有半导体芯片收纳部201、202、203、204、205、206,该半导体芯片收纳部201、202、203、204、205、206使层叠基板140(电路板142a、142b)露出。此外,在夹具200的供导电端子配置的位置处设置有导电端子收纳部207、208,该导电端子收纳部207、208使层叠基板140(电路板142a、142b)露出。
接着,如图8、图9所示,将半导体芯片144a~144c、146a~146c、跨接端子145a、145b、树脂板147配置在电路板142a、142b上,利用树脂板147对半导体芯片144a~144c、146a~146c进行定位,同时通过锡焊连接将电路板142a、142b、半导体芯片144a~144c、146a~146c及跨接端子145a、145b之间接合。
接着,如图8(a)所示,通过锡焊将电子元器件配置于层叠基板140。将锡焊材料和半导体芯片144a、144b、144c、146a、146b、146c依次配置于半导体芯片收纳部201、202、203、204、205、206内的电路板142a、142b上。此外,将锡焊材料和导电端子143a、143b依次配置于导电端子收纳部207、208内的电路板142a、142b上。
接着,如图8(b)所示,将用于对端子部145ab、145bb进行定位的夹具210配置在已配置于半导体芯片收纳部201、202、203、204、205、206的各半导体芯片上方。在夹具210的供端子部145ab、145bb配置的位置处设置有端子部收纳部210a,该端子部收纳部210a使各半导体芯片的主电极(发射器电极)露出。
接着,如图9所示,使已将跨接端子145a、145b的平板部145aa、145ba***到狭缝147c中的树脂板147配置在层叠基板140上。将锡焊材料配置在端子部145ab、145bb与各半导体芯片的主电极之间。
将这样组装后的部件及夹具投入炉中,将锡焊材料加热、熔解、冷却来将各构件锡焊连接。这样,半导体芯片144a、144b、144c、146a、146b、146c的背面(集电器电极)通过锡焊连接而与电路板142a、142b接合,导电端子143a、143b的背面通过锡焊连接而与电路板142a、142b接合,此外,端子部145ab、145bb通过锡焊连接而与各半导体芯片的正面(发射器电极)接合,锡焊材料是不包含铅的板焊料或糊剂焊料。
另外,在上述例子中,在图9的状态之前,在组装好部件的状态下一并进行了锡焊连接,但也可以分多次进行锡焊连接。例如,也可以如图8(a)所示,在将电子元器件配置于层叠基板140后的阶段,通过锡焊连接将半导体芯片144a~144c、146a~146c的背面及导电端子143a、143b的背面与电路板142a、142b接合,接着,如图9所示,在将树脂板147配置于层叠基板140上的阶段,通过锡焊连接将半导体芯片144a~144c、146a~146c的正面与端子部145ab、145bb接合。
树脂板147以使定位部147b与电路板142a、142b紧密接触,且从内侧(中央侧)对半导体芯片144a、144b、144c、146a、146b、146c的位置进行限定的方式配置在层叠基板140上。
也就是说,在树脂板147配置于层叠基板140上的状态下,半导体芯片144a、144b、144c、146a、146b、146c的位置被夹具200从外侧限定,被定位部147b从内侧限定。
在这种状态下,使***到狭缝147c中的平板部145aa、145ba在狭缝147c内滑动,来使端子部145ab、145bb移动到夹具210的端子部收纳部210a的适当位置。接着,将端子部145ab、145bb的背面与各半导体芯片锡焊连接,以将端子部145ab、145bb与各半导体芯片接合。然后,去除夹具200、210。藉此,能获得图3所示这样的层叠基板140的结构。
这样,由于在利用夹具200从外侧并利用定位部147b从内侧对各半导体芯片的位置进行限定的状态下,将端子部145ab、145bb接合,因此,能抑制因接合时的热等而使各半导体芯片移动离开适当的位置。
此外,通过使用夹具200仅对半导体芯片的外侧进行定位,而利用为了确保跨接端子145a、145b的绝缘性而采用的树脂板147来进行内侧的定位,从而在组装后能容易地将夹具200从层叠基板140去除。
接着,使用图10~图12,对端子块120、130进行说明。
图10是实施方式的半导体装置的端子块的立体图。
此外,图11和图12是实施方式的半导体装置的印刷基板及端子块的立体图。另外,在图11和图12中,示出了将端子块120、130配置于印刷基板119a的情况。
如图10所示,端子块120、130是在将控制端子(外部连接端子)121、131一体成型后通过树脂构成的,呈大致长方体状。在端子块120、130的下表面(第二面)一侧,分别形成有由两个突起规定的间隙122、132。端子块120、130的下表面分别是用于设置到印刷基板119a的面。另外,间隙122、132从端子块120、130的图中正面侧朝背面侧贯穿。此外,在端子块120、130的彼此相对的面一侧,分别形成有台阶部123、133。
这种端子块120、130对多个控制端子121、131进行保持。控制端子121、131形成为两端部比主体部厚。端子块120、130对这种控制端子121、131的主体部进行保持,形成为比主体部厚的两端部分别突出于端子块120、130的图中上表面(第一面)及下表面(第二面)。如后所述,突出于端子块120、130的图中下表面一侧的控制端子121、131的下端部被压入(按压配合)到设于印刷基板119a的通孔中。另外,在图10中,控制端子121、131在端子块120、130上形成两列。藉此,与将控制端子121、131形成一列的情况相比,能增加保持于端子块120、130的控制端子121、131的根数。此外,端子块120、130不局限于将控制端子121、131形成为两列,通过形成为三列以上,能进一步增加所保持的控制端子121、131的根数。端子块120、130配置于印刷基板119a的一端部。
另外,形成壳体110所用的印刷基板(电路配线基板)119a包括由导电材料构成的配线层和由耐热性高的材料构成的基板,与配线层电连接的电极119a1在正面上排列多列。配线层的结构也可以是单层、层叠在两个面上的结构和多层结构中的任一个。此外,印刷基板119a形成有从上表面(第一主表面)向下表面(第二主表面)贯穿的多个贯穿孔119a2。如后所述,当将印刷基板119a与壳体110一体成型时,通过使壳体110的树脂进入上述贯穿孔119a2,来使印刷基板119a容易地固接到壳体110上。较为理想的是,多个贯穿孔119a2配置成将排齐的多个电极119a1夹在中间。通过用贯穿孔119a2内的树脂将电极119a1的周围固定,从而能提高后续步骤中的线材148的连接的可靠性。
此外,也可以预先在印刷基板119a的背面形成由铜制成的图案,并在该图案的表面通过黑化处理刻意地设置凹凸。藉此,当将印刷基板119a一体成型于壳体110时,通过使背面的凹凸与壳体110贴合,而使印刷基板119a容易地固接于壳体110。下表面侧的配线层的整体模(日文:ベタパターン)也能被用作保护罩。较为理想的是,在印刷基板119a的下表面不留有抗蚀剂等的残渣。
从端子块120、130的下表面突出的控制端子121、131的下端部通过压入(按压配合)与这种印刷基板119a连接,以供端子块120、130配置。藉此,印刷基板119a与控制端子121、131电连接。如图12所示,也可以使控制端子121、131的端部在印刷基板119a、119b的下表面侧露出或突出。
另外,在控制端子121、131的下端部与主体部具有相同厚度的情况下,也可以不使用压入而是通过锡焊来与印刷基板119a连接。在这种情况下,在印刷基板119a的背面侧将(从印刷基板119a的正面侧)贯穿印刷基板119a的控制端子121、131的下端部锡焊连接。但是,锡焊会随着温度而熔融,因而存在熔融的锡焊进入树脂这样的情况。为了防止这种熔融后的锡焊流入树脂,也可以使用环氧树脂将印刷基板119a的背面侧的控制端子121、131的锡焊连接部覆盖,并进行使该环氧树脂固化的处理。因而,当将控制端子121、131安装于印刷基板119a时,进行压入比使用锡焊更为理想。
此外,在印刷基板119a上也可以设置控制电路,并装载与控制端子121、131电连接的电子元器件等。另外,后述的印刷基板119b也具有与印刷基板119a相同的结构,能进行同样地处理。
准备好这样的层叠基板140、印刷基板119a、119b以及端子块120、130。
[步骤S12]通过将配置有端子块120、130的印刷基板119a、119b、配线端子(第三配线端子)118、P端子113a、113b、113c、N端子114a、114b、114c、U端子115a、V端子115b、W端子115c等一体成型,并使用树脂来形成壳体110。
使用图13及图14,对这样形成的壳体110进行说明。
图13是实施方式的半导体装置的壳体的俯视图,图14是实施方式的半导体装置的壳体的后视图。
壳体110例如通过注塑成型并使用树脂形成,其具有在中央部形成有凹部的框形状。在中央部的凹部内形成有收纳部112a、112b、112c,在该收纳部112a、112b、112c中分别用于收纳上述层叠基板140。在收纳部112a的周缘部(沿着壳体110的短边方向)配置有印刷基板119a、119b。在收纳部112b的周缘部(沿着壳体110的短边方向)配置有一对印刷基板119a。在收纳部112c的周缘部(沿着壳体110的短边方向)配置有印刷基板119a、119b。此外,各印刷基板119a、119b通过一体成型配置于壳体110。
对于这样的壳体110的收纳部112a,在壳体110的长边方向的一边侧(图中下侧)设置有P端子113a和N端子114a,在另一边侧(图中上侧)设置有U端子115a。同样地,对于收纳部112b,在壳体110的长边方向的一边侧(图中下侧)设置有P端子113b和N端子114b,在另一边侧(图中上侧)设置有V端子115b。此外,对于收纳部112c,在壳体110的长边方向的一边侧(图中下侧)设置有P端子113c和N端子114c,在另一边侧(图中上侧)设置有W端子115c。
在各收纳部112a、112b、112c上,配置有配线端子118,该配线端子118与P端子113a、113b、113c电连接,并从P端子113a、113b、113c突出。另外,配线端子118在与后述配线端子(第一配线端子)117相对的边上具有从底面部118a立起(与底面部118a正交)的侧面部118b。侧面部118b的厚度例如为1.0mm~1.5mm。
此外,在收纳部112a的U端子115a侧的印刷基板119a、119b上,分别配置有端子块120、130,控制端子121、131与印刷基板119a、119b电连接。另外,端子块120、130分别配置在壳体110的长边方向的边的U端子115a、V端子115b、W端子115c附近。
端子块120、130通过一体成型而与壳体110的树脂一体化。在二次成型时,通过使端子块120、130的上表面、下表面或位于上表面与下表面间的侧面(第三面)与加热后的树脂熔接,来使端子块120、130与壳体110接合。作为树脂,能使用例如聚苯硫醚(PPS)等热塑性树脂。
[步骤S13]将在步骤S11b中准备好的层叠基板140收纳于在步骤S12中形成的壳体110。在收纳时,层叠基板140的导电端子143a与壳体110的配线端子118的底面部118a(的背面侧)接合。
具体来说,将在图3中所说明的层叠基板140设置于铜板或冷却器。以使设置于铜板或冷却器的层叠基板140分别收纳于在图13、图14中说明的壳体110的收纳部112a、112b、112c的方式对壳体110进行接合。
[步骤S14]使用线材148将半导体芯片144a、144b、144c的门电极等控制电极与印刷基板119a连接,以用线材148将半导体芯片146a、146b、146c的门电极等控制电极与印刷基板119b连接。
另外,最好将半导体芯片144a、144b、144c配置成使各控制电极沿着印刷基板119a排齐。对于半导体芯片146a、146b、146c亦是如此。通过这种配置,能容易地实现利用线材148进行的连接。若使用RC-IGBT作为半导体芯片144a等,则能如图3所示使控制电极的排齐变得容易。
[步骤S15]如图1所示,通过焊接,将配线端子(第二配线端子)116与壳体110的U端子115a、V端子115b及W端子115c的一端、层叠基板140的导电端子143b、跨接端子145a(的平板部145aa)分别接合。藉此,使配线端子116、U端子115a、V端子115b、W端子115c、层叠基板140的导电端子143b、跨接端子145a电连接。
如图1所示,通过焊接,将配线端子117与壳体110的N端子114a、114b、114c的一端、跨接端子145b(的平板部145ba)分别接合。藉此,使配线端子117与N端子114a、114b、114c、跨接端子145b电连接。
藉此,能获得图1所示这样的半导体装置100的结构。
在此,使用图1、图15~图17,对配线端子116、117进行说明。图15是实施方式的半导体装置的配线端子的立体图。图16是实施方式的半导体装置的配线端子及层叠基板的剖视图,其是沿图1的点划线X-X的剖视图。图17是实施方式的半导体装置的主要部分放大图。
配线端子116具有底面部116a、侧面部116b、侧面部116c。如图1、图17所示,底面部116a在一端的背面侧(图中下表面)与U端子115a、V端子115b、W端子115c的一端和导电端子143b接合,另一端与印刷基板119a、119b平行地延伸到配线端子118的前方。
此外,如图16所示,底面部116a的下侧(图中下表面)支承于跨接端子145a的台阶部145ac。此外,底面部116a从台阶部145ac突出,在底面部116a的突出部分与端子部145ab之间设置有间隙。此外,在底面部116的突出部分处,形成有图15所示这样的从图中上表面贯穿到下表面一侧的通孔116d。通过这样在底面部116a的突出部分上设置通孔116d,半导体100在用树脂进行封装时,能使树脂进入通孔116d来提高树脂的密接性,并能使树脂难以剥离。
如图1、图16、图17所示,侧面部116b设置成在底面部116a的与配线端子117相对的边上从底面部116a呈L字形立起(与底面部116a正交)的面。此外,如图1、图16、图17所示,侧面部116b与后述的侧面部117b平行配置,并与跨接端子145a(的平板部145aa)接合,且与跨接端子145a电连接。
例如,侧面部116b在平板部145aa的上端侧(与层叠基板140相对的一侧)与平板部145aa接合。这样,通过将侧面部116b在平板部145aa的上端侧接合,能使接合部分远离各半导体芯片。藉此,半导体装置100能减弱因配线端子116的膨胀等而传递到各半导体芯片及层叠基板140的应力,并能抑制各半导体芯片及层叠基板140的破裂及破损,能提高半导体装置100的可靠性。
此外,如图1、图17所示,侧面部116c设置成在底面部116a的与配线端子117相对的边上从底面部116a呈L字形立起(与底面部116a正交)的面,并与配线端子117的侧面部117c平行地配置。侧面部116b、116c的厚度例如为1.0mm~1.5mm。
配线端子117具有底面部117a、侧面部117b、侧面部117c。如图1、图17所示,底面部117a在一端的背面侧(图中下表面)与N端子114a、114b、114c的一端接合,另一端与印刷基板119a、119b平行地延伸到配线端子116的前方。
此外,如图16所示,底面部117a的下侧(图中下表面)支承于跨接端子145b的台阶部145bc。此外,底面部117a从台阶部145ac突出,在底面部117a的突出部分与端子部145bb之间设置有间隙。另外,在底面部117的突出部分处,形成有图15所示这样的从图中上表面贯穿到下表面一侧的通孔117d。通过这样在底面部117a的突出部分上设置通孔117d,半导体100在用树脂进行封装时,能使树脂进入通孔117d来提高树脂的密接性,并能使树脂难以剥离。
如图1、图16、图17所示,侧面部117b设置成在底面部117a的与配线端子116及配线端子118相对的边上从底面部117a呈L字形立起(与底面部117a正交)的面。此外,如图1、图16、图17所示,侧面部117b与后述的侧面部116b、118b平行配置,并与跨接端子145b(的平板部145ba)接合,且与跨接端子145b电连接。
例如,侧面部117b在平板部145ba的上端侧(与层叠基板140相对的一侧)与平板部145ba接合。这样,通过将侧面部117b在平板部145ba的上端侧接合,能使接合部分远离各半导体芯片。藉此,半导体装置100能减弱因配线端子117的膨胀等而传递到各半导体芯片及层叠基板140的应力,并能抑制各半导体芯片及层叠基板140的破裂及破损,能提高半导体装置100的可靠性。
此外,如图1、图17所示,侧面部117c设置成在底面部117a的与配线端子116相对的边上从底面部117a呈L字形立起(与底面部117a正交)的面,并与配线端子116的侧面部116c平行地配置。侧面部117b、117c的厚度例如为1.0mm~1.5mm。
这样,侧面部116b和侧面部117b夹着平行配置的平板部145aa、板部147a、平板部145ba而平行地配置。
即,在半导体装置100中,电连接的侧面部117b及平板部145ba与电连接的侧面部116b及平板部145aa夹着板部147a平行地配置。此外,在半导体装置100中,侧面部116c与侧面部117c平行地配置。此外,在半导体装置100中,侧面部117b与侧面部118b平行地配置。
[步骤S16]将树脂块嵌入壳体110的凹部内。在此,使用图18,对树脂块进行说明。图18是实施方式的半导体装置的树脂块的立体图。
树脂块150由树脂形成,具有以嵌入半导体装置100中央部的凹部中的方式例如由多个框组装成框形的结构。此外,由于包括这样的树脂块150,因此,在半导体装置100中,能提高刚性率,并能使对于由来自外部的冲击等所引起的弯曲、扭绞而产生的变形减小。因而,能防止对半导体装置100内部的半导体芯片144a、144b、144c及半导体芯片146a、146b、146c带来的冲击、损伤等。
[步骤S17]使用封装树脂将壳体110的凹部内的层叠基板140、印刷基板119a、119b、配线端子116、117、118、线材148等进行封装,并使封装树脂固化。藉此,完成半导体装置100。作为封装树脂,例如能使用环氧树脂。
接着,使用图1、图3、图19,对由这样的半导体装置100构成的电路结构进行说明。图19是表示形成在实施方式的半导体装置内的电路结构的电路图。
在半导体100的收纳部112a的层叠基板140(图1、图3)中,通过配线端子118与P端子113a电连接的导电端子143a经由电路板142a,而与半导体芯片144a、144b、144c的集电器电极电连接。在与半导体芯片144a、144b、144c的发射器电极电连接的跨接端子145a上,电气地布置有配线端子116,配线端子116与U端子115a电连接。
导电端子143b被电连接到与U端子115a电连接的配线端子116,经由电路板142b而与半导体芯片146a、146b、146c的集电器电极电连接。在与半导体芯片146a、146b、146c的发射器电极电连接的跨接端子145b上,电气地布置有配线端子117,配线端子117与N端子114a电连接。
此外,在半导体100的收纳部112b的层叠基板140(图1和图3)中,通过配线端子118与P端子113b电连接的导电端子143a经由电路板142a,而与半导体芯片144a、144b、144c的集电器电极电连接。在与半导体芯片144a、144b、144c的发射器电极电连接的跨接端子145a上,电气地布置有配线端子116,配线端子116与V端子115b电连接。
导电端子143b被电连接到与V端子115b电连接的配线端子116,经由电路板142b而与半导体芯片146a、146b、146c的集电器电极电连接。在与半导体芯片146a、146b、146c的发射器电极电连接的跨接端子145b上,电气地布置有配线端子117,配线端子117与N端子114b电连接。
此外,在半导体装置100的收纳部112c的层叠基板140(图1、图3)中,通过配线端子118与P端子113c电连接的导电端子143a经由电路板142a,而与半导体芯片144a、144b、144c的集电器电极电连接。在与半导体芯片144a、144b、144c的发射器电极电连接的跨接端子145a上,电气地布置有配线端子116,配线端子116与W端子115c电连接。
导电端子143b被电连接到与W端子115c电连接的配线端子116,经由电路板142b而与半导体芯片146a、146b、146c的集电器电极电连接。在与半导体芯片146a、146b、146c的发射器电极电连接的跨接端子145b上,电气地布置有配线端子117,配线端子117与N端子114c电连接。
通过这种结构,在半导体装置100的内部构成图19所示的电路。
因而,在电源的正极与P端子113a连接、负极与N端子114a连接的状态下,控制信号经由控制端子121、131及印刷基板119a、119b而与外部电路之间输入输出。根据上述控制信号,经由印刷基板119a、119b及线材148,将控制信号输入至半导体芯片144a、144b、144c及半导体芯片146a、146b、146c的门电极,并根据控制信号从U端子115a输出。
此外,在正极与P端子113b连接、负极与N端子114b连接的状态下,控制信号经由控制端子121、131及印刷基板119a、119b输入输出。根据上述控制信号,经由印刷基板119a、119b及线材148,将控制信号输入至半导体芯片144a、144b、144c及半导体芯片146a、146b、146c的门电极,并根据控制信号从V端子115b输出。
此外,在正极与P端子113c连接、负极与N端子114c连接的状态下,控制信号经由控制端子121、131及印刷基板119a、119b输入输出。根据上述控制信号,经由印刷基板119a、119b及线材148,将控制信号输入至半导体芯片144a、144b、144c及半导体芯片146a、146b、146c的门电极,并根据控制信号从W端子115c输出。
然而,如上所述,在半导体装置100中,电连接的侧面部117b及平板部145ba与电连接的侧面部116b及平板部145aa夹着板部147a平行地相对配置。此外,在半导体装置100中,侧面部116c与侧面部117c平行地相对配置。此外,在半导体装置100中,侧面部117b与侧面部118b平行地相对配置。能增加配置于P端子(上臂)侧的跨接端子145a及配线端子116、118与配置于N端子(下臂)侧的跨接端子145b及配线端子117的相对的面积,并能降低主电路的阻抗。
详细来说,根据上述电路结构及半导体装置100的结构,由在平行配置的侧面部117b及平板部145ba中流动的电流而产生的磁场与由在侧面部116b及平板部145aa中流动的电流而产生的磁场相互抵消。
此外,由在平行配置的侧面部117c中流动的电流而产生的磁场与由在侧面部116b中流动的电流而产生的磁场相互抵消。
此外,由在平行配置的侧面部117b中流动的电流而产生的磁场与由在侧面部118b中流动的电流而产生的磁场相互抵消。
即,在半导体装置100中,能减弱磁场,并能抑制因磁场而引发的半导体装置100的误操作。藉此,在半导体装置100中,能提高半导体装置100的可靠性。
另外,由于利用被跨接端子145a、145b夹持的树脂板147对各半导体芯片进行定位,因此,能使将各半导体芯片及跨接端子145a、145b装载于层叠基板140的组装工序变得容易,并能实现半导体装置100的小型化。
另外,也能将配线端子116、117与收纳部112a、112b、112c对应地一体成型于树脂块150的背面侧。通过这样将树脂块150与配线端子116、117一体成型,从而能一并配置配线端子116、117,在半导体装置100中,能使半导体装置100的组装性提高。在这种情况下,最好用树脂形成收纳部单元的树脂块,并将一组配线端子116、117一体成型于各收纳部单元的树脂块的背面。通过这样将收纳部单元的树脂块与配线端子116、117一体成型,从而能将配线端子116、117引导到跨接端子145a、145b的适当的位置处,并能将配线端子116、117良好地接合。
此外,配线端子116、117也能与壳体110一体成型。
此外,半导体装置100也可以构成为包括一组层叠基板140、半导体芯片144a~144c、146a~146c、跨接端子145a、145b、树脂板147、输入端子(P端子113a、N端子114a)及输出端子(U端子115a)的一相的功率半导体模块。
Claims (10)
1.一种半导体装置,其特征在于,包括:
层叠基板,所述层叠基板具有绝缘基板、第一电路板和第二电路板,其中,所述第一电路板配置于所述绝缘基板的正面,所述第二电路板与所述第一电路板并排地配置于所述正面;
第一半导体芯片,所述第一半导体芯片配置于所述第一电路板;
第二半导体芯片,所述第二半导体芯片配置于所述第二电路板;
第一跨接端子,所述第一跨接端子具有第一端子部和第一板构件,其中,所述第一端子部与所述第一半导体芯片的主电极电连接;
第二跨接端子,所述第二跨接端子具有第二端子部和第二板构件,其中,所述第二端子部与所述第二半导体芯片的主电极电连接;以及
树脂板,所述树脂板具有第一定位部、第二定位部及板部,其中,所述第一定位部载置于所述第一电路板的正面并对所述第一半导体芯片在所述第一电路板上的位置进行限定,所述第二定位部载置于所述第二电路板的正面并对所述第二半导体芯片在所述第二电路板上的位置进行限定,所述板部在所述第一电路板与所述第二电路板之间被所述第一板构件和所述第二板构件夹持。
2.如权利要求1所述的半导体装置,其特征在于,
所述第一板构件和所述第二板构件平行地配置,
在所述第一板构件和所述第二板构件中流过反向的电流。
3.如权利要求1所述的半导体装置,其特征在于,
所述板部为包括所述第一板构件和所述第二板构件重合的区域的大小。
4.如权利要求1所述的半导体装置,其特征在于,
所述树脂板包括:
第一***部,所述第一***部接纳所述第一板构件的***;以及
第二***部,所述第二***部接纳所述第二板构件的***。
5.如权利要求4所述的半导体装置,其特征在于,
所述第一***部设置在所述板部与所述第一定位部之间,
所述第二***部设置在所述板部与所述第二定位部之间。
6.如权利要求1所述的半导体装置,其特征在于,
所述第一定位部俯视观察为凸形,并利用构成凸形的台阶部分的两条边对所述第一半导体芯片的位置进行限定,
所述第二定位部俯视观察为凸形,并利用构成凸形的台阶部分的两条边对所述第二半导体芯片的位置进行限定。
7.如权利要求1所述的半导体装置,其特征在于,包括:
壳体,所述壳体对所述层叠基板进行收纳;
第一外部端子,所述第一外部端子设置于所述壳体,并将所述壳体的外部与内部连接;
第二外部端子,所述第二外部端子与所述第一外部端子相邻地设置于所述壳体,并将所述壳体的外部与内部连接;
第三外部端子,所述第三外部端子设置在所述壳体的与配置有所述第一外部端子一侧相反的一侧,并将所述壳体的外部与内部连接;
第一配线端子,所述第一配线端子具有第一底面部和第一侧面部,其中,所述第一底面部与所述层叠基板平行,在一端处与所述第一外部端子连接,并且另一端延伸到所述第三外部端子的前方,所述第一侧面部与所述第一底面部正交,并与所述第二板构件电连接;以及
第二配线端子,所述第二配线端子具有第二底面部和第二侧面部,其中,所述第二底面部与所述层叠基板平行,在一端处与所述第三外部端子连接,并且另一端延伸到所述第二外部端子的前方,所述第二侧面部与所述第二底面部正交,并与所述第一板构件电连接。
8.如权利要求7所述的半导体装置,其特征在于,
所述第一侧面部与所述第二板构件平行,
所述第二侧面部与所述第一板构件平行,
通过所述第一侧面部和所述第二侧面部,将所述第一板构件、所述板部及所述第二板构件夹持。
9.如权利要求7所述的半导体装置,其特征在于,还包括:
第三配线端子,所述第三配线端子具有第三底面部和第三侧面部,其中,所述第三底面部与所述层叠基板平行,在一端处与所述第二外部端子连接,并且另一端延伸到所述第二底面部的前方,所述第三侧面部在所述第三底面部的与所述第一底面部相对的边上与所述第三底面部正交,
所述第一侧面部延伸到与所述第三侧面部相对的位置处。
10.如权利要求7所述的半导体装置,其特征在于,
在所述第一底面部的另一端处与所述第二底面部相对,
所述第一配线端子在所述第一底面部的另一端的与所述第二底面部相对的边上具有与所述第一底面部正交的第二个第一侧面部,
所述第二配线端子在所述第二底面部的与所述第一底面部的另一端相对的边上具有与所述第二底面部正交的第二个第二侧面部。
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WO2018142864A1 (ja) | 2017-02-06 | 2018-08-09 | 富士電機株式会社 | 半導体モジュール、電気自動車およびパワーコントロールユニット |
JP6777243B2 (ja) * | 2017-10-19 | 2020-10-28 | 富士電機株式会社 | 半導体装置及び半導体装置の製造方法 |
JP6669789B2 (ja) * | 2018-01-19 | 2020-03-18 | ファナック株式会社 | 電気装置およびモータ駆動装置 |
JP7077728B2 (ja) * | 2018-04-02 | 2022-05-31 | 富士電機株式会社 | 組み立て治具及び半導体装置の製造方法 |
USD908632S1 (en) * | 2018-09-17 | 2021-01-26 | Cree Fayetteville, Inc. | Power module |
CN210042640U (zh) * | 2018-12-29 | 2020-02-07 | 台达电子企业管理(上海)有限公司 | 电子设备及其功率模块 |
JP1650295S (ja) | 2019-01-11 | 2020-01-20 | 半導体モジュール | |
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TWI734434B (zh) * | 2019-04-11 | 2021-07-21 | 日商新川股份有限公司 | 接合裝置 |
JP7428018B2 (ja) | 2020-03-06 | 2024-02-06 | 富士電機株式会社 | 半導体モジュール |
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