CN106449592B - A kind of differential inductor structure and its manufacture craft of high quality factor - Google Patents
A kind of differential inductor structure and its manufacture craft of high quality factor Download PDFInfo
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- CN106449592B CN106449592B CN201610708670.8A CN201610708670A CN106449592B CN 106449592 B CN106449592 B CN 106449592B CN 201610708670 A CN201610708670 A CN 201610708670A CN 106449592 B CN106449592 B CN 106449592B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
- H01L2224/81024—Applying flux to the bonding area
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Abstract
The present invention discloses the differential inductor structure and its manufacture craft of a kind of high quality factor.The differential inductor is located in annulus through silicon via array, and the through silicon via in annulus is divided into left and right side, and is from top to bottom first, second, third and fourth, five, six through silicon vias.Each through silicon via is laid out to the connection of layer according to design requirement progress metal layer, again.The present invention hollows out slot in silicon base using bosch technique, reduces silicon base loss.Using the through silicon via array structure three-dimensional differential inductor in annulus, coupling (current direction in metal layer and the metal wire being laid out in layer again is incorgruous two-by-two) and lesser effective area inside differential inductance will improve inductance value.
Description
Technical field
The invention belongs to passive electronic technical field, be related to a kind of high quality factor differential inductor structure and its
Manufacture craft.
Background technique
With the development of wireless telecommunications, radio frequency microwave circuit Medical Devices, WLAN and in terms of
It is widely applied.Wherein inductance plays an important role in the circuits such as filter, amplifier, frequency mixer and oscillator.
With the continuous diminution of integrated device, conventional two-dimensional inductor on area occupied and has been unable to satisfy demand on packaging cost.
In recent years, with the rapid development of three dimensional integrated circuits, a kind of emerging ic manufacturing process through silicon via work
Skill receives significant attention.The circuit of silicon chip surface can be connected to silicon chip back side by through silicon via by it, realize different layer devices it
Between electric property connection.And through silicon via technology can provide bigger design freedom and better electric property to design not
Same component.Wherein can be used for constructing the on pieces element such as three dimensional inductor and transformer based on through silicon via technology, the inductor with
Conventional two-dimensional inductor is compared, quality factor with higher.
The main judging quota of inductor performance superiority and inferiority is quality factor, if its quality factor is higher, inductance component
Performance is better.And the quality factor for improving inductor can mainly be carried out from the following aspects: 1. reduce the parasitic effect of substrate
It answers；2. reducing inductor resistance itself；3. improving itself effective inductance value.
In addition 8,143,952 B2 patent of U.S. Patent No., which gives, constructs inductor and transformer using through silicon via
Component structure.Inductor structure wherein is constructed using the chain structure of through silicon via, but there are a large amount of incorgruous electricity in the connection type
Stream greatly weakens inductance value, and then influences so that the quality factor of inductor decline.The present invention will be by effectively connecting
Current direction in adjacent through silicon via and metal interconnecting wires is consistent by mode, will enhance mutual inductance in this way, and then increases total electricity
Inductance value (improves itself effective inductance value).
As the demand to bandwidth is more urgent, the working frequency of three dimensional integrated circuits is continuously improved, noise coupling and electricity
Magnetic disturbance problem is further serious.Differential configuration circuit will effectively inhibit electromagnetic interference, reduce noise.And differential inductance can answer extensively
For in the RF ICs such as mobile phone, TV, wireless network.However traditional plane differential inductance still face area occupied and
The problems such as quality factor are low.And current existing through silicon via technique is using plasma etching through-hole, using chemical vapor deposition
Shallow lake method forms oxide layer in through-hole surfaces, fills through-hole finally by copper electro-plating method, and use chemical Mechanical Polishing Technique
Remove extra copper electroplated layer.In the through silicon via technique there is loss in silicon substrate bottom substrate, thus make the performance of inductance component
Decline, i.e., quality factor are reduced.The present invention will provide a kind of three-dimensional differential inductor structure of high quality factor.With tradition
Inductor is compared, and the coupling and lesser effective area inside differential inductance will improve inductance value.
Summary of the invention
It is an object of the invention in view of the deficiencies of the prior art, provide one kind to be based on hollowing out slot technique in silicon base
Three-dimensional differential inductor structure improve the inductance value of effective area by two layers of coil around through silicon via cross wiring.
Differential inductor of the present invention is located in annulus through silicon via array, and the through-silicon via structure is across silicon base
Copper is equipped with the insulating layer that material is silica in copper periphery, generally it is with a thickness of 0.5 μm, in insulating layer to prevent leakage current
Periphery is then silicon base.Circular ring structure is made of 12 through-silicon via structures, above-mentioned 12 through-silicon via structures are divided into the left and right sides
Distribution, left side through silicon via and right side through silicon via are symmetrical, and the adjacent through silicon via spacing of annulus the same side is identical.Passing through described in wherein
The radius of the copper of silicon base is 10 μm, is highly 230 μm；The annulus outer radius is 100 μm, and inside radius is 80 μm；
Preferably, the spacing of the adjacent through silicon via in annulus the same side is 31 μm；The first through silicon via of left side and the first silicon of right side
The spacing of through-hole is 115 μm.
Through silicon via in annulus is divided into left and right side, and is from top to bottom first, second, third and fourth, five, six through silicon vias.
Using the metal layer end of the first through silicon via of the first through silicon via of left side and right side as input port, the 6th through silicon via of left side and right side
The metal layer end of six through silicon vias is as output port.Metal wire arrangement, external metallization line are carried out first at the top of differential inductor
It is separately connected input port, the metal layer end of the second through silicon via of left side and the metal layer end of right side third through silicon via pass through metal wire
Interconnection, the metal layer end of left side third through silicon via and the metal layer end of the second through silicon via of right side intersect company by metal wire
It connects, the metal layer end of the 4th through silicon via of left side and the metal layer end of the 5th through silicon via of right side pass through metal wire interconnection, left side
The metal layer end of 5th through silicon via and the metal layer end of the 4th through silicon via of right side pass through metal wire interconnection, output port difference
Outside is connected to by metal wire；
It is laid out layer again in differential inductor bottom and carries out metal wire arrangement, the layer of the layout again end of the first through silicon via of left side
Pass through metal wire interconnection, the layer of the layout again end of the second through silicon via of left side with the layer of the layout again end of the second through silicon via of right side
Pass through metal wire interconnection, the layer of the layout again end of left side third through silicon via with the layer of the layout again end of the first through silicon via of right side
Pass through metal wire interconnection, the layer of the layout again end of the 4th through silicon via of left side with the layer of the layout again end of the 4th through silicon via of right side
Pass through metal wire interconnection, the layer of the layout again end of the 5th through silicon via of left side with the layer of the layout again end of right side third through silicon via
Pass through metal wire interconnection, the layer of the layout again end of the 6th through silicon via of left side with the layer of the layout again end of the 6th through silicon via of right side
Pass through metal wire interconnection with the layer of the layout again end of the 5th through silicon via of right side.
A further object of the present invention is to provide the process for making of above-mentioned three-dimensional differential inductor structure.This method packet
Containing following steps:
Step (1), progress silicon base wafer first are thinned, and polish to silicon wafer upper and lower surface；
Step (2) carries out precipitation of silica formation oxide layer (its thickness is greater than 0.5 μm) in silicon wafer upper and lower surface, and
Through silicon via region is defined, anisotropic corrosion silica is passed sequentially through；
Step (3) is defining in through silicon via region, using Bosch technique etching silicon wafer, forms through-hole；
Step (4), 0.5 μm of thickness for defining oxide layer, and the blocked up oxide layer of silicon wafer upper and lower surface is removed, until
Its thickness reaches 0.5 μm, additionally synchronizes the oxide layer to be formed with a thickness of 0.5 μm in the side wall of through-hole；
Step (5) carries out copper filling to through-hole using copper electric plating method, through-hole is filled full；
Step (6) hollows out slot structure using bosch technique around copper vias so that the silicon base around copper with a thickness of
10μm；
Step (7), in silicon wafer metal layer at top according to designed layout, carry out metal wire connection；
Step (8) is laid out layer by the progress metal wire connection of designed layout, later again again on new silicon wafer
It is laid out position corresponding with another silicon wafer through silicon via on layer and adds solder joint.
Step (9) will be finally bonded above and below two pieces of silicon wafers progress.
The present invention hollows out slot in silicon base using bosch technique, reduces silicon base loss.Utilize the through silicon via battle array in annulus
Column construct three-dimensional differential inductor, coupling (metal layer and the electric current being laid out in the metal wire in layer again inside differential inductance
Flow to it is incorgruous two-by-two) and lesser effective area will improve inductance value.
Detailed description of the invention
Fig. 1 is according to the inductance member shown by 8,143,952 B2 patent of U.S. Patent No. with through silicon via construction
Part；
Fig. 2 is the top and bottom sectional view of three-dimensional differential inductor；
Fig. 3 is the perspective view of three-dimensional differential inductor；
Fig. 4 A-H is the process flow chart of present invention production inductor.
It is marked in Fig. 1 as follows: inductance element 100, first input port 101, the second input port 102, through substrate
Through silicon via 103, the metal wire 104 in base top metal layer M1, the metal wire 105 of substrate bottom being laid out in layer again；
Fig. 2, label is as follows in 3: the first through silicon via of left side 401, the second through silicon via of left side 402, left side third through silicon via
403, the 4th through silicon via 404 of left side, the 5th through silicon via 405 of left side, the 6th through silicon via 406 of left side, the first through silicon via of right side 407,
The second through silicon via of right side 408, right side third through silicon via 409, the 4th through silicon via 410 of right side, the 5th through silicon via 411 of right side, right side
6th through silicon via 412；
It is marked in Fig. 4 A-H as follows: silicon wafer 601, silicon wafer upper and lower surface silica 602, through silicon via region 603, through-hole
604, through-hole side wall oxide layer 605, copper 606, empty slot structure 607, again be laid out layer 608, solder joint 609.
Specific embodiment
Below in conjunction with attached drawing, the invention will be further described.
Fig. 1 is according to the inductance member shown by 8,143,952 B2 patent of U.S. Patent No. with through silicon via construction
Part 100 comprising input port 101 and 102, the through silicon via 103 through substrate, the metal wire in base top metal layer M1
104 and substrate bottom again be laid out layer in metal wire 105.It extends metal wire using through silicon via technology as seen from the figure
Length, to obtain biggish inductance value.But it is limited to through silicon via size, self-induction is smaller, and metal layer M1 and is laid out layer again
There are a large amount of heterodromes in middle metal wire, can reduce overall inductance value.
Fig. 2 is the top and bottom sectional view of three-dimensional differential inductor.Differential inductor is located in annulus through silicon via array,
Through silicon via in annulus is divided into left and right side, and is from top to bottom first, second, third and fourth, five, six through silicon vias.By left side
The metal layer end of one through silicon via 401 and the first through silicon via of right side 407 is as input port, the 6th through silicon via 406 of left side and right side
The metal layer end of 6th through silicon via 412 is as output port.Metal wire arrangement is carried out at the metal layer end of differential inductor, it is external
Metal wire is respectively connected to the metal layer end (input port) of the first through silicon via of left and right side, the second through silicon via of left side 402
Metal layer end and the metal layer end of right side third through silicon via 409 pass through metal wire interconnection, the gold of left side third through silicon via 403
The metal layer end for belonging to layer end and the second through silicon via of right side 408 passes through metal wire interconnection, the metal of the 4th through silicon via 404 of left side
Layer end and the metal layer end of the 5th through silicon via 411 of right side pass through metal wire interconnection, the metal of the 5th through silicon via 405 of left side
Layer end and the metal layer end of the 4th through silicon via 410 of right side pass through metal wire interconnection, the gold of the 6th through silicon via of left and right side
Belong to layer end (output port) and metal wire is connected to outside respectively；
It is laid out layer again in differential inductor and carries out metal wire arrangement, the layer of the layout again end of the first through silicon via of left side 401
Pass through metal wire interconnection, the cloth again of the second through silicon via of left side 402 with the layer of the layout again end of the second through silicon via of right side 408
Office layer end and the layer of the layout again end of the first through silicon via of right side 407 pass through metal wire interconnection, left side third through silicon via 403
Again by metal wire interconnection, the 4th silicon of left side is logical for layout layer end and the layer of the layout again end of the 4th through silicon via 410 of right side
Again the layout layer end in hole 404 and the layer of the layout again end of right side third through silicon via 409 are by metal wire interconnection, left side the
The layout layer end again of five through silicon vias 405 and the layer of the layout again end of the 6th through silicon via 412 of right side pass through metal wire interconnection,
The layout layer end again of the 6th through silicon via 406 of left side and the layer of the layout again end of the 5th through silicon via 411 of right side are handed over by metal wire
Fork connection.
Fig. 3 is the perspective view of three-dimensional differential inductor, and the course of work of the inductance element: electric current is respectively from two input ports
(413 and 414) are begun to flow into, first electric current from input port 413 by metal wire flow into left side the first through silicon via 401 gold
Belong to layer end, and it is flowed to by through silicon via and is laid out layer end again, the weight of the second through silicon via 408 of right side is then flowed to by metal wire
New layout layer end, and by flowing to its metal layer end, the metal layer of left side third through silicon via 403 is then flowed by metal wire
End, and it is flowed to by through silicon via and is laid out layer end again, the 4th through silicon via 410 of right side is then flowed to again by metal wire
It is laid out layer end, and its metal layer end is flowed to by through silicon via, the gold of the 5th through silicon via 405 of left side is then flowed by metal wire
Belong to layer end, and it is flowed to by through silicon via and is laid out layer end again, the weight of the 6th through silicon via 412 of right side is then flowed to by metal wire
New layout layer end, and by flowing to its metal layer end, then flow to its output port 416；Another electric current is logical from input port 414
It crosses metal wire and flows into the metal layer end of the first through silicon via 407 of right side, and it is flowed to by through silicon via and is laid out layer end again, then
The layer of the layout again end of the second through silicon via 402 of left side is flowed to by metal wire, and by flowing to its metal layer end, then passes through gold
Belong to line and flow into the metal layer end of right side third through silicon via 409, and it is flowed to by through silicon via and is laid out layer end again, then passes through
The layer of the layout again end of the 4th through silicon via 404 of metal wire flow direction left side, and its metal layer end is flowed to by through silicon via, then lead to
It crosses metal wire and flows into the metal layer end of the 5th through silicon via 411 of right side, and it is flowed to by through silicon via and is laid out layer end again, then
The layer of the layout again end of the 6th through silicon via 406 of left side is flowed to by metal wire, and by flowing to its metal layer end, then flows to it
Output port 415.
The manufacturing process of above-mentioned inductor:
Step 1, as shown in Figure 4 A, progress wafer first are thinned, and polish to 601 upper and lower surface of silicon wafer；
Step 2 carries out the precipitating of silica 602 in 601 upper and lower surface of silicon wafer and forms oxide layer (its thickness as shown in Figure 4 B
Degree is greater than 0.5 μm), and through silicon via region 603 is defined, pass sequentially through anisotropic corrosion silica.
Step 3 is defining in through silicon via region as shown in Figure 4 C, using Bosch technique etching silicon wafer, forms through-hole
604；
Step 4, as shown in Figure 4 D, define oxide layer with a thickness of 0.5 μm, and it is blocked up to remove silicon wafer upper and lower surface
Oxide layer 602 additionally synchronize the oxygen to be formed with a thickness of 0.5 μm in the side of through-hole 604 until its thickness reaches 0.5 μm
Change layer 605.
Step 5 carries out copper filling 606 to through-hole using copper electric plating method as shown in Figure 4 E；
Step 6 hollows out slot structure 607 using bosch technique, so that around copper as illustrated in figure 4f around copper vias
Silicon base is with a thickness of 10 μm；
Step 7 carries out metal wire connection in silicon wafer metal layer according to the layout of Fig. 4 A (differential inductor)；
Step 8, as shown in Figure 4 G, the layer of layout again on new silicon wafer according to Fig. 4 B (differential inductor) layout
Connection is being laid out position addition solder joint 609 corresponding with another silicon wafer through silicon via on layer 608 later again.
Two pieces of silicon wafers are finally carried out fitting up and down as shown at figure 4h by step 9.
Above-described embodiment is not for limitation of the invention, and the present invention is not limited only to above-described embodiment, as long as meeting
The present invention claims all belong to the scope of protection of the present invention.
Claims (9)
1. a kind of based on the differential inductor for hollowing out slot technique in silicon base, it is characterised in that differential inductor is located at annulus silicon
In through-hole array, through silicon via is equipped with 12 in the annulus, is uniformly arranged at left and right sides of above-mentioned 12 through silicon vias, and left side through silicon via
Symmetrical with right side through silicon via, the adjacent through silicon via spacing of the same side is identical；
Left and right side through silicon via is first, second, third and fourth, five, six through silicon vias from top to bottom；By the first through silicon via of left side and right side
The metal layer end of one through silicon via is as input port, and the metal layer end of the 6th through silicon via of left side and the 6th through silicon via of right side is as defeated
Exit port；
Metal wire arrangement is carried out first at the top of differential inductor, external metallization line is separately connected input port, the second silicon of left side
The metal layer end of through-hole and the metal layer end of right side third through silicon via pass through metal wire interconnection, the gold of left side third through silicon via
Belong to the metal layer end of layer end and the second through silicon via of right side by metal wire interconnection, the metal layer end of the 4th through silicon via of left side with
The metal layer end of the 5th through silicon via of right side passes through metal wire interconnection, the metal layer end and right side the 4th of the 5th through silicon via of left side
The metal layer end of through silicon via passes through metal wire respectively and is connected to outside by metal wire interconnection, output port；
It is laid out layer again in differential inductor bottom and carries out metal wire arrangement, the layer of the layout again end and the right side of the first through silicon via of left side
The layer of the layout again end of the second through silicon via of side passes through metal wire interconnection, the layer of the layout again end and the right side of the second through silicon via of left side
The layer of the layout again end of the first through silicon via of side passes through metal wire interconnection, the layer of the layout again end and the right side of left side third through silicon via
The layer of the layout again end of the 4th through silicon via of side passes through metal wire interconnection, the layer of the layout again end and the right side of the 4th through silicon via of left side
The layer of the layout again end of side third through silicon via passes through metal wire interconnection, the layer of the layout again end and the right side of the 5th through silicon via of left side
The layer of the layout again end of the 6th through silicon via of side passes through metal wire interconnection, the layer of the layout again end and the right side of the 6th through silicon via of left side
The layer of the layout again end of the 5th through silicon via of side passes through metal wire interconnection.
2. as described in claim 1 a kind of based on the differential inductor for hollowing out slot technique in silicon base, it is characterised in that silicon
Copper periphery insulating layer with a thickness of 0.5 μm in through-hole structure.
3. as described in claim 1 a kind of based on the differential inductor for hollowing out slot technique in silicon base, it is characterised in that silicon
Radius in through-hole structure across the copper of silicon base is 10 μm, is highly 230 μm.
4. as described in claim 1 a kind of based on the differential inductor for hollowing out slot technique in silicon base, it is characterised in that institute
The annulus outer radius for the annulus through silicon via array stated is 100 μm, and inside radius is 80 μm.
5. as described in claim 1 a kind of based on the differential inductor for hollowing out slot technique in silicon base, it is characterised in that circle
The spacing of the adjacent through silicon via in ring the same side is 31 μm.
6. as described in claim 1 a kind of based on the differential inductor for hollowing out slot technique in silicon base, it is characterised in that left
The spacing of the first through silicon via of side and the first through silicon via of right side is 115 μm.
7. a kind of manufacture craft based on the differential inductor for hollowing out slot technique in silicon base as described in claim 1,
It is characterized in that the process includes the following:
Step (1), progress silicon base wafer first are thinned, and polish to the silicon base upper and lower surface；
Step (2) carries out precipitation of silica in step (1) treated silicon base upper and lower surface, forms oxide layer；Then fixed
Justice goes out through silicon via region, passes sequentially through anisotropic corrosion silica；
Step (3), in the through silicon via region defined, utilize Bosch technique etch silicon base, formed through-hole；
The blocked up oxide layer of step (4), removal silicon base upper and lower surface, until certain thickness；Simultaneously in the side of step (3) through-hole
Wall forms certain thickness oxide layer；
Step (5) carries out copper filling to through-hole using copper electric plating method, through-hole is filled full；
Step (6) hollows out slot structure in copper vias periphery silicon base using bosch technique；
Step (7) handles obtained silicon base metal layer at top layout described in accordance with the claim 1 in above-mentioned steps (6), into
The connection of row metal line；
Step (8) separately takes a new silicon base, is laid out layer layout described in accordance with the claim 1 again and carries out metal wire connection；
Step (9) is added in the layer of the layout again position corresponding with step (7) silicon base through silicon via of step (8) silicon base
Two pieces of silicon bases are finally carried out fitting up and down by solder joint.
8. manufacture craft as claimed in claim 7, it is characterised in that step (4) is specifically that removal silicon base upper and lower surface is blocked up
Oxide layer, until its thickness reaches 0.5 μm；The oxide layer with a thickness of 0.5 μm is formed in the side wall of step (3) through-hole simultaneously.
9. manufacture craft as claimed in claim 7, it is characterised in that step (6) is specifically using bosch technique in copper vias
Periphery silicon base hollows out slot structure, and the silicon base around copper is with a thickness of 10 μm.
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| EP0920036A1 (en) * | 1997-11-28 | 1999-06-02 | STMicroelectronics SA | Integrated circuit transformer |
| CN101142638A (en) * | 2005-08-04 | 2008-03-12 | 加利福尼亚大学董事 | Interleaved three-dimensional on-chip differential inductors and transformers |
| CN103824840A (en) * | 2012-11-16 | 2014-05-28 | 南京理工大学 | Solenoid type difference inductor based on silicon through hole |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011096778A (en) * | 2009-10-28 | 2011-05-12 | Seiko Epson Corp | Wiring structure of spiral coil and integrated circuit device |
| US9275786B2 (en) * | 2014-07-18 | 2016-03-01 | Qualcomm Incorporated | Superposed structure 3D orthogonal through substrate inductor |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0920036A1 (en) * | 1997-11-28 | 1999-06-02 | STMicroelectronics SA | Integrated circuit transformer |
| CN101142638A (en) * | 2005-08-04 | 2008-03-12 | 加利福尼亚大学董事 | Interleaved three-dimensional on-chip differential inductors and transformers |
| CN103824840A (en) * | 2012-11-16 | 2014-05-28 | 南京理工大学 | Solenoid type difference inductor based on silicon through hole |
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