CN106449554B - 带有封闭空腔的芯片嵌入式封装结构及其制作方法 - Google Patents
带有封闭空腔的芯片嵌入式封装结构及其制作方法 Download PDFInfo
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- CN106449554B CN106449554B CN201611109949.0A CN201611109949A CN106449554B CN 106449554 B CN106449554 B CN 106449554B CN 201611109949 A CN201611109949 A CN 201611109949A CN 106449554 B CN106449554 B CN 106449554B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 152
- 239000005022 packaging material Substances 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 25
- 238000009825 accumulation Methods 0.000 claims description 38
- 229910000679 solder Inorganic materials 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 24
- 239000002313 adhesive film Substances 0.000 claims description 19
- 238000005538 encapsulation Methods 0.000 claims description 17
- 239000000919 ceramic Substances 0.000 claims description 7
- 239000011521 glass Substances 0.000 claims description 7
- 238000007789 sealing Methods 0.000 claims description 6
- 229920006336 epoxy molding compound Polymers 0.000 claims description 4
- 229920002799 BoPET Polymers 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims 3
- 239000010410 layer Substances 0.000 description 116
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 12
- 229910052802 copper Inorganic materials 0.000 description 12
- 239000010949 copper Substances 0.000 description 12
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- 238000000206 photolithography Methods 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 9
- 238000010897 surface acoustic wave method Methods 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 239000002184 metal Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 4
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- 238000005530 etching Methods 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 238000004528 spin coating Methods 0.000 description 4
- 238000003475 lamination Methods 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 229910018487 Ni—Cr Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 2
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims (14)
Priority Applications (1)
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CN201611109949.0A CN106449554B (zh) | 2016-12-06 | 2016-12-06 | 带有封闭空腔的芯片嵌入式封装结构及其制作方法 |
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CN201611109949.0A CN106449554B (zh) | 2016-12-06 | 2016-12-06 | 带有封闭空腔的芯片嵌入式封装结构及其制作方法 |
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CN106449554A CN106449554A (zh) | 2017-02-22 |
CN106449554B true CN106449554B (zh) | 2019-12-17 |
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Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
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CN108091616A (zh) * | 2017-12-15 | 2018-05-29 | 苏州晶方半导体科技股份有限公司 | 一种芯片的封装方法以及封装结构 |
CN107910274A (zh) * | 2017-12-18 | 2018-04-13 | 苏州晶方半导体科技股份有限公司 | 一种指纹芯片的封装方法以及封装结构 |
CN107958882A (zh) * | 2017-12-20 | 2018-04-24 | 苏州晶方半导体科技股份有限公司 | 芯片的封装结构及其制作方法 |
CN108269781A (zh) * | 2018-03-27 | 2018-07-10 | 苏州晶方半导体科技股份有限公司 | 一种芯片的封装结构以及封装方法 |
CN108470724A (zh) * | 2018-03-27 | 2018-08-31 | 苏州晶方半导体科技股份有限公司 | 一种芯片的封装结构以及封装方法 |
CN108257921A (zh) * | 2018-03-27 | 2018-07-06 | 苏州晶方半导体科技股份有限公司 | 一种芯片的封装结构以及封装方法 |
WO2020001583A1 (zh) * | 2018-06-29 | 2020-01-02 | 宁波舜宇光电信息有限公司 | 线路板组件、感光组件、摄像模组及其制作方法 |
CN109087909A (zh) * | 2018-08-10 | 2018-12-25 | 付伟 | 具有金属柱的多腔室封装结构及其制作方法 |
CN108711569A (zh) * | 2018-08-10 | 2018-10-26 | 付伟 | 带有容纳滤波器芯片腔室的多芯片封装结构及其制作方法 |
CN108807350A (zh) * | 2018-08-10 | 2018-11-13 | 付伟 | 放大器芯片电极外设的多腔室封装结构及其制作方法 |
CN108766955A (zh) * | 2018-08-10 | 2018-11-06 | 付伟 | Rf开关芯片电极外设的多腔室封装结构及其制作方法 |
CN108831876B (zh) * | 2018-08-10 | 2024-03-08 | 浙江熔城半导体有限公司 | 滤波器芯片内嵌且具有孔洞的封装结构及其制作方法 |
CN108831881A (zh) * | 2018-08-10 | 2018-11-16 | 付伟 | 带有腔室的上下堆叠式多芯片封装结构及其制作方法 |
CN109065531A (zh) * | 2018-08-10 | 2018-12-21 | 付伟 | 外设式多芯片封装结构及其制作方法 |
CN108831875B (zh) * | 2018-08-10 | 2024-03-05 | 浙江熔城半导体有限公司 | 滤波器芯片内嵌且电极外设的封装结构及其制作方法 |
CN109087912A (zh) * | 2018-08-10 | 2018-12-25 | 付伟 | 带有腔室的多芯片封装结构及其制作方法 |
CN108766956A (zh) * | 2018-08-10 | 2018-11-06 | 付伟 | 具有多腔室的多芯片封装结构及其制作方法 |
CN109087911A (zh) * | 2018-08-10 | 2018-12-25 | 付伟 | 带有容纳功能芯片腔室的多芯片封装结构及其制作方法 |
CN109103173B (zh) * | 2018-08-10 | 2024-04-16 | 浙江熔城半导体有限公司 | 滤波器芯片内嵌且引脚上置的封装结构及其制作方法 |
CN109257874A (zh) * | 2018-11-16 | 2019-01-22 | 深圳市和美精艺科技有限公司 | 一种在pcb板制作过程中芯片埋入的方法及其结构 |
CN109494163A (zh) * | 2018-11-20 | 2019-03-19 | 苏州晶方半导体科技股份有限公司 | 芯片的封装结构以及封装方法 |
TWI692802B (zh) * | 2019-04-30 | 2020-05-01 | 欣興電子股份有限公司 | 線路載板結構及其製作方法與晶片封裝結構 |
CN110127597A (zh) * | 2019-06-14 | 2019-08-16 | 苏州敏芯微电子技术股份有限公司 | 背孔引线式压力传感器及其制备方法 |
CN111884613B (zh) * | 2020-06-19 | 2021-03-23 | 珠海越亚半导体股份有限公司 | 一种具有空气谐振腔的嵌埋封装结构的制造方法 |
CN115632034A (zh) * | 2022-12-20 | 2023-01-20 | 珠海妙存科技有限公司 | eMMC模组封装结构及其制作方法 |
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CN1428930A (zh) * | 2001-12-18 | 2003-07-09 | 株式会社村田制作所 | 声表面波装置 |
US7368808B2 (en) * | 2003-06-30 | 2008-05-06 | Intel Corporation | MEMS packaging using a non-silicon substrate for encapsulation and interconnection |
US8138590B2 (en) * | 2008-06-20 | 2012-03-20 | Stats Chippac Ltd. | Integrated circuit package system with wire-in-film encapsulation |
CN102870326A (zh) * | 2010-05-07 | 2013-01-09 | 株式会社村田制作所 | 弹性表面波装置以及其制造方法 |
CN106158772A (zh) * | 2015-03-27 | 2016-11-23 | 蔡亲佳 | 板级嵌入式封装结构及其制作方法 |
CN206312887U (zh) * | 2016-12-06 | 2017-07-07 | 苏州源戍微电子科技有限公司 | 带有封闭空腔的芯片嵌入式封装结构 |
Family Cites Families (1)
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JP5113627B2 (ja) * | 2007-06-12 | 2013-01-09 | 日本電波工業株式会社 | 電子部品及びその製造方法 |
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2016
- 2016-12-06 CN CN201611109949.0A patent/CN106449554B/zh active Active
Patent Citations (6)
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CN1428930A (zh) * | 2001-12-18 | 2003-07-09 | 株式会社村田制作所 | 声表面波装置 |
US7368808B2 (en) * | 2003-06-30 | 2008-05-06 | Intel Corporation | MEMS packaging using a non-silicon substrate for encapsulation and interconnection |
US8138590B2 (en) * | 2008-06-20 | 2012-03-20 | Stats Chippac Ltd. | Integrated circuit package system with wire-in-film encapsulation |
CN102870326A (zh) * | 2010-05-07 | 2013-01-09 | 株式会社村田制作所 | 弹性表面波装置以及其制造方法 |
CN106158772A (zh) * | 2015-03-27 | 2016-11-23 | 蔡亲佳 | 板级嵌入式封装结构及其制作方法 |
CN206312887U (zh) * | 2016-12-06 | 2017-07-07 | 苏州源戍微电子科技有限公司 | 带有封闭空腔的芯片嵌入式封装结构 |
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Effective date of registration: 20201016 Address after: 215000, Suzhou Industrial Park, Jinji Lake Road, 99, Suzhou City, northwest of the city of Jiangsu, 5, 3 Patentee after: SUZHOU YUANSHU MICROELECTRONICS TECHNOLOGY Co.,Ltd. Address before: 313200 No. 926 Changhong East Street, Fuxi Street, Deqing County, Huzhou City, Zhejiang Province (Mogan Mountain National High-tech Zone) Patentee before: Zhejiang Rongcheng Semiconductor Co., Ltd |
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