CN106448532B - Shift register, drive circuit and display panel - Google Patents
Shift register, drive circuit and display panel Download PDFInfo
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- CN106448532B CN106448532B CN201610860031.3A CN201610860031A CN106448532B CN 106448532 B CN106448532 B CN 106448532B CN 201610860031 A CN201610860031 A CN 201610860031A CN 106448532 B CN106448532 B CN 106448532B
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- 239000000758 substrate Substances 0.000 claims description 9
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- 238000010586 diagram Methods 0.000 description 25
- 101100102583 Schizosaccharomyces pombe (strain 972 / ATCC 24843) vgl1 gene Proteins 0.000 description 14
- 102100023478 Transcription cofactor vestigial-like protein 1 Human genes 0.000 description 14
- 101100102598 Mus musculus Vgll2 gene Proteins 0.000 description 9
- 102100023477 Transcription cofactor vestigial-like protein 2 Human genes 0.000 description 9
- 238000000034 method Methods 0.000 description 7
- 230000005540 biological transmission Effects 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 238000006073 displacement reaction Methods 0.000 description 3
- 108010076504 Protein Sorting Signals Proteins 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000032696 parturition Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
- Shift Register Type Memory (AREA)
Abstract
The invention provides a shift register, a driving circuit and a display panel, which comprise an initial control module, a first reverse module, a second reverse module, a pull-up control module, a first pull-up output module, a second pull-up output module, a first pull-down output module, a second pull-down output module, a first node, a second node, a third node and a fourth node, wherein: the modules each include at least one switch. The first pull-up output module and the first pull-down output module are used for controlling signal output of the first signal output end, the second pull-up output module and the second pull-down output module are used for controlling signal output of the second signal output end, the first signal output end is electrically connected with a grid electrode of the display panel, and the second signal output end is electrically connected with a signal input end of the next-stage shift register. The semiconductor oxide transistor of the shift register is not conducted due to negative bias of a threshold value through two low level signal input ends with different level signal values.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of shift registers, driving circuit and display panel.
Background technique
Currently, conductor oxidate transistor be since its own characteristic of semiconductor can drive ultra high-definition display panel, and
Mobility high power consumption is low so that more and more display panels begin to use conductor oxidate transistor.
The gate driving circuit of small-medium size display panel uses 7T2C (7 thin film transistor (TFT)s and 2 electricity more at present
Hold) construction, 7 thin film transistor (TFT)s can be effectively reduced power consumption using conductor oxidate transistor and meet the need of high pixel
It asks.But due to the technological problems of producing line now, so that conductor oxidate transistor is in the production process due to process conditions
Fluctuation and the inclined negative value of threshold voltage that causes transistor itself.In addition, backlight luminescence irradiation at present, so that the half of array substrate side
Conducting oxide transistor is illuminated by the light influence and leads to the inclined negative value of itself threshold voltage.
Due to the inclined negative value of transistor threshold voltage, so that transistor can be opened with clock pulse signal and be exported to grid
Pole has larger impact to the display effect of panel.
Summary of the invention
To solve the above problems, the present invention provides a kind of shift register, including initial control module, the first reversed mould
Block, the second reversed module, pull-up control module, the first pull-up output module, the second pull-up output module, the first drop-down output mould
Block, the second drop-down output module, first node, second node, third node and fourth node, in which:
The initial control module, the first reversed module, the second reversed module, the pull-up control module,
The first pull-up output module, the second pull-up output module, the first drop-down output module, second drop-down are defeated
Module includes at least one switch out；
The initial control module electrical connection signal input part, high level signal input terminal, the first clock signal input terminal,
First low level signal input terminal, for generating control signal；
The first reversed module is electrically connected with the initial control module by the first node, and described first is reversed
Module is electrically connected the high level signal input terminal, the first low level signal input terminal and the input of the second low level signal
End；
The second reversed module is electrically connected with the described first reversed module by the second node, and described second is reversed
Module is electrically connected the high level signal input terminal, the first low level signal input terminal and the input of the second low level signal
End；
The pull-up control module is electrically connected with the described first reversed module by the second node, anti-with described second
It is realized and is electrically connected by the third node to module, the pull-up control module is electrically connected the signal input part, for lifting
High node current potential；
The first pull-up output module is electrically connected with the pull-up control module by the fourth node, and described first
Pull up output module electrical connection second clock signal input part and the first signal output end；
The second pull-up output module is electrically connected with the first pull-up output module by the fourth node, described
Second pull-up output module electrical connection second clock signal input part and second signal output end, for being moved to described in next stage
Bit register input signal；
The first drop-down output module is electrically connected with the described second reversed module by third node realization,
The first drop-down output module is electrically connected the first low level signal input terminal and the first signal output end；
The second drop-down output module is electrically connected with the described second reversed module by third node realization, described
Second drop-down output module is electrically connected the second low level signal input terminal and second signal output end, for described in next stage
Shift register input signal.
A kind of driving circuit, including N grades of any one shift register described above, N is positive integer, wherein
The second signal of shift register described in the signal input part electrical connection i-stage of the i+1 grade shift register
Output end, i are the positive integer less than N.
A kind of display panel, comprising:
Underlay substrate, the underlay substrate have viewing area and surround the non-display area of the viewing area；
Grid line is set to the viewing area；
Data line is set to the viewing area, intersects with grid line insulation to limit multiple pixel regions；
Driving circuit described above is set to the non-display area；
The grid line is electrically connected the first signal output end in the driving circuit.
Compared with prior art, technical solution of the present invention has one of the following advantages: shift register provides initial control
Molding block, the first reversed module, the second reversed module, pull-up control module, the first pull-up output module, the second pull-up output mould
Block, the first drop-down output module, the second drop-down output module.Wherein, the first pull-up output module and the first drop-down output mould
Block is used to control the signal output of the first signal output end, and the second pull-up output module and the second drop-down output module are for controlling
The signal of second signal output end processed exports, and the first signal output end is electrically connected the grid of display panel, second signal output end
It is electrically connected the signal input part of next stage shift register.By the different low level signal input terminal of two level signal values,
Realize that the conductor oxidate transistor of shift register is not connected because threshold value is partially negative.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of module connection diagram of shift register provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of initial control module provided in an embodiment of the present invention；
Fig. 3 is the structural schematic diagram of the provided in an embodiment of the present invention first reversed module；
Fig. 4 is the structural schematic diagram of the provided in an embodiment of the present invention second reversed module；
Fig. 5 is the structural schematic diagram of pull-up control module provided in an embodiment of the present invention；
Fig. 6 is the structural schematic diagram of the first pull-up output module provided in an embodiment of the present invention；
Fig. 7 is the structural schematic diagram of the second pull-up output module provided in an embodiment of the present invention；
Fig. 8 is the structural schematic diagram of the first drop-down output module provided in an embodiment of the present invention；
Fig. 9 is the structural schematic diagram of the second drop-down output module provided in an embodiment of the present invention；
Figure 10 is a kind of attachment structure schematic diagram of shift register provided in an embodiment of the present invention；
Figure 11 is a kind of structural schematic diagram of driving circuit provided in an embodiment of the present invention；
Figure 12 is a kind of driving method for driving Figure 11 driving circuit provided in an embodiment of the present invention；
Figure 13 is a kind of schematic diagram of display panel provided in an embodiment of the present invention.
Specific embodiment
A kind of shift register of the invention and driving circuit are described in more detail below with reference to schematic diagram, wherein
Illustrating the preferred embodiment of the present invention, it should be appreciated that those skilled in the art can modify invention described herein, and still
So realize advantageous effects of the invention.Therefore, following description should be understood as the widely known of those skilled in the art,
And it is not intended as limitation of the present invention.
Fig. 1 is a kind of module connection diagram of shift register provided in an embodiment of the present invention, a kind of displacement of the present invention
Register include initial control module 1, the first reversed module 2, the second reversed module 3, pull-up control module 4, first pull-up it is defeated
Module 5, second pulls up output module 6, first and pulls down output module 7, second drop-down output module 8, first node A, second out
Node B, third node C, fourth node D, initial control module 1, the first reversed module 2, the second reversed module 3, pull-up control
Module 4, first pulls up output module 5, second and pulls up the drop-down drop-down output module 8 of output module 7, second of output module 6, first
It include at least one switch, which can be MOS transistor, in which:
It is defeated that initial control module 1 is electrically connected signal input part Cn-1, high level signal input terminal VGH, the first clock signal
Enter to hold CK1, the first low level signal input terminal VGL1, initial control module 1 transmits it to for generating control signal
One node A.
First reversed module 2 is electrically connected with initial control module 1 by first node A realization, and the first reversed module 2 is electrically connected
Meet high level signal input terminal VGH, the first low level signal input terminal VGL1 and the second low level signal input terminal VGL2.The
One reversed module 2 is mainly used for reversely being exported the current potential of first node A, and is transmitted to second node B.
Second reversed module 3 is electrically connected with the first reversed module 2 by second node B realization, and the second reversed module 3 is electrically connected
Meet high level signal input terminal VGH, the first low level signal input terminal VGL1 and the second low level signal input terminal VGL2.The
Two reversed modules 3 are mainly used for reversely being exported the current potential at second node B, and are transmitted to node third node C.This
When, third node C is identical as the electrical property of first node A, but current potential is different.
Pull-up control module 4 is electrically connected with the described first reversed module 2 by second node B realization, with the second reversed mould
Block 3 realizes electrical connection by third node C, and pull-up control module 4 is electrically connected signal input part Cn-1, for raising node electricity
Position.
First pull-up output module 5 is electrically connected with pull-up control module 4 by fourth node D realization, the first pull-up output
Module 5 is electrically connected second clock signal input part CK2 and the first signal output end Gn.First pull-up output module 5 is for giving
First signal output end Gn transmits output signal.
Second pull-up output module 6 is electrically connected with the first pull-up output module 5 by fourth node D realization, the second pull-up
Output module 6 is electrically connected second clock signal input part CK2 and second signal output end Cn, is used for next stage shift LD
Device transmits input signal.
First drop-down output module 7 is electrically connected with the second reversed module 3 by third node C realization, the first drop-down output
Module 7 is electrically connected the first low level signal input terminal VGL1 and the first signal output end Gn.First drop-down output module 7 is used for
Output signal is transmitted to the first signal output end Gn.
Second drop-down output module 8 is electrically connected with the second reversed module 3 by third node C realization, the second drop-down output
Module 8 is electrically connected the second low level signal input terminal VGL2 and second signal output end Cn, for shifting to described in next stage
Register input signal.
For the clearer specific connection structure for illustrating modules, now by Fig. 2 to Fig. 9 to first device of modules
Part is illustrated.Detailed description of the invention is one kind of the present embodiment, not limitation of the present invention.
Fig. 2 is the structural schematic diagram of initial control module provided in an embodiment of the present invention, and initial control module 1 includes first
Switch M1 and second switch M2.The control terminal of first switch M1 is electrically connected the first clock signal input terminal CK1, first switch M1
The first pole be electrically connected high level signal input terminal VGH, the second pole of first switch M1 is electrically connected first node A.Second switch
The control terminal of M2 is electrically connected signal input part Cn-1, and the first pole of second switch M2 is electrically connected the first low level signal input terminal
The second pole of VGL1, second switch M2 are electrically connected first node A.First node A is received to be inputted by high level signal input terminal VGH
High level signal or the first low level signal input terminal VGL1 input low level signal.
Fig. 3 is the structural schematic diagram of the provided in an embodiment of the present invention first reversed module, and the first reversed module 2 includes third
Switch M3, the 4th switch M4, the 5th switch M5 and the 6th switch M6, wherein the high electricity of control terminal electrical connection of third switch M3
The first pole of flat signal input part VGH, third switch M3 is electrically connected high level signal input terminal VGH, and the second of third switch M3
Pole is electrically connected the control terminal of the 4th switch M4.The first pole of 4th switch M4 is electrically connected high level signal input terminal VGH, and the 4th opens
The second pole for closing M4 is electrically connected second node B.The control terminal of 5th switch M5 is electrically connected first node A, and the of the 5th switch M5
The second pole that one pole is electrically connected the first low level signal input terminal VGL1, the 5th switch M5 is electrically connected the control of the 4th switch M4
End.The control terminal of 6th switch M6 is electrically connected first node A, and it is defeated that the first pole of the 6th switch M6 is electrically connected the second low level signal
Enter and hold VGL2, the second pole of the 6th switch M6 is electrically connected second node B.First reversed module 2 is used for the current potential of first node A
It carries out reversed and is transmitted to second node B.
Specifically, the impedance of third switch M3 is greater than the impedance of the 5th switch M5, impedance, that is, resistance.The control of 4th switch M4
End processed is controlled by the output signal of third switch M3 and the 5th switch M5, when third switch M3 and the 5th switch M5 are both turned on
When, high level and be electrically connected with the 5th switch M5 that the high level signal input terminal VGH being electrically connected with third switch M3 is exported
The first low level signal input terminal VGL1 input low level competed at the 4th switch M4.At this point, when third switchs
When the resistance of M3 is greater than the resistance of the 5th switch M5, the electric current of low level signal is greater than the electric current of high level signal, the 4th switch
The control terminal of M4 is controlled by low level signal and is disconnected.
Further, since third switch M3 and the 5th switch M5 are due to competing, current loss is larger, therefore is electrically connected
4th switch M4 and the 6th switch M6 is lost to reduce.
Fig. 4 is the structural schematic diagram of the provided in an embodiment of the present invention second reversed module, and the second reversed module 3 includes the 7th
Switch M7, the 8th switch M8, the 9th switch M9 and the tenth switch M10.The control terminal electrical connection high level letter of 7th switch M7
The first pole of number input terminal VGH, the 7th switch M7 are electrically connected high level signal input terminal VGH, and the second of the 7th switch M7 is extremely electric
Connect the control terminal of the 8th switch M8.The first pole of 8th switch M8 is electrically connected high level signal input terminal VGH, the 8th switch M8
The second pole be electrically connected third node C.The control terminal of 9th switch M9 is electrically connected second node B, the first pole of the 9th switch M9
The second pole for being electrically connected the first low level signal input terminal VGL1, the 9th switch M9 is electrically connected the control terminal of the 8th switch M8.The
The control terminal of ten switch M10 is electrically connected second node B, and the first pole of the tenth switch M10 is electrically connected the input of the second low level signal
VGL2 is held, the second pole of the tenth switch M10 is electrically connected third node C.
Specifically, the impedance of the 7th switch M7 is greater than the impedance of the 9th switch M9, impedance, that is, resistance.The control of 8th switch M8
End processed is controlled by the output signal of the 7th switch M7 and the 9th switch M9, when the 7th switch M3 and the 9th switch M9 is both turned on
When, high level and be electrically connected with the 9th switch M9 that the high level signal input terminal VGH being electrically connected with the 7th switch M7 is exported
The first low level signal input terminal VGL1 input low level competed at the 8th switch M8.At this point, when the 7th switch
When the resistance of M7 is greater than the resistance of the 9th switch M9, the electric current of low level signal is greater than the electric current of high level signal, the 8th switch
The control terminal of M8 is controlled by low level signal and is disconnected.
Further, since the 7th switch M7 and the 9th switch M9 are due to competing, current loss is larger, therefore is electrically connected
8th switch M8 and the tenth switch M10 is lost to reduce.
Fig. 5 is the structural schematic diagram of pull-up control module provided in an embodiment of the present invention, and pull-up control module 4 includes the tenth
One switch M11 and the 12nd switch M12.The control terminal of 11st switch M11 is electrically connected signal input part Cn-1, the 11st switch
The first pole of M11 is electrically connected second node B, and the second pole of the 11st switch is electrically connected fourth node D.12nd switch M12's
Control terminal is electrically connected third node C, and the of the electrical connection of the first pole second some B, the 12nd switch M12 of the 12nd switch M12
Two poles are electrically connected fourth node D.Pull-up control module 4 is used to control the current potential of fourth node D.
Fig. 6 is the structural schematic diagram of the first pull-up output module provided in an embodiment of the present invention, the first pull-up output module 5
Including the 15th switch M15, wherein the control terminal of the 15th switch M15 is electrically connected fourth node D, and the of the 15th switch M15
One pole is electrically connected second clock signal input part CK2, and the second pole of the 15th switch M15 is electrically connected the first signal output end Gn.
Specifically, the first signal output end Gn electric connection grid polar curve, the output for generating the first pull-up output module 5
Signal is transmitted to grid line.
Fig. 7 is the structural schematic diagram of the second pull-up output module provided in an embodiment of the present invention, the second pull-up output module 6
Including the 13rd switch M13.The control terminal of 13rd switch M13 is electrically connected fourth node D, the first pole of the 13rd switch M13
It is electrically connected second clock signal input part CK2, the second pole of the 13rd switch M13 is electrically connected second signal output end Cn.Second
Signal output end Cn is electrically connected the signal input part of next stage shift register, therefore the second pull-up output module 6 is for generating
Signal is simultaneously transmitted to next stage shift register.
Fig. 8 is the structural schematic diagram of the first drop-down output module provided in an embodiment of the present invention, the first drop-down output module 7
M16 is closed including sixteenmo.The control terminal that sixteenmo closes M16 is electrically connected third node C, and sixteenmo closes the first pole of M16
It is electrically connected the first low level signal input terminal VGL1, the second pole that sixteenmo closes M16 is electrically connected the first signal output end Gn.
Specifically, the first signal output end Gn electric connection grid polar curve, the output for generating the first drop-down output module 7
Signal is transmitted to grid line.
Fig. 9 is the structural schematic diagram of the second drop-down output module provided in an embodiment of the present invention, the second drop-down output module 8
Including the 14th switch M14.The control terminal of 14th switch M14 is electrically connected third node C, the first pole of the 14th switch M14
It is electrically connected the second pole electrical connection second signal output end Cn of the second low level signal input terminal VGL2, the 14th switch M14.The
Binary signal output end Cn is electrically connected the signal input part of next stage shift register, therefore the second drop-down output module 8 is for giving birth to
At signal and it is transmitted to next stage shift register.
The inside connection of all modules has been described in detail in Fig. 2 to Fig. 9, and Figure 10 is a kind of displacement provided in an embodiment of the present invention
The attachment structure schematic diagram of register.With Fig. 2 to Fig. 9, something in common repeats no more the specific connection type of the modules of Figure 10.
Shift register shown in Fig. 10 is all made of N-type oxide semiconductor tube, and first switch M1 to sixteenmo closes the control terminal of M16
When receiving high level signal, switch conduction.
Specifically, the first low level signal input terminal VGL1 has different electricity from the second low level signal input terminal VGL2
Ordinary mail number, it is defeated that the low level signal of the first low level signal input terminal VGL1 input is higher than the second low level signal input terminal VGL2
The low level signal entered.Since shift register tool is there are two low level signal input terminal, the first signal output end Gn with
The signal of second signal output end Cn output is different.
The present invention also provides a kind of driving circuits, and with reference to Figure 11, Figure 11 is a kind of driving electricity provided in an embodiment of the present invention
The structural schematic diagram on road, a kind of driving circuit of the present invention includes N grades of shift registers described above, and wherein N is positive integer.Tool
Body, by taking the shift register is made of N-type oxide semiconductor tube as an example.
The signal input part Cn-1 electrical connection i-stage of i+1 grade shift register (not shown) is moved in driving circuit
The second signal output end Cn of bit register (not shown), wherein i is the positive integer less than N.
Specifically, driving circuit further includes the first clock cable S1, second clock signal wire S2 and third clock letter
Number line S3.The pulse signal and third that pulse signal, the second clock signal wire S2 of first clock cable S1 output are exported
The pulse signal timing of clock cable S3 output is different.For example, the pulse letter of the first clock cable S1 output
Number failing edge it is Chong Die with the rising edge of pulse signal that second clock signal wire S2 is exported, second clock signal wire S2 output
The failing edge of pulse signal is Chong Die with the rising edge of pulse signal that third clock cable S3 is exported.
Specifically, the first clock signal input terminal CK1 of kth grade shift register is electrically connected the first clock cable S1,
Second clock signal input part CK2 is electrically connected third clock cable S3.At this point, the signal input part of kth grade shift register
Signal sequence of the signal sequence of Cn-1 input with second clock signal wire S2.First signal of kth grade shift register exports
End Gn output signal Gk is simultaneously transmitted to the grid line in display panel, for controlling the conducting and disconnection of grid；Second signal is defeated
Outlet Cn output signal Ck is simultaneously transmitted to+1 grade of shift register of kth.
The first clock signal input terminal CK1 of+1 grade of shift register of kth is electrically connected second clock signal wire S2, when second
Clock signal input part CK2 is electrically connected the first clock cable S1.Signal input part is electrically connected the second letter of kth grade shift register
Number output end Cn receives input signal Ck.The first signal output end Gn output signal Gk+1 of+1 grade of shift register of kth is simultaneously passed
The grid line in display panel is transported to, for controlling the conducting and disconnection of grid；Second signal output end Cn output signal Ck+1
And it is transmitted to+2 grades of shift registers of kth.
The first clock signal input terminal CK1 of+2 grades of shift registers of kth is electrically connected third clock cable S3, when second
Clock signal input part CK2 is electrically connected second clock signal wire S2.The signal input part Cn-1 of+2 grades of shift registers of kth is electrically connected
The second signal output end Cn of+1 grade of shift register of kth simultaneously receives input signal Ck+1.The first of+2 grades of shift registers of kth
Signal output end Gn output signal Gk+2 is simultaneously transmitted to the grid line in display panel, for controlling the conducting and disconnection of grid；
Second signal output end Cn output signal Ck+2 is simultaneously transmitted to next Ghandler motion bit register.
Figure 11 it is merely exemplary list kth grade shift register ,+1 grade of shift register of kth and+2 grades of kth displacement
Register, wherein k+1 is the positive integer less than N.But the embodiment of the present invention is without being limited thereto, any to be done based on the above embodiment
Deformation and extension belong to the scope of the present invention.
For the working principle and mode of clear interpretation shift register of the present invention and driving circuit, now in conjunction with Figure 10 to figure
12 illustrate, wherein Figure 12 is a kind of driving method for driving Figure 11 driving circuit provided in an embodiment of the present invention.In Figure 11
The specific connection structure of shift register is the same as shift register described in Figure 10.Specifically, the switch in shift register is N
Type oxide semiconductor tube.
Driving method shown in Figure 12 include first stage T1, second stage T2, phase III T3, fourth stage T4 and
5th stage T5.The first clock cable S1, second are electrically connected with the first clock signal input terminal CK1 of this grade of shift register
Clock signal input terminal CK2 is electrically connected for third clock cable S3.
During first stage T1, the first clock signal input terminal CK1 input high level of shift register of the present invention is believed
Number, second clock signal input part CK2 input low level signal, signal input part Cn-1 there is no signal to input.At this point, first opens
M1 conducting is closed, second switch M2 is disconnected, and the high level signal of high level signal input terminal VGH is transmitted to first node A.Third is opened
It closes M3 and is constantly on state, the 5th switch M5 is connected because first node A is in high level state.At this point, because third is opened
The impedance for closing M3 is greater than the impedance of the 5th switch M5, leads to the first low level letter that the 5th switch M5 is transmitted in electric current competition process
Number dominance, therefore the 4th switch M4 is disconnected and the 6th switch M6 conducting.It is defeated to receive the second low level signal by second node B at this time
The second low level signal for entering to hold VGL2 to input.First reversed module 2 realizes first node A and the signal of second node B is anti-
To.
Similarly, the structure & working mechanism of the second reversed module 3 and the first reversed module 2 is completely the same, therefore the first rank
During section T1, phase III C is high level signal.At this point, the 11st switch M11 is low level letter because of signal input part Cn-1
Number and disconnect, the 12nd switch M12 is connected because of the high level signal of third node C.Fourth node D receives second node at this time
The low level signal of B transmission.Similarly, the 13rd switch M13 and the 15th switch M15 because the low level signal of fourth node D it is disconnected
It opens, the 14th switch M14 and sixteenmo close M16 high pass due to the high level signal of third node C.The first signal is defeated at this time
Outlet Gn exports the first low level signal, and second signal output end Cn exports the second low level signal.
During second stage T2, the first clock signal input terminal CK1 input low level signal, the input of second clock signal
CK2 is held to maintain low level signal, signal input part Cn-1 has high level signal input at this time.First node A is because of second switch M2
First low level signal of conducting and reception the first low level signal input terminal VGL1 input.Second node B is because of the first reversed mould
The inversion principle of block 2 and be in high level state, third node C is in low level because of the inversion principle of the second reversed module 3
State.Operation principles are the same as first stage T1.
Because signal input part Cn-1 has high level signal input, therefore the 11st switch M11 is in the conductive state, and at this time
Four node D receive the high level signal of second node B transmission.13rd switch M13 and the 15th switch M15 are because of fourth node
The high level state of D and high pass.At this point, the first signal output end Gn and second clock signal output end Cn exports second clock
The low level signal of signal input part CK2 transmission.
During phase III T3, the first clock signal input terminal CK1 maintains low level signal, the input of second clock signal
CK2 input high level signal is held, signal input part Cn-1 becomes low level signal.At this point, first node A is maintained on last stage
Low level state, second node B maintain high level state because of the acting in opposition of the first reversed module 2, and third node C is because of second
The acting in opposition of reversed module 3 and maintain low level state.Fourth node because being high level state, discharge off way on last stage
Diameter, therefore the 13rd switch M13 is connected with the 15th switch M15 at this time, the first signal output end Gn and second signal output
Hold the high level signal of Cn transmission third clock signal input terminal CK3 transmission.Because of the 13rd switch M13 and the 15th switch M15
Component itself will form coupled capacitor, when coupled capacitor a pole be electrically connected output terminal potential get higher when, cause to couple
The node potential of another pole connection of capacitor is also got higher, and current potential is raised fourth node D due to the influence of coupled capacitor at this time.
During fourth stage T4, the first clock signal input terminal CK1 input high level signal, and second clock signal is defeated
Enter to hold CK2 input low level signal.First node A receives high level signal input terminal because of the conducting of first switch M1 at this time
The high level signal of VGH transmission.Second node B becomes low level state because of the acting in opposition of the first reversed module 2, and third
Node C maintains high level state because of the acting in opposition of the second reversed module 3.Fourth node D is due to the 12nd switch M12 is connected
Receive the low level signal of second node B.At this point, the first signal output end Gn and second signal output end Cn exports low level
Signal.
During 5th stage T5, the first clock signal input terminal CK1 input low level signal, the input of second clock signal
Hold input low level signal.At this point, first node A maintains high level state, and second node B maintains low level because of reversed module
State, third node C maintain high level state because of reversed module.Fourth node D becomes low because the 12nd switch M12 is opened
Level state.At this point, the first signal output end Gn and second signal output end Cn export low level signal.
In operation, oxide semiconductor tube can't be beaten above-mentioned shift register because threshold voltage is partially negative
It opens.At this point, shift register can normally carry out signal output under and backlight illumination condition bad in process conditions, it will not
Output multipulse signal is opened in non-opening state and influences to show.In addition, because of low level signal input terminal setting two, and the
One low level signal is different from the second low level signal, has distinguished output to the signal of grid and has been transmitted to next pole shift LD
The signal of device.
Figure 13 is a kind of schematic diagram of display panel provided in an embodiment of the present invention, which includes underlay substrate
10, underlay substrate 10 includes viewing area and the non-display area for surrounding viewing area.In addition, being provided with grid line 20 on underlay substrate 10
And data line 30.Grid line 20 and data line 30 are located at display area.The underlay substrate 10 further includes driving described above
Circuit GIP, driving circuit GIP are set to non-display area.Driving circuit GIP is made of above-mentioned shift register, grid line 20
The first signal output end being electrically connected in driving circuit GIP, i.e. Gn in Figure 11.Wherein, a grid line 20 is electrically connected level-one
First signal output end of shift register is electrically insulated with the first signal output end of other shift registers, realizes that one is a pair of
Answer connection relationship.
It is found by experimental verification, if the shift register driving circuit of prior art 7T2C will be exported normally, is needed
Guarantee that the threshold voltage of oxide semiconductor tube is greater than 0.5V；And a kind of shift register provided in an embodiment of the present invention and driving
Circuit, if needed normal output, it is only necessary to guarantee that the threshold voltage of oxide semiconductor tube is greater than -2V.That is,
In the case where threshold voltage is partially negative, the embodiment of the present invention also can be operated preferably.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (18)
1. a kind of shift register, including initial control module, the first reversed module, the second reversed module, pull-up control module,
First pull-up output module, second pull-up output module, first drop-down output module, second drop-down output module, first node,
Second node, third node and fourth node, in which:
It is the initial control module, the first reversed module, the second reversed module, the pull-up control module, described
First pull-up output module, the second pull-up output module, the first drop-down output module, the second drop-down output mould
Block includes at least one switch；
The initial control module is electrically connected signal input part, high level signal input terminal, the first clock signal input terminal, first
Low level signal input terminal, for generating control signal；
The first reversed module is electrically connected with the initial control module by the first node, the first reversed module
It is electrically connected the high level signal input terminal, the first low level signal input terminal and the second low level signal input terminal；
The second reversed module is electrically connected with the described first reversed module by the second node, the second reversed module
It is electrically connected the high level signal input terminal, the first low level signal input terminal and second low level signal input
End；
The pull-up control module is electrically connected with the described first reversed module by the second node, with the described second reversed mould
Block realizes by the third node and is electrically connected that the pull-up control module is electrically connected the signal input part, for controlling
State fourth node current potential；
The first pull-up output module is electrically connected with the pull-up control module by the fourth node, first pull-up
Output module is electrically connected second clock signal input part and the first signal output end；
The second pull-up output module is electrically connected with the first pull-up output module by the fourth node, and described second
It pulls up output module and is electrically connected the second clock signal input part and second signal output end, for being moved to described in next stage
Bit register input signal；
The first drop-down output module is electrically connected with the described second reversed module by third node realization, and described first
It pulls down output module and is electrically connected the first low level signal input terminal and first signal output end；
The second drop-down output module is electrically connected with the described second reversed module by third node realization, and described second
It pulls down output module and is electrically connected the second low level signal input terminal and the second signal output end, be used for next stage
The shift register input signal.
2. a kind of shift register as described in claim 1, the initial control module includes first switch and second switch,
Wherein,
The control terminal of the first switch is electrically connected first clock signal input terminal, and the first pole of the first switch is electrically connected
The high level signal input terminal is connect, the second pole of the first switch is electrically connected the first node；
The control terminal of the second switch is electrically connected the signal input part, the first pole electrical connection of the second switch described the
Second pole of one low level signal input terminal, the second switch is electrically connected the first node.
3. a kind of shift register as described in claim 1, the first reversed module include third switch, the 4th switch,
5th switch and the 6th switch, wherein
The control terminal of the third switch is electrically connected the high level signal input terminal, the first pole electrical connection of the third switch
The high level signal input terminal, the second pole of the third switch are electrically connected the control terminal of the 4th switch；
First pole of the 4th switch is electrically connected the high level signal input terminal, the second pole electrical connection of the 4th switch
The second node；
The control terminal of 5th switch is electrically connected the first node, the first pole electrical connection described first of the 5th switch
Low level signal input terminal, the second pole of the 5th switch are electrically connected the control terminal of the 4th switch；
The control terminal of 6th switch is electrically connected the first node, the first pole electrical connection described second of the 6th switch
Second pole of low level signal input terminal, the 6th switch is electrically connected the second node.
4. a kind of shift register as claimed in claim 3, wherein the impedance of the third switch is greater than the 5th switch
Impedance.
5. a kind of shift register as described in claim 1, the second reversed module is switched including the 7th, the 8th switchs,
9th switch and the tenth switch, wherein
The control terminal of 7th switch is electrically connected the high level signal input terminal, the first pole electrical connection of the 7th switch
The high level signal input terminal, the second pole of the 7th switch are electrically connected the control terminal of the 8th switch；
First pole of the 8th switch is electrically connected the high level signal input terminal, the second pole electrical connection of the 8th switch
The third node；
The control terminal of 9th switch is electrically connected the second node, the first pole electrical connection described first of the 9th switch
Low level signal input terminal, the second pole of the 9th switch are electrically connected the control terminal of the 8th switch；
The control terminal of tenth switch is electrically connected the second node, and the first pole of the tenth switch is electrically connected the second low electricity
Second pole of flat signal input part, the tenth switch is electrically connected the third node.
6. a kind of shift register as claimed in claim 5, wherein the impedance of the 7th switch is greater than the 9th switch
Impedance.
7. a kind of shift register as described in claim 1, the pull-up control module includes the 11st switch and the 12nd
Switch, wherein
The control terminal of 11st switch is electrically connected signal input part, the first pole electrical connection described the of the 11st switch
Second pole of two nodes, the 11st switch is electrically connected the fourth node；
The control terminal of 12nd switch is electrically connected the third node, the first pole electrical connection described second of the 12nd switch
Second pole of node, the 12nd switch is electrically connected the fourth node.
8. a kind of shift register as described in claim 1, the first pull-up output module includes the 15th switch,
In,
The control terminal of 15th switch is electrically connected the fourth node, the first pole electrical connection second of the 15th switch
Second pole of clock signal input terminal, the 15th switch is electrically connected the first signal output end.
9. a kind of shift register as described in claim 1, the second pull-up output module includes the 13rd switch,
In,
The control terminal of 13rd switch is electrically connected the fourth node, the first pole electrical connection second of the 13rd switch
Second pole of clock signal input terminal, the 13rd switch is electrically connected second signal output end.
10. a kind of shift register as described in claim 1, the first drop-down output module is closed including sixteenmo,
In,
The control terminal that the sixteenmo closes is electrically connected the third node, described in the first pole electrical connection that the sixteenmo closes
First low level signal input terminal, the second pole that the sixteenmo closes are electrically connected first signal output end.
11. a kind of shift register as described in claim 1, the second drop-down output module includes the 14th switch,
In,
The control terminal of 14th switch is electrically connected the third node, described in the first pole electrical connection of the 14th switch
Second pole of the second low level signal input terminal, the 14th switch is electrically connected the second signal output end.
12. a kind of shift register as described in claim 1, wherein the switch is N-type oxide semiconductor tube.
13. a kind of shift register as described in claim 1, wherein the level of the first low level signal input terminal is high
In the level of the second low level signal input terminal.
14. a kind of driving circuit, including a kind of N grades of such as described in any item shift registers of claim 1-13, N is positive whole
Number, wherein
The second signal output of shift register described in the signal input part electrical connection i-stage of the i+1 grade shift register
End, i are the positive integer less than N.
15. a kind of driving circuit as claimed in claim 14, further include the first clock cable, second clock signal wire and
Third clock cable, wherein
First clock signal input terminal of the kth grade shift register is electrically connected first clock cable, described
Second clock signal input part is electrically connected the third clock cable；
First clock signal input terminal of+1 grade of the kth shift register is electrically connected the second clock signal wire, institute
It states second clock signal input part and is electrically connected first clock cable；
First clock signal input terminal of+2 grades of the kth shift registers is electrically connected the third clock cable, institute
It states second clock signal input part and is electrically connected the second clock signal wire, k+1 is the positive integer less than N.
16. a kind of driving circuit as claimed in claim 15, wherein first clock cable, second clock letter
Number line and the third clock cable are electrically connected with IC chip, and Xiang Suoshu shift register successively sequentially provides arteries and veins
Rush signal.
17. a kind of driving circuit as claimed in claim 14, wherein the signal input part electricity of the 1st grade of shift register
Connect initial signal line；The initial signal line is electrically connected IC chip, transmits initial signal.
18. a kind of display panel, comprising:
Underlay substrate, the underlay substrate have viewing area and surround the non-display area of the viewing area；
Grid line is set to the viewing area；
Data line is set to the viewing area, intersects with grid line insulation to limit multiple pixel regions；
Such as the described in any item driving circuits of claim 14-17, it is set to the non-display area；
The grid line is electrically connected the first signal output end in the driving circuit.
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| CN108573679B (en) * | 2017-03-07 | 2019-12-24 | 昆山工研院新型平板显示技术中心有限公司 | Control signal driving circuit and driving method and pixel circuit driving method |
| CN106611582A (en) | 2017-03-08 | 2017-05-03 | 京东方科技集团股份有限公司 | Shift register, grid driving circuit, display panel and driving method |
| CN108510938B (en) * | 2018-04-20 | 2020-12-11 | 上海天马有机发光显示技术有限公司 | Shift register and driving method thereof, emission driving circuit and display device |
| CN108573673B (en) * | 2018-04-27 | 2021-07-30 | 厦门天马微电子有限公司 | Shift register, drive circuit and display device |
| CN110875001A (en) * | 2019-11-29 | 2020-03-10 | 京东方科技集团股份有限公司 | Test circuit, display substrate, display panel and test method |
| CN111754951A (en) * | 2020-07-15 | 2020-10-09 | 武汉华星光电技术有限公司 | MOG circuit and display panel |
| CN116597767B (en) * | 2023-07-14 | 2023-09-26 | 惠科股份有限公司 | GOA drive circuit, display panel and display device |
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