CN104637430A - Grid driving circuit and display device - Google Patents

Grid driving circuit and display device Download PDF

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Publication number
CN104637430A
CN104637430A CN201510002863.7A CN201510002863A CN104637430A CN 104637430 A CN104637430 A CN 104637430A CN 201510002863 A CN201510002863 A CN 201510002863A CN 104637430 A CN104637430 A CN 104637430A
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transistor
signal
drive unit
electrically connected
transmission
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CN104637430B (en
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张盛东
廖聪维
胡治晋
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Peking University Shenzhen Graduate School
InfoVision Optoelectronics Kunshan Co Ltd
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Peking University Shenzhen Graduate School
InfoVision Optoelectronics Kunshan Co Ltd
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Abstract

The embodiment of the invention discloses a grid driving circuit and a display device, and belongs to the technical field of display driving. The grid driving unit circuit comprises an input module, a positive feedback module, a driving module and a transmission module, wherein the output end of the input module is connected to a control node; the positive feedback module is used for pulling the output end up to a high level when the control node is at the high level; the driving module is used for applying a high level signal or a low level signal of a first clock signal to a grid scanning signal output end in response to the state of the control node when the control node is at the high level; when the control node is at a low level, a grid scanning signal output by the grid scanning signal output end is at the low level; the transmission module comprises a transmission signal output end for outputting a transmission signal, and is used for receiving the first clock signal. The grid driving unit circuit has the advantages of reasonable multiplexing of a circuit module, less charge leakage paths, simple circuit structure and high circuit reliability.

Description

Gate driver circuit and display device
Technical field
The present invention relates to display driver technical field, particularly a kind of gate driver circuit and display device.
Background technology
In recent years, narrow frame display technique development rapidly, and starts the flat panel display progressively becoming main flow.Especially for small-medium size thin film transistor (TFT) (Thin Film Transistor such as smart mobile phone and flat boards; TFT) display screen, the application of narrow frame display technique is more extensive.The core of narrow frame display technique is integrated raster data model (Gate-driver In Array the is called for short GIA) circuit design of TFT.After adopting GIA circuit, not only can reduce the frame size of display screen significantly, make whole display screen compacter, attractive in appearance, but also the quantity of ranks driving chip on display screen can be reduced, and corresponding connecting line quantity.In addition, the rear road packaging technology of display screen also can reduce.So the manufacturing cost of display screen can reduce greatly, the fraction defective occurred due to rear road module technique reduces, and the reliability of TFT display screen is also improved.In addition, because outconnector quantity reduces, lead spacing no longer seriously limits the realization of sharpness screen.
In recent years, the technology such as traditional a-Si or poly-Si are not suitable for realizing high resolving power TFT display screen due to mobility, reliability or homogeneity.And the IGZO-TFT emerged in large numbers in recent years (Indium Gallium Zinc Oxide-Thin Film Transistor, indium gallium zinc oxide-thin film transistor (TFT)) technology then because the outstanding advantage such as its higher mobility, characteristic are even and reliability is high, is particularly suitable for the realization of sharpness screen.
Due to the characteristic good of IGZO-TFT, the GIA circuit therefore based on IGZO-TFT should have higher performance compared to the GIA circuit of a-Si.But, and traditional Si base TFT (such as amorphous silicon or multi-crystal TFT) is different, the oxide TFT such as IGZO easily have negative threshold voltage, present the feature of depletion type work.Mainly because there is a large amount of Lacking oxygen, so electron concentration is large in the raceway groove of oxide TFT in this.Even if thus when grid-source bias voltage is 0V, the electric current flow through in oxide TFT is also very large.Accordingly, the grid-source voltage that apply to bear just can exhaust the charge carrier in raceway groove, state TFT being in close completely.When the oxide TFT such as IGZO have been applied in long negative gate bias, or under being in illumination condition, may excite in channels and produce more electronics, so the threshold voltage of IGZO-TFT is more negative.Although can make the IGZO-TFT of positive threshold voltage by adjusting process, these methods may damage the reliability of device.Therefore, the threshold voltage of the oxide TFT generally speaking made in existing technique is partially negative.
Due to deviated stress (the Negative bias tempreture stress that the threshold voltage of IGZO-TFT is partially negative, negative,, when traditional gate driver circuit scheme is for realizing the gate driver circuit of IGZO-TFT, easily there is the faults such as leakage current is large, bootstrapping is abnormal in the reason such as NBTS).Fig. 1 is the circuit diagram of the gate drive unit circuit of existing a kind of IGZO-TFT.Refer to Fig. 1, gate drive unit circuit comprises: transistor T10-T60, the grid of transistor T10 is electrically connected to Controlling vertex Q0, and the first end of transistor T10 exports transmission of signal VC [n], and second termination of transistor T10 receives the first clock signal clk 1.The grid of transistor T20 is electrically connected to Controlling vertex Q0, and the first end of transistor T20 exports grid level sweep signal VG [n], and second termination of transistor T20 receives the first clock signal clk 1.The grid of transistor T30 receives the transmission of signal VC [n+1] of the (n+1)th pole gate drive unit circuit output, and the first end of transistor T30 is electrically connected to the first voltage output end VLL0, and second end of transistor T30 exports transmission of signal VC [n].The grid of transistor T40 receives the gated sweep signal VG [n+1] of the (n+1)th pole gate drive unit circuit output, the first end of transistor T40 is electrically connected the second voltage output end VSS0, and second end of transistor T40 exports gated sweep signal VG [n].The grid of transistor T50 receives the 4th clock signal clk 4, and the first end of transistor T50 is electrically connected to second end of transistor T60, and second termination of transistor T50 receives the transmission of signal VC [n-1] of (n-1)th grade of gate drive unit circuit output.The grid of transistor T60 receives the 4th clock signal clk 4, and the first end of transistor T60 is electrically connected to Controlling vertex Q0, and second end of transistor T60 is electrically connected to the first end of transistor T50.But transistor T50 and T60 of above-mentioned gate drive unit circuit has serious electric leakage in the bootstrapping or downdraw process of transistor T20, makes Controlling vertex Q0 also cannot remain high level state.This seriously can increase the rising and falling time of the gated sweep signal VG [n] of output on the one hand, also level magnitudes and the phase place of the transmission of signal VC [n] of output can be affected on the other hand, cause the inefficacy of overall gate drive unit circuit, the faults such as leakage current is large, bootstrapping is abnormal easily occur.So, in order to adapt to the characteristic of IGZO-TFT, need new gate driver circuit architecture design badly.
Summary of the invention
The invention provides a kind of gate drive unit circuit, gate driver circuit and display device, available circuit leakage current be large to solve, the problem such as bootstrapping inefficacy.
Described technical scheme is as follows:
Embodiments provide a kind of gate driver circuit, comprise multiple gate drive unit circuit and clock cable, gate drive unit circuit comprises: load module, positive feedback module, driver module and transmission module, load module and positive feedback module, driver module are electrical connected, driver module and load module, positive feedback module and transmit module and be electrical connected, wherein, load module comprises the first signal receiving end (111) for receiving the first transmission of signal and output terminal (113), its output terminal (113) is electrically connected to Controlling vertex (Q), when the first transmission of signal is high level, load module is charged to Controlling vertex (Q) by its output terminal (113), when the first transmission of signal is low level, load module is discharged to Controlling vertex (Q) by its output terminal (113), positive feedback module, comprise the control end (122) and output terminal (123) that are electrically connected to Controlling vertex (Q), wherein output terminal (123) is electrically connected to first node (P), positive feedback module is used for when Controlling vertex (Q) is for high level, by its output terminal (123), first node P is pulled upward to high level, driver module, comprise the gated sweep signal output part (133) exporting gated sweep signal, for receiving the first clock signal receiving end (131) of the first clock signal, and be electrically connected to the control end (132) of the second Controlling vertex Q, the state of driver module response limiting node Q, when Controlling vertex Q is high level, the high level signal of the first clock signal or low level signal are applied to its gated sweep signal output part (133) by driver module, when Controlling vertex Q is low level, no matter the first clock signal is high level or low level, the gated sweep signal that the gated sweep signal output part (133) of driver module exports is low level, transmit module, comprise the transmission of signal output terminal (143) for exporting transmission of signal, for receiving the first clock signal receiving end (141) of the first clock signal, and be electrically connected to the control end (142) of Controlling vertex Q, when Controlling vertex Q is high level, transmit module and the high level signal of the first clock signal or low level signal are applied to its output terminal (143), when Controlling vertex Q is low level, no matter the first clock signal is high level or low level, the transmission of signal that the output terminal (143) transmitting module exports is low level.
In one embodiment of the invention, driver module comprises transistor seconds (T2) and the 4th transistor (T4), transmits module and comprises the first transistor (T1) and third transistor (T3); The grid of the first transistor (T1) is electrically connected to Controlling vertex (Q), and first end is electrically connected to transmission of signal output terminal (143), and the second end is for receiving the first clock signal; The grid of transistor seconds (T2) is electrically connected to Controlling vertex (Q), and first end is electrically connected to grid level sweep signal output terminal (133), and the second end is for receiving the first clock signal; The grid of third transistor (T3) receives the transmission of signal of (n+1)th grade of gate drive unit circuit output, first end is electrically connected the first voltage output end (VLL), and the second end is electrically connected to transmission of signal output terminal (143); The grid of the 4th transistor (T4) receives the gated sweep signal of (n+1)th grade of gate drive unit circuit output, first end is electrically connected the second voltage output end (VSS), second end is electrically connected to gated sweep signal output part (133), wherein, gate drive unit circuit is assumed to n-th grade of gate drive unit circuit.
In one embodiment of the invention, load module comprises the 5th transistor (T5) and the 6th transistor (T6), the grid of the 5th transistor (T5) receives the 4th clock signal, first end is electrically connected to first node (P), and the second termination receives the transmission of signal that the (n-1)th pole gate drive unit circuit exports; The grid of the 6th transistor (T6) receives the 4th clock signal, first end is electrically connected to Controlling vertex (Q), second end is electrically connected to first node (P), and wherein, gate drive unit circuit is assumed to n-th grade of gate drive unit circuit.
In one embodiment of the invention, positive feedback module comprises seven transistors (T7); The grid of the 7th transistor (T7) is electrically connected to Controlling vertex (Q), and first end is electrically connected to first node (P), and the second end is electrically connected tertiary voltage output terminal (VDD).
In one embodiment of the invention, positive feedback module comprises the 8th to the tenth transistor, the grid of the 8th transistor (T71) is electrically connected Controlling vertex (Q), first end is electrically connected the first end of the 9th transistor (T81) and the tenth transistor (T91), second end is electrically connected first node (P), second end of the 9th transistor (T81) and grid receive second clock signal, and the second end and the grid of the tenth transistor (T91) receive the first clock signal.
In one embodiment of the invention, load module comprises the 11 to the 14 transistor, the grid of the 11 transistor (T52) receives the 5th clock signal, first end is electrically connected to first node (P), second termination receives the transmission of signal that the (n-1)th pole gate drive unit circuit exports, the grid of the tenth two-transistor (T62) receives the 5th clock signal, first end is electrically connected to Controlling vertex (Q), second end is electrically connected first node (P), the grid of the 13 transistor (T72) is electrically connected the 3rd clock signal, first end is electrically connected to first node (P), second termination receives the transmission of signal that the (n+1)th pole gate drive unit circuit exports, the grid of the 14 transistor (T82) receives the 3rd clock signal, first end is electrically connected Controlling vertex (Q), second end is electrically connected first node (P), wherein, gate drive unit circuit is assumed to n-th grade of gate drive unit circuit.
In one embodiment of the invention, positive feedback module comprises the 15 transistor (T92), the grid of the 15 transistor (T92) is electrically connected Controlling vertex (Q), first end is electrically connected to first node (P), and the second end is electrically connected tertiary voltage output terminal (VDD).
In one embodiment of the invention, the magnitude of voltage that first voltage output end (VLL) and the second voltage output end (VSS) export meets following condition: VL=VSS1, VL-VLL1>VTH, VTH is the threshold voltage of transistor, VL is the low level value of the first clock signal, VLL1 is the magnitude of voltage that the first voltage output end exports, and VSS1 is the magnitude of voltage that the second voltage output end exports.
In one embodiment of the invention, also comprise electric capacity (C1), it is connected between Controlling vertex (Q) and gated sweep signal output part (133).
In one embodiment of the invention, transistor is IGZO thin film transistor (TFT).
Embodiments provide a kind of display device, it comprises: panel, and panel comprises the two-dimensional array be made up of multiple pixel, and many gate lines of first direction be connected with each pel array and a plurality of data lines of second direction; Data drive circuit, for providing picture signal to data line; Above-mentioned gate driver circuit, for providing gated sweep drive singal to gate line.
The beneficial effect that the technical scheme that the embodiment of the present invention provides is brought is:
The charge leakage in gate drive unit circuit bootstrapping stage is offset adaptively by introducing positive feedback module, so the partially negative bootstrapping Problem of Failure caused of transistor threshold voltage can be solved, concurrent multiplexing circuit module, circuit structure is simplified, charge leakage paths is less, and the reliability of circuit is higher.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to technological means of the present invention can be better understood, and can be implemented according to the content of instructions, and can become apparent to allow above and other object of the present invention, feature and advantage, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of the gate drive unit circuit of existing a kind of IGZO-TFT;
Fig. 2 is the circuit diagram of the gate drive unit circuit that first embodiment of the invention provides;
Fig. 3 is the sequential chart of the gate drive unit circuit of Fig. 2;
Fig. 4 is the sequential chart that the gate drive unit circuit of Fig. 2 removes positive feedback module;
Fig. 5 is the cascade block diagram of gate driver circuit in first embodiment of the invention;
Fig. 6 is the circuit diagram of the gate drive unit circuit that second embodiment of the invention provides;
Fig. 7 is the sequential chart of the gate drive unit circuit of Fig. 6;
Fig. 8 is the cascade block diagram of gate driver circuit in second embodiment of the invention;
Fig. 9 is the circuit diagram of the gate drive unit circuit that third embodiment of the invention provides;
Figure 10 is the sequential chart of gate drive unit circuit under forward scan pattern of Fig. 9;
Figure 11 is the sequential chart of gate drive unit circuit under reverse scan pattern of Fig. 9;
Figure 12 is the cascade block diagram of gate driver circuit in third embodiment of the invention.
Embodiment
Below by specific embodiment and be described in detail the present invention by reference to the accompanying drawings.
The electric leakage of gate drive unit circuit bootstrapping stage is caused in order to suppress the threshold voltage of IGZO TFT partially negative, the inventive concept that the embodiment of the present invention realizes gate drive unit circuit is: one side reasonably multiplex circuit module, thus reduces the path of charge leakage in gate drive unit circuit; On the other hand on the crucial branch road of charge leakage, introduce regenerative feedback loop, offset the impact of electric leakage.
First embodiment
Fig. 2 is the circuit diagram of the gate drive unit circuit that first embodiment of the invention provides.Refer to Fig. 2, gate drive unit circuit 5 comprises: load module 10, positive feedback module 20, driver module 30 and transmission module 40.Load module 10 and positive feedback module 20, driver module 30 are electrical connected, driver module 30 and load module 10, positive feedback module 20 and transmit module 40 and be electrical connected.
In embodiments of the present invention, all suppose that current Gate driver element circuit is the n-th pole gate drive unit circuit, VG [n], VC [n] represents the gated sweep signal that n-th grade of gate drive unit circuit exports and transmission of signal respectively, VG [n+1], VC [n+1] represents the gated sweep signal that next stage ((n+1)th grade) gate drive unit circuit of gate drive unit circuit at the corresponding levels exports and transmission of signal respectively, VG [n-1], VC [n-1] represents the gated sweep signal that upper level ((n-1)th grade) gate drive unit circuit of gate drive unit circuit at the corresponding levels exports and transmission of signal respectively.
Load module 10, comprise the first signal receiving end 111 for receiving the first transmission of signal VC [n-1], for receiving clock signal receiving end 112 and the output terminal 113 of the 4th clock signal clk 4, its output terminal 113 is connected to Controlling vertex Q, when the first transmission of signal VC [n-1] (being the transmission of signal VC [n-1] that (n-1)th grade of gate drive unit circuit exports) is high level, and the 4th clock signal clk 4 is when being also high level, driver module 10 will be charged by its output terminal 113 couples of Controlling vertex Q.In addition, after the gated sweep signal VG [n] that load module 10 also exports in the gate drive unit circuit at the corresponding levels and transmission of signal VC [n] that gate drive unit circuit at the corresponding levels exports becomes low level, transmission of signal VC [n-1] is low level, when 4th clock signal clk 4 is high level, discharged by its output terminal 113 couples of Controlling vertex Q.
Positive feedback module 20, comprise the control end 122 and output terminal 123 that are electrically connected to Controlling vertex Q, wherein output terminal 123 is connected to first node P, and positive feedback module is used for when Controlling vertex Q is high level, by its output terminal 123, first node P is pulled upward to high level.
Driver module 30, comprising the gated sweep signal output part 133 exporting gated sweep signal, for receiving the first clock signal receiving end 131 of the first clock signal clk 1, and being electrically connected to the control end 132 of Controlling vertex Q.The state of driver module 30 response limiting node Q, when Controlling vertex Q is high level, the high level signal of the first clock signal clk 1 or low level signal are applied to its gated sweep signal output part 133 by described driver module, when Controlling vertex Q is low level, no matter the first clock signal is high level or low level, and the gated sweep signal VG [n] that the gated sweep signal output part 133 of described driver module exports is low level.The gated sweep signal output part 133 of driver module 30 is for exporting gated sweep signal VG [n], wherein, every one-level gate drive unit circuit is coupled to a gate line corresponding with it, in this example, the gated sweep signal VG [n] that this gate drive unit circuit 5 exports is applied to the gate line corresponding with it.
The logic transmitting the logical and driver module 30 of module 40 is identical, that is, transmitting module 40, comprising the transmission of signal output terminal 143 for exporting transmission of signal, for receiving the first clock signal receiving end 141 of the first clock signal clk 1, and be electrically connected to the control end 142 of Controlling vertex Q.When Controlling vertex Q is high level, transmits module 40 and the high level signal of the first clock signal clk 1 or low level signal are applied to transmission of signal output terminal 143.When Controlling vertex Q is low level, no matter the first clock signal is high level or low level, and the transmission of signal VC [n] that the transmission of signal output terminal 143 transmitting module 40 exports is low level.Transmit module 40 and the difference part of driver module 30 and be to transmit the first signal receiving end that transmission of signal that module 40 exports is sent to the load module 10 of (n+1)th grade of gate drive unit circuit, the magnitude of voltage of transmission module 40 output signal is different from the magnitude of voltage that driver module 30 outputs signal.
Particularly, in a first embodiment, load module 10 comprises transistor T5 (the 5th transistor) and transistor T6 (the 6th transistor).Positive feedback module 20 comprises transistor T7 (the 7th transistor).Driver module 30 comprises transistor T2 (transistor seconds) and transistor T4 (the 4th transistor).Transmit module 40 and comprise transistor T1 (the first transistor) and transistor T3 (third transistor).
The grid of transistor T1 is electrically connected to Controlling vertex Q, and the first end of transistor T1 is electrically connected to transmission of signal output terminal 143, and for exporting transmission of signal VC [n], second termination of transistor T1 receives the first clock signal clk 1.The grid of transistor T2 is electrically connected to Controlling vertex Q, and the first end of transistor T2 is electrically connected to gated sweep signal output part 133, and for exporting grid level sweep signal VG [n], second termination of transistor T2 receives the first clock signal clk 1.The grid of transistor T3 receives the transmission of signal VC [n+1] of the (n+1)th pole gate drive unit circuit output, the first end of transistor T3 is electrically connected to voltage first voltage output end VLL, second end of transistor T3 is electrically connected to transmission of signal output terminal 143, for exporting transmission of signal VC [n].The grid of transistor T4 receives the gated sweep signal VG [n+1] of the (n+1)th pole gate drive unit circuit output, the first end of transistor T4 is electrically connected the second voltage output end VSS (), second end of transistor T4 is electrically connected to gated sweep signal output part 133, for exporting gated sweep signal VG [n].The grid of transistor T5 receives the 4th clock signal clk 4, and the first end of transistor T5 is electrically connected to first node P, and second termination of transistor T5 receives the transmission of signal VC [n-1] of (n-1)th grade of gate drive unit circuit output.The grid of transistor T6 receives the 4th clock signal clk 4, and the first end of transistor T6 is electrically connected to Controlling vertex Q, and second end of transistor T6 is electrically connected to node P.The first end of transistor T7 is electrically connected to node P, and second end of transistor T7 is electrically connected tertiary voltage output terminal VDD, and the grid of transistor T7 is electrically connected to Controlling vertex Q.
In the present embodiment, tertiary voltage output terminal VDD connects high level voltage source supply device, and therefore, when Controlling vertex Q is high level, positive feedback module 20 realizes the function by transistor T7, first node P being pulled to high level.
Preferably, in the present embodiment, can also shunt capacitance C1 between Controlling vertex Q and sweep signal output terminal 133.
The first end of above-mentioned transistor can be source electrode or the drain electrode of transistor, and correspondingly, the second end of above-mentioned transistor can be drain electrode or the source electrode of transistor.Fig. 3 is the sequential chart of the gate drive unit circuit of Fig. 2.This sequential chart is obtained by SPICE (Simulation program with integrated circuit emphasis, simulation of integrated circuit program) simulation.Curve 1P in Fig. 3, 1Q represents the voltage change curve of node P and Controlling vertex Q respectively, curve 1VC [n-1] in Fig. 3, 1VC [n+1] represents the transmission of signal voltage change curve that the (n-1)th pole and the (n+1)th pole gate drive unit circuit export respectively, curve 1CLK1 in Fig. 3, 1CLK4 represents first and the 4th change curve of clock signal respectively, curve 1VC [n] in Fig. 3 represents the transmission of signal voltage change curve that the n-th pole gate drive unit circuit exports, curve 1VG [n] in Fig. 3 represents the gated sweep signal voltage change curve that the n-th pole gate drive unit circuit exports, below with reference to Fig. 2 and Fig. 3, the course of work of the present embodiment gate drive unit circuit is described, the course of work of gate drive unit circuit comprises double teacher, i.e. charging stage P1, bootstrapping pull-up stage P2, drop-down stage P3, discharge regime P4, low level maintenance stage P5:
Charging stage P1:
At charging stage P1, the transmission of signal VC [n-1] of (n-1)th grade of gate drive unit circuit output is high level, clock signal clk 4 is also high level, therefore transistor T5 and T6 conducting, and Controlling vertex Q charging is pulled upward to high level current potential by its output terminal 113 by load module 10.So the equal conducting of transistor T1 of the transistor T2 of driver module 30 and transmission module 40.
For transistor T2, its grid potential is essentially pulled up to high level, and the current potential of source electrode and drain electrode due to clock signal clk 1 be low level, so the gate source capacitance of transistor T2, gate drain capacitor are all charged.And the gate source capacitance of transistor T2, the charging of gate drain capacitor constitute the condition precedent that bootstrapping occurs driving transistors T2 grid potential.Therefore, must the charge leakage of inhibitory control node Q or node P in the process of charging stage P1.
In the charging stage, because Controlling vertex Q is charged to high level state, transistor T7 also conducting in positive feedback module 20, so node P is coupled to the high level voltage value that tertiary voltage output terminal VDD exports, therefore positive feedback module 20 plays the effect of accelerated charging in the charging stage.
Bootstrapping pull-up stage P2:
At bootstrapping pull-up stage P2, transmission of signal VC [n-1] and the clock signal clk 4 of (n-1)th grade of gate drive unit circuit output all become low level state.Clock signal clk 1 then saltus step is high level state.Because transistor T2 is in conducting state at charging stage P1, and its gate drain capacitor has been charged to certain high-voltage value, according to principle of charge conservation on electric capacity, the moment at clock signal clk 1 voltage jump is kept constant by the magnitude of voltage on it.So the lifting along with clock signal clk 1 current potential be connected with second end of transistor T2 raises by the grid potential of transistor T2.Therefore transistor T2 is in heavily conducting state, the load charging of the gated sweep signal VG [n] exporting to n-th grade of gate drive unit circuit due to the first clock signal clk 1 promotes by the level value of the first end (as the gated sweep signal VG [n] that n-th grade of gate drive unit circuit exports, i.e. the gated sweep signal VG [n] of current Gate driver element circuit output) of transistor T2 step by step.Simultaneously also because the gate source capacitance of transistor T2 pipe is charged to certain high-voltage value at charging stage P1, therefore according to principle of charge conservation, the lifting that followed by the level value of the first end (gated sweep signal VG [n] output terminal as the n-th pole gate drive unit circuit) of transistor T2 further raises by the level value of the grid potential of transistor T2.Above-mentioned two processes in succession occurred are called as the bootstrapping pull-up stage.
Wherein, can the bootstrapping efficiency in the pull-up stage of booting and above-mentioned two bootstrapping pull-up actions in succession normally determine the rise time of the sweep waveform of gate drive unit circuit and the high value of sweep signal.It is worth mentioning that, in depletion type IGZO TFT situation, the bootstrapping pull-up stage may be destroyed because leakage current is comparatively large, thus the generation of interference sweep waveform.This threshold voltage mainly due to depletion type IGZO TFT is partially negative, even if therefore its grid-source voltage difference is 0, still may flow through the larger electric current of numerical value between its Drain-Source.In gate drive unit circuit as shown in Figure 2, Controlling vertex Q, the transmission of signal VC [n-1] that also namely the load module 10 that consists of transistor T5 and T6 uniquely of the grid of transistor T2 and (n-1)th grade of gate drive unit circuit export forms possible conductive path.Due in the bootstrapping pull-up stage, the transmission of signal VC [n-1] of (n-1)th grade of gate drive unit circuit output becomes low level, and therefore the majority charge leak path of the grid of transistor T2 is the load module 10 that transistor T5 and T6 is formed.
In the bootstrapping pull-up stage, positive feedback module 20 can play the effect of the charge leakage of offsetting load module 10.Because the grid of transistor T2 is lifted to high value, the therefore transistor T7 conducting of positive feedback module 20 by twice voltage bootstrapping in succession.Again because second end of transistor T7 is electrically connected to the tertiary voltage output terminal VDD of high level, therefore transistor T7 provides a charge compensation path, it can offset the loss of charge amount by load module 10, thus keeps the grid potential of transistor T2 to be steady state value in the bootstrapping pull-up stage.
In addition, be similar to the bootstrapping pull-up process of the gated sweep signal VG [n] that n-th grade of gate drive unit circuit exports, at bootstrapping pull-up stage P2, the transmission of signal VC [n] of n-th grade of gate drive unit circuit output is also essentially pulled up to high level by transistor T1.In order to promote the bootstrapping pull-up efficiency of the grid potential of transistor T2, can also preferably shunt capacitance C1 between the grid and source electrode of transistor T2, this is also conducive to the charge leakage suppressing load module 10 further.
Drop-down stage P3:
In the drop-down stage, load module 10 and positive feedback module 20 remain the state identical with the pull-up stage P2 that boots, and clock signal clk 1 saltus step is low level.Similarly due to principle of charge conservation, the grid of transistor T2 followed by clock signal clk 1 and saltus step is a comparatively low level value.But because load module 10 is still closed condition, and the value of the level value of the grid of transistor T2 and finish time charging stage is almost equal, still be high level state, so positive feedback module 20 also still remains conducting state, so transistor T2 still remains stronger conducting state.Therefore, the output terminal 133 (the gated sweep signal VG [n] as the n-th pole gate drive unit circuit exports) of gate drive unit circuit pulled down to the low level voltage equal with clock signal clk 1 by by transistor T2.Similarly, the transmission of signal VC [n] that the n-th pole gate drive unit circuit exports also pulled down to the low level voltage equal with clock signal clk 1 by transistor T1.
Discharge regime P4:
Discharge regime is also the key link of gate drive unit circuit.Before saltus step is high level to clock signal clk 1 again, if the current potential on transistor T2 grid does not pulled down to low level voltage, twice bootstrap process mentioned in the pull-up stage of so booting will repeatedly occur constantly.And in general, the normal output signal of every one-level gate drive unit circuit should be produce single sweep operation pulse in a frame time.Therefore, if discharge process is abnormal, then the output of single-stage gate drive unit circuit there will be multiple scanning impulse in a frame time, and display frame so will be caused abnormal.
At discharge regime P4, the transmission of signal VC [n-1] of clock signal clk 1 and (n-1)th grade of gate drive unit circuit output is still low level, and clock signal clk 4 becomes high level again, so transistor T5 and T6 conducting again.The grid of transistor T2 pulled down to low level voltage by load module 10, and correspondingly, the electric charge on the gate drain capacitor of transistor T2, gate source capacitance is released.So transistor T2 ends, even if clock signal clk 1 saltus step is once again high level, the gated sweep signal VG [n] of n-th grade of gate drive unit circuit output also will remain low level state.Similarly, at the end of discharge regime, transistor T1 also ends, thus guarantee can not because of the conducting of transistor T1, and clock signal clk 1 seals in and has influence on the low level state of the transmission of signal VC [n] that n-th grade of gate drive unit circuit exports.
Low level maintenance stage P5:
In the output signal of gate drive unit circuit signals such as (i.e.) the gated sweep signal VG [n] that exports of n-th grade of gate drive unit circuit and transmission of signal VC [n], most of the time, interior its should be maintained at low level state.But in the GIA circuit of depletion type IGZO TFT, the low level maintenance process of the gated sweep signal VG [n] having following reason that n-th grade of gate drive unit circuit is exported easily is interfered: one, owing to there is overlap capacitance between the gate-to-drain of IGZO TFT, gate-to-source, so by the coupling of the electric capacity between gate-to-drain, the grid potential of transistor T2 may be followed by clock signal clk 1 saltus step and changes.This may bring transistor T2 conducting.Two, the threshold voltage of depletion type IGZO TFT is partially negative, so transistor T2 conducting, or even the leakage current that faint conducting may cause numerical value considerable, the leakage current of transistor T2 may cause the gated sweep signal VG [n] of n-th grade of gate drive unit circuit output and the voltage of transmission of signal VC [n] to be lifted to high level voltage mistakenly.Three, compared to the situation of a-Si TFT, the mobility of depletion type IGZO TFT is higher, this will increase its leakage current further, more easily amplify clock feed-through effect to the impact of gate drive unit circuit output low level, even can cause the complete disorder of circuit output logic, more than be clock feed-through effect.
Exactly because above reason, in the GIA circuit design of depletion type IGZO TFT, another one key issue how to suppress clock feed-through effect, maintains the low level value of the gated sweep signal VG [n] of the n-th grade of gate drive unit circuit output exported.In this gate drive unit circuit shown in Fig. 2, multiplexing load module 10 suppresses clock feed-through effect.In the low level maintenance stage, the level due to Controlling vertex Q is low level, so the transistor T7 of positive feedback module 20 ends.So the leakage current of load module 10 starts to play a role by because of the closedown of positive feedback module 2.Although the leakage current of load module 10 is all undesirable in the processes such as aforementioned charging stage P1, bootstrapping pull-up stage P2, discharge regime P3, in the low level maintenance stage, this leakage current then just in time may be used for offset clock feedthrough effect.
When the leakage current of load module 10 does not play a role, due to clock feed-through effect, voltage jump amount (the Δ V on Controlling vertex Q q) following formula can be expressed as:
in formula, C gDthe gate drain capacitor sum of transistor T2 and T1, C qall electric capacity sums on Controlling vertex Q, V hand V lhigh level and the low level voltage value of clock signal clk 1 respectively.Because the threshold voltage of IGZO TFT is partially negative, therefore Δ V qcan easily exceed the threshold voltage value of transistor T2.
Under the leakage current effect of load module 10, Controlling vertex Q is connected to the low level voltage of the transmission of signal VC [n-1] that the (n-1)th pole gate drive unit circuit exports equivalently, so the current potential of Controlling vertex Q is clamped down on.Even if saltus step repeatedly occurs clock signal clk 1, the level of Controlling vertex Q still remains constant.So clock feed-through effect can be suppressed preferably.
It should be noted that, the above-mentioned course of work is also relevant with the level value of clock signal, power supply, transmission of signal etc.Here a kind of selection mode of level value is provided, such as: when the threshold V T H of IGZO TFT is-2V, the high value VH of clock signal clk 1, CLK4 is 15V, their low level value VL is-5V, the magnitude of voltage VSS1 of low level voltage output end VSS is-5, and the magnitude of voltage VLL1 of low level voltage output end VLL is-10V.So in the low level maintenance stage, transmission of signal VC [n] is held in-10V substantially, and the gated sweep signal VG [n] of output signal such as n-th grade of gate drive unit circuit output is held in-5V, and Controlling vertex Q is held in-10V.
Total voltage selection principle can be stated with following formula:
VL＝VSS1
VL-VLL1>VTH
Fig. 4 be the gate drive unit circuit of Fig. 2 remove suppress bootstrapping stage electric leakage positive feedback module 20 time sequential chart.Curve 11P in Fig. 4, 11Q represents the voltage change curve of node P and Controlling vertex Q respectively, curve 11VC [n-1] in Fig. 4, 11VC [n+1] represents the transmission of signal voltage change curve that the (n-1)th pole and the (n+1)th pole gate drive unit circuit export respectively, curve 11CLK1 in Fig. 4, 11CLK4 represents first and the 4th change curve of clock signal respectively, curve 11VC [n] in Fig. 4 represents the transmission of signal voltage change curve that the n-th pole gate drive unit circuit exports, curve 11VG [n] in Fig. 4 represents the gated sweep signal voltage change curve that n-th grade of gate drive unit circuit exports, comparison diagram 3 and Fig. 4 can find, after removing positive feedback module 20, due to the serious drain of load module 10, at bootstrapping stage P2, the current potential of node P is dragged down, Controlling vertex Q also cannot remain high level state simultaneously.So gated sweep signal VG [n] downdraw process of n-th grade of gate drive unit circuit output there occurs exception, cause its low level voltage value cannot reach the magnitude of voltage of voltage output end VSS output.
Fig. 5 is the gate driver circuit cascade block diagram of the formation of gate drive unit circuit in first embodiment of the invention.This gate driver circuit comprises the gate drive unit circuit as described in Figure 2 of N number of cascade, described N be greater than 1 integer, gate driver circuit also comprises four road clock cables (VA, VB, VC, VD).Wherein, the clock of the first clock cable VA, second clock signal wire VB, the 3rd clock cable VC, a 4th clock cable VD late phase place successively.
In this gate driver circuit, the first clock signal terminal 51CLK1, the second clock signal end 51CLK4 of first order gate drive unit circuit 501 connects the first clock cable VA, the 4th clock cable VD respectively to receive the first clock signal clk 1 and the 4th clock signal clk 4 (as shown in Figure 2).First signal receiving end 51VC [n-1] of first order gate drive unit circuit 501 connects initial transmission of signal output terminal STV, to receive transmission of signal.Three voltage receiving ends 51VLL, 51VSS, 51VDD of first order gate drive unit circuit 501 connect low level voltage output terminal VLL, VSS, high level voltage output terminal VDD respectively.Gated sweep signal output part 51VG [n], the transmission of signal output terminal 51VC [n] of first order gate drive unit circuit 501 export gated sweep signal VG [1] and transmission of signal VC [1] respectively.Gated sweep signal receiving end 51VG [n+1] and the transmission of signal receiving end 51VC [n+1] of first order gate drive unit circuit 501 are also connected gated sweep signal output part 52VG [n] and the transmission of signal output terminal 52VC [n] of second level gate drive unit circuit 502 respectively, to receive gated sweep signal VG [2] and the transmission of signal VC [2] of second level gate drive unit circuit 502 output.
First clock signal terminal 52CLK1 of second level gate drive unit circuit 502, second clock signal end 52CLK4 connect second clock signal wire VB, the first clock cable VA respectively to receive second clock signal and the first clock signal.First signal receiving end 52VC [n-1] of second level gate drive unit circuit 502 connects the output terminal 51VC [n] of first order gate drive unit circuit 501, to receive transmission of signal VC [1].Three voltage receiving ends 52VLL, 52VSS, 52VDD of second level gate drive unit circuit 502 connect low level voltage output terminal VLL, VSS, high level voltage output terminal VDD respectively.The gated sweep signal output part 52VG [n] of second level gate drive unit circuit 502 and transmission of signal output terminal 52VC [n] exports gated sweep signal VG [2] and transmission of signal VC [2] respectively.Gated sweep signal receiving end 52VG [n+1] and the transmission of signal receiving end 52VC [n+1] of second level gate drive unit circuit 502 are also connected gated sweep signal output part 53VG [n] and the transmission of signal output terminal 53VC [n] of third level gate drive unit circuit 503 respectively, to receive gated sweep signal VG [3] and the transmission of signal VC [3] of third level gate drive unit circuit 503 output.
First clock signal terminal 53CLK1 of third level gate drive unit circuit 503, second clock signal end 53CLK4 connect the 3rd clock cable VC, second clock signal wire VB respectively to receive the 3rd clock signal and second clock signal.First signal receiving end 53VC [n-1] of third level gate drive unit circuit 503 connects the output terminal 52VC [n] of second level gate drive unit circuit 502, to receive transmission of signal VC [2].Three voltage receiving ends 53VLL, 53VSS, 53VDD of third level gate drive unit circuit 503 connect low level voltage output terminal VLL, VSS, high level voltage output terminal VDD respectively.The gated sweep signal output part 53VG [n] of third level gate drive unit circuit 503 and transmission of signal output terminal 53VC [n] exports gated sweep signal VG [3] and transmission of signal VC [3] respectively.Gated sweep signal receiving end 53VG [n+1] and the transmission of signal receiving end 53VC [n+1] of third level gate drive unit circuit 503 are also connected gated sweep signal output part 54VG [n] and the transmission of signal output terminal 54VC [n] of fourth stage gate drive unit circuit 504 respectively, to receive gated sweep signal VG [4] and the transmission of signal VC [4] of fourth stage gate drive unit circuit 504 output.
First clock signal terminal 54CLK1 of fourth stage gate drive unit circuit 504, second clock signal end 54CLK4 connect the 4th clock cable VD, the 3rd clock cable VC respectively to receive the 4th clock signal and the 3rd clock signal.First signal receiving end 54VC [n-1] of fourth stage gate drive unit circuit 504 connects the output terminal 53VC [n] of third level gate drive unit circuit 503, to receive transmission of signal VC [3].Three voltage receiving ends 54VLL, 54VSS, 54VDD of fourth stage gate drive unit circuit 504 connect low level voltage output terminal VLL, VSS, high level voltage output terminal VDD respectively.Two gated sweep signal output part 54VG [n], the transmission of signal output terminal 54VC [n] of fourth stage gate drive unit circuit 504 export gated sweep signal VG [4] and transmission of signal VC [4] respectively.Gated sweep signal receiving end 54VG [n+1] and the transmission of signal receiving end 54VC [n+1] of fourth stage gate drive unit circuit 504 are also connected gated sweep signal output part and the transmission of signal output terminal (not shown) of level V gate drive unit circuit respectively, to receive gated sweep signal and the transmission of signal of the output of level V gate drive unit circuit.
In gate driver circuit, first to fourth gate drive unit circuit forms one-period, and subsequent gate driver element circuit cycles repeats the annexation of first to fourth grade of element circuit, does not repeat them here.
Second embodiment
Fig. 6 is the circuit diagram of the gate drive unit circuit that second embodiment of the invention provides.The difference of the present embodiment and Fig. 2 is: positive feedback module 22 comprises transistor T71 (the 8th transistor), T81 (the 9th transistor) and T91 (the tenth transistor).Wherein, the grid of transistor T71 (the 8th transistor) is electrically connected Controlling vertex Q, the first end of transistor T71 (the 8th transistor) is electrically connected the first end of transistor T81 (the 9th transistor) and T91, second end of transistor T71 (the 8th transistor) is electrically connected to first node P, second end of transistor T81 and grid receive second clock signal CLK2, and second end of transistor T91 and grid receive the first clock signal clk 1.So be between high period at clock signal clk 1 and CLK2, the first end of transistor T71 is coupled to high level voltage (such as, the high value VH of clock signal clk 1), thus avoids the charge leakage of Controlling vertex Q at bootstrapping stage.
Fig. 7 is the sequential chart of the gate drive unit circuit of Fig. 6.Curve 2P in Fig. 7, 2Q represents the voltage change curve of first node P and Controlling vertex Q respectively, curve 2VC [n-1] in Fig. 7, 2VC [n+1] represents the transmission of signal voltage change curve that the (n-1)th pole and the (n+1)th pole gate drive unit circuit export respectively, curve 2CLK1 in Fig. 7, 2CLK4 represents first and the 4th change curve of clock signal respectively, curve 2VC [n] in Fig. 7 represents the transmission of signal voltage change curve that the n-th pole gate drive unit circuit exports, curve 2VG [n] in Fig. 7 represents the gated sweep signal voltage change curve that the n-th pole gate drive unit circuit exports.The sequential of this figure is obtained by SPICE simulation, this demonstrate that the correctness of the gate drive unit circuit of the second embodiment.
Fig. 8 is the cascade block diagram of gate driver circuit in second embodiment of the invention.This gate driver circuit comprises the gate drive unit circuit as described in Figure 6 of N number of cascade, described N be greater than 1 integer, gate driver circuit also comprises four road clock cables (VA, VB, VC, VD).Wherein, the clock of the first clock cable VA, second clock signal wire VB, the 3rd clock cable VC, a 4th clock cable VD late phase place successively.
In this gate driver circuit, the first clock signal terminal 71CLK1 of first order gate drive unit circuit 701, second clock signal end 71CLK2, the 3rd clock signal terminal 71CLK4 connect the first clock cable VA, second clock signal wire VB, the 4th clock signal output terminal line respectively to receive the first clock signal, second clock signal and the 4th clock signal (as shown in Figure 6).First signal receiving end 71VC [n-1] of first order gate drive unit circuit 701 connects initial transmission of signal output terminal STV, to receive transmission of signal.Three voltage receiving ends 71VLL, 71VSS, 71VDD of first order gate drive unit circuit 701 connect low level voltage output terminal VLL, VSS, high level voltage output terminal VDD respectively.The gated sweep signal output part 71VG [n] of first order gate drive unit circuit 701 and transmission of signal output terminal 71VC [n] exports gated sweep signal VG [1] and transmission of signal VC [1] respectively.Gated sweep signal receiving end 71VG [n+1] and the transmission of signal receiving end 71VC [n+1] of first order gate drive unit circuit 701 are also connected gated sweep signal output part 72VG [n] and the transmission of signal output terminal 72VC [n] of second level gate drive unit circuit 702 respectively, to receive gated sweep signal VG [2] and the transmission of signal VC [2] of second level gate drive unit circuit 702 output.
First clock signal terminal 72CLK1 of second level gate drive unit circuit 702, second clock signal end 72CLK2, the 3rd clock signal terminal 72CLK4 connect second clock signal wire VB, the 3rd clock cable VC, the first clock cable VA respectively to receive second clock signal, the 3rd clock signal and the first clock signal.First signal receiving end 72VC [n-1] of second level gate drive unit circuit 702 connects the transmission of signal output terminal 71VC [n] of first order gate drive unit circuit 701, to receive transmission of signal VC [1].Three voltage receiving ends 72VLL, 72VSS, 72VDD of second level gate drive unit circuit 702 connect low level voltage output terminal VLL, VSS, high level voltage output terminal VDD respectively.The gated sweep signal output part 72VG [n] of second level gate drive unit circuit 702 and transmission of signal output terminal 72VC [n] exports gated sweep signal VG [2] and transmission of signal VC [2] respectively.Gated sweep signal receiving end 72VG [n+1] and the transmission of signal receiving end 72VC [n+1] of second level gate drive unit circuit 702 are also connected gated sweep signal output part 73VG [n] and the transmission of signal output terminal 73VC [n] of third level gate drive unit circuit 703 respectively, to receive gated sweep signal VG [3] and the transmission of signal VC [3] of third level gate drive unit circuit 703 output.
First clock signal terminal 73CLK1 of third level gate drive unit circuit 703, second clock signal end 73CLK2, the 3rd clock signal terminal 73CLK4 connect the 3rd clock cable VC, the first clock cable VA, second clock signal wire VB respectively to receive the 3rd clock signal, the first clock signal and second clock signal.First signal receiving end 73VC [n-1] of third level gate drive unit circuit 703 connects the transmission of signal output terminal 72VC [n] of second level gate drive unit circuit 702, to receive transmission of signal VC [2].Three voltage receiving ends 73VLL, 73VSS, 73VDD of third level gate drive unit circuit 703 connect low level voltage output terminal VLL, VSS, high level voltage output terminal VDD respectively.The gated sweep signal output part 73VG [n] of third level gate drive unit circuit 703 and transmission of signal output terminal 73VC [n] exports gated sweep signal VG [3] and transmission of signal VC [3] respectively.Gated sweep signal receiving end 73VG [n+1] and the transmission of signal receiving end 73VC [n+1] of third level gate drive unit circuit 703 are also connected gated sweep signal output part 74VG [n] and the transmission of signal output terminal 74VC [n] of fourth stage gate drive unit circuit 704 respectively, to receive gated sweep signal VG [4] and the transmission of signal VC [4] of fourth stage gate drive unit circuit 704 output.
First clock signal terminal 74CLK1 of fourth stage gate drive unit circuit 704, second clock signal end 74CLK2, the 3rd clock signal terminal 74CLK4 connect the 4th clock cable VD, the first clock cable VA, second clock signal wire VB respectively to receive the 4th clock signal, the first clock signal and second clock signal.First signal receiving end 74VC [n-1] of fourth stage gate drive unit circuit 704 connects the transmission of signal output terminal 73VC [n] of third level gate drive unit circuit 703, to receive transmission of signal VC [3].Three voltage receiving ends 74VLL, 74VSS, 74VDD of fourth stage gate drive unit circuit 704 connect low level voltage output terminal VLL, VSS, high level voltage output terminal VDD respectively.The gated sweep signal output part 74VG [n] of fourth stage gate drive unit circuit 704 and transmission of signal output terminal 74VC [n] exports gated sweep signal VG [4] and transmission of signal VC [4] respectively.Gated sweep signal receiving end 74VG [n+1] and the transmission of signal receiving end 74VC [n+1] of fourth stage gate drive unit circuit 704 are also connected gated sweep signal output part and the transmission of signal output terminal (not shown) of level V gate drive unit circuit respectively, to receive gated sweep signal and the transmission of signal of the output of level V gate drive unit circuit.
In this gate driver circuit, first to fourth gate drive unit circuit forms one-period, and subsequent gate driver element circuit cycles repeats the annexation of first to fourth grade of element circuit, does not repeat them here.
3rd embodiment
In the practical application of gate drive unit circuit, it is often needed to have bilateral scanning function, namely be not only can from the progression of little sequence number toward the progression transmission of large sequence number for the order of scanning impulse transmission, such as according to 1,2,3 ... transmit in turn to N-1, N level, can also from the progression of large sequence number toward the progression transmission of little sequence number, such as, according to N, N-1 ... 3,2,1 grades of ground transmit in turn.
Fig. 9 is the circuit diagram of the gate drive unit circuit that third embodiment of the invention provides, and it just possesses this bilateral scanning function.Its main difference is load module 13, it not only includes transistor T72 (the 13 transistor) and the T82 (the 14 transistor) of the 3rd clock signal clk 3 control, and including transistor T52 (the 11 transistor) and the T62 (the tenth two-transistor) of the 5th clock signal clk 5 control, positive feedback module 23 comprises transistor T92 (the 15 transistor).Gate drive unit circuit shown in remainder with Fig. 2 is identical, does not repeat them here.
Wherein, the grid of transistor T52 (the 11 transistor) receives the 5th clock signal clk 5, the first end of transistor T52 is electrically connected to first node P, and second termination of transistor T52 receives the transmission of signal VC [n-1] of (n-1)th grade of gate drive unit circuit output.The grid of transistor T62 (the tenth two-transistor) receives the 5th clock signal clk 5, and the first end of transistor T62 is electrically connected to Controlling vertex Q, and second end of transistor T62 is electrically connected to first node P.The grid of transistor T72 (the 13 transistor) receives the 3rd clock signal clk 3, the first end of transistor T72 is electrically connected to first node P, and second termination of transistor T72 receives the transmission of signal VC [n+1] of the (n+1)th pole gate drive unit circuit output.The grid of transistor T82 (the 14 transistor) receives the 3rd clock signal clk 3, and the first end of transistor T82 is electrically connected Controlling vertex Q, and second end of transistor T82 is electrically connected to first node P.The grid of transistor T92 (the 15 transistor) is electrically connected to Controlling vertex Q, and the first end of transistor T92 is electrically connected to first node P, and second end of transistor T92 is electrically connected voltage output end VDD.
Figure 10 is the sequential chart of gate drive unit circuit under forward scan pattern of Fig. 9, curve 3P in Figure 10, 3Q represents the voltage change curve of node P and Controlling vertex Q respectively, curve 3VC [n-1] in Figure 10, 3VC [n+1] represents the transmission of signal voltage change curve that the (n-1)th pole and the (n+1)th pole gate drive unit circuit export respectively, curve 3CLK1 in Figure 10, 3CLK3, 3CLK5 represents first respectively, 3rd, the change curve of the 5th clock signal, curve 3VC [n] in Figure 10 represents the transmission of signal voltage change curve that the n-th pole gate drive unit circuit exports, curve 3VG [n] in Figure 10 represents the gated sweep signal voltage change curve that the n-th pole gate drive unit circuit exports.Figure 11 is the sequential chart of gate drive unit circuit under reverse scan pattern of Fig. 9.Curve 33P in Figure 11, 33Q represents the voltage change curve of first node P and Controlling vertex Q respectively, curve 33VC [n-1] in Figure 11, 33VC [n+1] represents the transmission of signal voltage change curve that the (n-1)th pole and the (n+1)th pole gate drive unit circuit export respectively, curve 33CLK1 in Figure 11, 33CLK3, 33CLK5 represents first respectively, 3rd, the change curve of the 5th clock signal, curve 33VC [n] in Figure 11 represents the transmission of signal voltage change curve that the n-th pole gate drive unit circuit exports, curve 33VG [n] in Figure 11 represents the gated sweep signal voltage change curve that the n-th pole gate drive unit circuit exports.
Figure 12 is the cascade block diagram of gate driver circuit in third embodiment of the invention.This gate driver circuit comprises the gate drive unit circuit as described in Figure 9 of N number of cascade, described N be greater than 1 integer, gate driver circuit also comprises six road clock cables (VA, VB, VC, VD VE, VF).Wherein, the gate drive unit circuit shown in Fig. 9 at least needs six road clock signal clk 1 ~ CLK6.When forward scan, the phase place sequencing of this six tunnels clock signal is CLK1, CLK2, CLK3, CLK4, CLK5 and CLK6 successively.So transistor T5 and T6 that aforementioned charging stage P1 and discharge regime P2 is controlled by clock signal clk 5 realizes.Here, transistor T7 and T8 that sequential clock signal clk 3 relatively rearward controls assists the charge leakage suppressing bootstrapping stage.
On the other hand, when reverse scan, the phase place sequencing of this six tunnels clock signal is CLK6, CLK5, CLK4, CLK3, CLK2 and CLK1 successively.So transistor T7 and T8 that aforementioned charging stage P1 and discharge regime P2 is controlled by clock signal clk 3 realizes.Here, transistor T5 and T6 that sequential clock signal clk 5 relatively rearward controls plays the auxiliary charge leakage suppressing bootstrapping stage.
In this gate driver circuit, the first clock signal terminal 91CLK1 of first order gate drive unit circuit 901, second clock signal end 91CLK2, the 3rd clock signal terminal 91CLK4 connect the first clock cable VA, the 3rd clock cable VC, the 5th clock cable VE respectively to receive the first clock signal, the 3rd clock signal and the 5th clock signal (as shown in Figure 9).First signal receiving end 91VC [n-1] of first order gate drive unit circuit 901 connects initial transmission of signal output terminal STV, to receive transmission of signal.Three voltage receiving ends 91VLL, 91VSS, 91VDD of first order gate drive unit circuit 901 connect low level voltage output terminal VLL, VSS, high level voltage output terminal VDD respectively.The gated sweep signal output part 91VG [n] of first order gate drive unit circuit 901 and transmission of signal output terminal 91VC [n] exports gated sweep signal VG [1] and transmission of signal VC [1] respectively.Gated sweep signal receiving end 91VG [n+1] and the transmission of signal receiving end 91VC [n+1] of first order gate drive unit circuit 901 are also connected gated sweep signal output part 92VG [n] and the transmission of signal output terminal 92VC [n] of second level gate drive unit circuit 902 respectively, to receive gated sweep signal VG [2] and the transmission of signal VC [2] of second level gate drive unit circuit 902 output.
First clock signal terminal 92CLK1 of second level gate drive unit circuit 902, second clock signal end 72CLK2, the 3rd clock signal terminal 92CLK4 connect second clock signal wire VB, the 4th clock cable VD, the 6th clock cable VF respectively to receive second clock signal, the 4th clock signal and the 6th clock signal.First signal receiving end 92VC [n-1] of second level gate drive unit circuit 902 connects the transmission of signal output terminal 91VC [n] of first order gate drive unit circuit 901, to receive transmission of signal VC [1].Three voltage receiving ends 92VLL, 92VSS, 92VDD of second level gate drive unit circuit 902 connect low level voltage output terminal VLL, VSS, high level voltage output terminal VDD respectively.The gated sweep signal output part 92VG [n] of second level gate drive unit circuit 902 and transmission of signal output terminal 92VC [n] exports gated sweep signal VG [2] and transmission of signal VC [2] respectively.Gated sweep signal receiving end 92VG [n+1] and the transmission of signal receiving end 92VC [n+1] of second level gate drive unit circuit 902 are also connected gated sweep signal output part 93VG [n] and the transmission of signal output terminal 93VC [n] of third level gate drive unit circuit 903 respectively, to receive gated sweep signal VG [3] and the transmission of signal VC [3] of third level gate drive unit circuit 903 output.
First clock signal terminal 93CLK1 of third level gate drive unit circuit 903, second clock signal end 93CLK2, the 3rd clock signal terminal 93CLK4 connect the 3rd clock cable VC, the 5th clock cable VE, the first clock cable VA respectively to receive the 3rd clock signal, the 5th clock signal and the first clock signal.First signal receiving end 93VC [n-1] of third level gate drive unit circuit 903 connects the transmission of signal output terminal 92VC [n] of second level gate drive unit circuit 902, to receive transmission of signal VC [2].Three voltage receiving ends 93VLL, 93VSS, 93VDD of third level gate drive unit circuit 903 connect low level voltage output terminal VLL, VSS, high level voltage output terminal VDD respectively.The gated sweep signal output part 93VG [n] of third level gate drive unit circuit 903 and transmission of signal output terminal 93VC [n] exports gated sweep signal VG [3] and transmission of signal VC [3] respectively.Gated sweep signal receiving end 93VG [n+1] and the transmission of signal receiving end 93VC [n+1] of third level gate drive unit circuit 903 are also connected gated sweep signal output part 94VG [n] and the transmission of signal output terminal 94VC [n] of fourth stage gate drive unit circuit 904 respectively, to receive gated sweep signal VG [4] and the transmission of signal VC [4] of fourth stage gate drive unit circuit 904 output.
First clock signal terminal 94CLK1 of fourth stage gate drive unit circuit 904, second clock signal end 94CLK2, the 3rd clock signal terminal 94CLK4 connect the 4th clock cable VD, the 6th clock cable VA, second clock signal wire VB respectively to receive the 4th clock signal, the 6th clock signal and second clock signal.First signal receiving end 94VC [n-1] of fourth stage gate drive unit circuit 904 connects the transmission of signal output terminal 93VC [n] of third level gate drive unit circuit 903, to receive transmission of signal VC [3].Three voltage receiving ends 94VLL, 94VSS, 94VDD of fourth stage gate drive unit circuit 904 connect low level voltage output terminal VLL, VSS, high level voltage output terminal VDD respectively.The gated sweep signal output part 94VG [n] of fourth stage gate drive unit circuit 904 and transmission of signal output terminal 94VC [n] exports gated sweep signal VG [4] and transmission of signal VC [4] respectively.Gated sweep signal receiving end 94VG [n+1] and the transmission of signal receiving end 94VC [n+1] of fourth stage gate drive unit circuit 904 are also connected gated sweep signal output part and the transmission of signal output terminal (not shown) of level V gate drive unit circuit respectively, to receive gated sweep signal and the transmission of signal of the output of level V gate drive unit circuit.
In this gate driver circuit, first to fourth gate drive unit circuit forms one-period, and subsequent gate driver element circuit cycles repeats the annexation of first to fourth grade of element circuit, does not repeat them here.
4th embodiment
According to above embodiment, fourth embodiment of the invention also discloses a kind of display device, comprise: panel, panel comprises the two-dimensional array be made up of multiple pixel, and a plurality of data lines of first direction be connected with each pel array and many controlling grid scan lines of second direction; Data drive circuit, provides picture signal for giving described data line; Also comprising the gate driver circuit in embodiment one to three, providing gated sweep drive singal for giving described controlling grid scan line.Pel array is formed on a transparent substrate, and comprises many gate lines, data line and multiple switching transistor.Switching transistor is coupled respectively to each gate line and each data line.Data drive circuit and data line coupling, and provide data-signal to data line.Gate driver circuit and gate line coupling, and driving switch transistor.
In sum, the gate drive unit circuit of the embodiment of the present invention offsets the charge leakage in gate drive unit circuit bootstrapping stage adaptively by introducing positive feedback module, so can solve the partially negative bootstrapping Problem of Failure caused of depletion type IGZO TFT threshold voltage.
The charging and discharging of drive TFT grid capacitance can not only be completed by load module, but also can clock feed-through effect be suppressed.Multiplexing due to multinomial circuit function, the structure of circuit can greatly simplify, and the charge leakage path of drive TFT grid capacitance also can be reduced.
Also pass through low level voltage output terminal VSS and VLL that introducing two kinds of magnitudes of voltage do not wait, the output of gate drive unit circuit is simultaneously divided into two-way: gated sweep signal VG [n] and transmission of signal VC [n], so the drive TFT of gate drive unit circuit at different levels is offset to negative-grid-source voltage, again because the off-state current value of depletion type IGZO TFT is less, so the overall power value of gate drive unit circuit is low.
As shown in the 3rd embodiment, also expanded simply by load module and can realize bilateral scanning function, thus widened the range of application of this gate drive unit circuit, the peripheral signal collocation of convenient various display module.
The above, it is only preferred embodiment of the present invention, not any type of restriction is done to the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, when the technology contents of above-mentioned announcement can be utilized to make a little change, still belong to the scope of technical solution of the present invention.

Claims (11)

1. a gate driver circuit, comprise multiple gate drive unit circuit and clock cable, it is characterized in that, described gate drive unit circuit comprises: load module, positive feedback module, driver module and transmission module, described load module and described positive feedback module, driver module are electrical connected, described driver module and load module, positive feedback module and described transmission module are electrical connected, wherein;
Described load module, comprise the first signal receiving end (111) for receiving the first transmission of signal and output terminal (113), its output terminal (113) is electrically connected to Controlling vertex (Q), when the first transmission of signal is high level, described load module is charged to Controlling vertex (Q) by its output terminal (113), when the first transmission of signal is low level, described load module is discharged to Controlling vertex (Q) by its output terminal (113);
Described positive feedback module, comprise the control end (122) and output terminal (123) that are electrically connected to Controlling vertex (Q), wherein output terminal (123) is electrically connected to first node (P), described positive feedback module is used for when Controlling vertex (Q) is for high level, by its output terminal (123), first node (P) is pulled upward to high level;
Described driver module, comprise the gated sweep signal output part (133) exporting gated sweep signal, for receiving the first clock signal receiving end (131) of the first clock signal, and be electrically connected to the control end (132) of Controlling vertex (Q), the state of described driver module response limiting node (Q), when Controlling vertex (Q) is for high level, the high level signal of the first clock signal or low level signal are applied to its gated sweep signal output part (133) by described driver module, when Controlling vertex (Q) is for low level, no matter the first clock signal is high level or low level, the gated sweep signal that the gated sweep signal output part (133) of described driver module exports is low level,
Described transmission module, comprise the transmission of signal output terminal (143) for exporting transmission of signal, for receiving the first clock signal receiving end (141) of the first clock signal, and be electrically connected to the control end (142) of Controlling vertex Q, when Controlling vertex Q is high level, the high level signal of the first clock signal or low level signal are applied to its output terminal (143) by described transmission module, when Controlling vertex Q is low level, no matter the first clock signal is high level or low level, the transmission of signal that the output terminal (143) of described transmission module exports is low level.
2. gate driver circuit according to claim 1, it is characterized in that, described driver module comprises transistor seconds (T2) and the 4th transistor (T4), and described transmission module comprises the first transistor (T1) and third transistor (T3); The grid of described the first transistor (T1) is electrically connected to described Controlling vertex (Q), and first end is electrically connected to transmission of signal output terminal (143), and the second end is for receiving described first clock signal; The grid of described transistor seconds (T2) is electrically connected to Controlling vertex (Q), and first end is electrically connected to grid level sweep signal output terminal (133), and the second end is for receiving described first clock signal; The grid of described third transistor (T3) receives the transmission of signal of (n+1)th grade of gate drive unit circuit output, first end is electrically connected the first voltage output end (VLL), and the second end is electrically connected to transmission of signal output terminal (143); The grid of described 4th transistor (T4) receives the gated sweep signal of (n+1)th grade of gate drive unit circuit output, first end is electrically connected the second voltage output end (VSS), second end is electrically connected to gated sweep signal output part (133), wherein, described gate drive unit circuit is assumed to n-th grade of gate drive unit circuit.
3. gate driver circuit according to claim 2, it is characterized in that, described load module comprises the 5th transistor (T5) and the 6th transistor (T6), the grid of described 5th transistor (T5) receives the 4th clock signal, first end is electrically connected to first node (P), and the second termination receives the transmission of signal that the (n-1)th pole gate drive unit circuit exports; The grid of described 6th transistor (T6) receives the 4th clock signal, first end is electrically connected to Controlling vertex (Q), second end is electrically connected to described first node (P), wherein, described gate drive unit circuit is assumed to n-th grade of gate drive unit circuit.
4. gate driver circuit according to claim 3, is characterized in that, described positive feedback module comprises the 7th transistor (T7); The grid of described 7th transistor (T7) is electrically connected to Controlling vertex (Q), and first end is electrically connected to described first node (P), and the second end is electrically connected tertiary voltage output terminal (VDD).
5. gate driver circuit according to claim 3, it is characterized in that, described positive feedback module comprises the 8th to the tenth transistor, the grid of described 8th transistor (T71) is electrically connected Controlling vertex (Q), first end is electrically connected the first end of the 9th transistor (T81) and the tenth transistor (T91), second end is electrically connected first node (P), second end of described 9th transistor (T81) and grid receive second clock signal, and the second end of described tenth transistor (T91) and grid receive described first clock signal.
6. gate driver circuit according to claim 2, it is characterized in that, described load module comprises the 11 to the 14 transistor, the grid of described 11 transistor (T52) receives the 5th clock signal, first end is electrically connected to first node (P), second termination receives the transmission of signal that the (n-1)th pole gate drive unit circuit exports, the grid of described tenth two-transistor (T62) receives the 5th clock signal, first end is electrically connected to Controlling vertex (Q), second end is electrically connected described first node (P), the grid of described 13 transistor (T72) is electrically connected the 3rd clock signal, first end is electrically connected to first node (P), second termination receives the transmission of signal that the (n+1)th pole gate drive unit circuit exports, the grid of described 14 transistor (T82) receives the 3rd clock signal, first end is electrically connected Controlling vertex (Q), second end is electrically connected described first node (P), wherein, described gate drive unit circuit is assumed to n-th grade of gate drive unit circuit.
7. gate driver circuit according to claim 6, it is characterized in that, described positive feedback module comprises the 15 transistor (T92), the grid of described 15 transistor (T92) is electrically connected Controlling vertex (Q), first end is electrically connected to described first node (P), and the second end is electrically connected tertiary voltage output terminal (VDD).
8. gate driver circuit according to claim 2, it is characterized in that, the magnitude of voltage that first voltage output end (VLL) and the second voltage output end (VSS) export meets following condition: VL=VSS1, VL-VLL1>VTH, VTH is the threshold voltage of transistor, VL is the low level value of the first clock signal, and VLL1 is the magnitude of voltage that the first voltage output end exports, and VSS1 is the magnitude of voltage that the second voltage output end exports.
9. gate driver circuit according to claim 1, is characterized in that, also comprises electric capacity (C1), and it is connected between Controlling vertex (Q) and gated sweep signal output part (133).
10. the gate driver circuit according to any one of claim 2-7, is characterized in that, described transistor is IGZO thin film transistor (TFT).
11. 1 kinds of display device, it is characterized in that, it comprises:
Display panel, described panel comprises the two-dimensional array be made up of multiple pixel, and many gate lines of first direction be connected with each pel array and a plurality of data lines of second direction;
Data drive circuit, provides picture signal for giving described data line;
Gate driver circuit according to any one of claim 1-10, provides gated sweep drive singal for giving described gate line.
CN201510002863.7A 2015-01-05 2015-01-05 Gate driving circuit and display device Active CN104637430B (en)

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