CN106356300B - Semiconductor device, manufacturing method thereof and electronic device - Google Patents
Semiconductor device, manufacturing method thereof and electronic device Download PDFInfo
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- CN106356300B CN106356300B CN201510418474.2A CN201510418474A CN106356300B CN 106356300 B CN106356300 B CN 106356300B CN 201510418474 A CN201510418474 A CN 201510418474A CN 106356300 B CN106356300 B CN 106356300B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 82
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 239000010410 layer Substances 0.000 claims abstract description 176
- 238000000034 method Methods 0.000 claims abstract description 63
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 239000011248 coating agent Substances 0.000 claims abstract description 34
- 238000000576 coating method Methods 0.000 claims abstract description 34
- 230000008569 process Effects 0.000 claims abstract description 32
- 238000005530 etching Methods 0.000 claims abstract description 26
- 239000011229 interlayer Substances 0.000 claims abstract description 24
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 239000006117 anti-reflective coating Substances 0.000 claims description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 30
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 24
- 238000005498 polishing Methods 0.000 abstract description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 20
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 10
- 238000004140 cleaning Methods 0.000 description 10
- 239000007789 gas Substances 0.000 description 10
- 239000001257 hydrogen Substances 0.000 description 10
- 229910052739 hydrogen Inorganic materials 0.000 description 10
- 239000012212 insulator Substances 0.000 description 10
- 229910052757 nitrogen Inorganic materials 0.000 description 10
- 239000002002 slurry Substances 0.000 description 9
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 8
- 235000012431 wafers Nutrition 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
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- 229910052710 silicon Inorganic materials 0.000 description 4
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- 238000002230 thermal chemical vapour deposition Methods 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 2
- 235000011114 ammonium hydroxide Nutrition 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
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- 239000005368 silicate glass Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
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- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 238000007613 slurry method Methods 0.000 description 1
- 239000003826 tablet Substances 0.000 description 1
- 238000004627 transmission electron microscopy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Provided are a semiconductor device, a method of manufacturing the same, and an electronic apparatus, including: providing a front-end device comprising a semiconductor substrate, a first grid and a second grid, wherein the first grid and the second grid are positioned on the semiconductor substrate, the width of the first grid is greater than that of the second grid, and a hard mask layer is formed on the first grid; forming a bottom anti-reflection coating on the first grid, the second grid and the semiconductor substrate; forming a photoresist mask layer exposing the bottom anti-reflection coating above the first grid on the bottom anti-reflection coating; performing an etching process to remove the bottom anti-reflection coating which is not covered by the photoresist mask layer and the hard mask layer above the first grid; removing the bottom anti-reflection coating and the photoresist mask layer; and depositing an interlayer dielectric layer. According to the method disclosed by the invention, the residues and the disc-shaped depressions of silicon nitride on a wider grid electrode are effectively avoided, the surface flatness of the interlayer dielectric layer after polishing is good, and the performance and the yield of a device are improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.
Background
Chemical Mechanical Polishing (CMP), a process technique combining chemical etching and mechanical removal, is mainly used for planarization of silicon wafers in the semiconductor industry. The effect of surface planarization by CMP is greatly improved compared to the effect of surface planarization by conventional planarization techniques, and thus CMP is a critical planarization technique in the semiconductor industry.
Currently, when the size of a semiconductor device is reduced to 28nm or less, a Fixed Abrasive (FA) CMP is often used to fabricate an inter-layer dielectric (ILD) layer between polysilicon gates. The thickness of the hard mask silicon nitride on the wafer before the deposition of the interlevel dielectric layer shows different magnitudes at the 28nm scale, for example, after stress-induced proximity technology (SPT), with a thicker residual thickness of SiN on the wider gate region, with silicon nitride thicknesses between 0 and 400 angstroms as observed with Transmission Electron Microscopy (TEM). This difference cannot be solved by the abrasive slurry based ILDCMP. When the fixed-abrasive CMP is used for ILDCMP, the polishing is fixed and deformation of the polishing pad is not generated, so that good silicon nitride loading and dishing performance can be brought. However, as FA webs stop production, ILDCMP has to employ abrasive slurry-based ILDCMP. However, when ILDCMP is performed using a polishing slurry at a 28nm scale, problems such as silicon nitride residue, dishing and poor planarity of the surface of the interlayer dielectric layer occur, which may result in a decrease in yield and performance of the resulting semiconductor device.
fig. 1 shows a comparison of ILDCMP using the FA process and the abrasive slurry process. In the figure, a straight line indicates a dielectric layer at a certain time during CMP planarization, a dotted line indicates a planarized surface of ILDCMP by the FA method, and a straight line indicates a planarized surface of ILDCMP by the slurry method. As can be seen from the figure, after the Stress Proximity Technology (SPT), ILDCMP using the FA method can obtain less silicon nitride residue and smaller dishing, and has better planarity; the ILDCMP performed by using the polishing slurry has more silicon nitride residues and larger dishing, and a wider gate region has thicker SiN residue thickness and poorer flatness.
Therefore, it is necessary to provide a new method for manufacturing a semiconductor device to solve the deficiencies of the prior art.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a semiconductor device, a manufacturing method thereof and an electronic device.
according to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including:
Step S101: providing a front-end device comprising a semiconductor substrate, a first grid and a second grid, wherein the first grid and the second grid are positioned on the semiconductor substrate, the width of the first grid is greater than that of the second grid, and a hard mask layer is formed on the first grid;
Step S102: forming a bottom anti-reflection coating on the first grid, the second grid and the semiconductor substrate;
Step S103: forming a photoresist mask layer on the bottom anti-reflection coating, wherein the photoresist mask layer exposes the bottom anti-reflection coating above the first grid;
step S104: performing an etching process to remove the bottom anti-reflection coating which is not covered by the photoresist mask layer above the first grid and the hard mask layer above the first grid;
step S105: removing the bottom anti-reflection coating and the photoresist mask layer;
Step S106: and depositing an interlayer dielectric layer.
Optionally, the material of the plurality of gates is polysilicon.
Optionally, the heights of the plurality of gates are equal.
Optionally, the interlayer dielectric layer is an oxide layer.
Optionally, in step S103, the method for forming the photoresist mask layer includes: and forming photoresist covering the bottom anti-reflection coating, and carrying out exposure and development treatment on the photoresist.
Optionally, a width of a portion of the bottom anti-reflective coating above the hard mask layer, which is not covered by the photoresist mask layer, is smaller than a width of the hard mask layer.
optionally, the following steps are further included between step S105 and step S106: and performing a stress proximity technology step, and removing the residual part of the hard mask layer.
Optionally, a width of a portion of the bottom anti-reflective coating above the hard mask layer, which is not covered by the photoresist mask layer, is greater than a width of the hard mask layer.
Optionally, the following steps are further included between step S101 and step S102: and forming an etching stop layer on the first grid electrode, the second grid electrode and the semiconductor substrate.
Optionally, the etching stop layer is a contact hole etching stop layer.
Optionally, the etching in step S104 is stopped at the height of the surface of the etching stop layer above the second gate.
according to another aspect of the present invention, there is provided a semiconductor device manufactured according to the above method.
according to another aspect of the present invention, there is provided an electronic device including the semiconductor device described above.
According to the manufacturing method of the semiconductor device, the bottom anti-reflection coating and the photoresist mask layer are formed above the grid electrode before ILDCMP is carried out so as to etch the hard mask silicon nitride load on the wider grid electrode, so that the residue and the disc-shaped recess of the hard mask silicon nitride on the wider grid electrode are effectively avoided, the surface flatness of the polished interlayer dielectric layer is good, and the performance and the yield of the device are improved. The electronic device of the present invention has better performance because of using the semiconductor device.
drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
in the drawings:
FIG. 1 is a schematic diagram comparing ILDCMP using the FA process and the slurry process;
fig. 2A to 2F are cross-sectional views of structures formed at steps associated with a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 3A to 3F are cross-sectional views of structures formed in accordance with steps associated with a method of manufacturing a semiconductor device according to another embodiment of the present invention;
Fig. 4 is a schematic flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
in the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
it is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Embodiments of the present invention provide a method of manufacturing a semiconductor device. Next, the detailed steps of the method for manufacturing a semiconductor device according to the embodiment of the present invention are described with reference to fig. 2A to 2F, fig. 3A to 3F, and fig. 4. Fig. 2A to 2F are cross-sectional views of structures formed in steps related to a method of manufacturing a semiconductor device according to an embodiment of the present invention; fig. 3A to 3F are cross-sectional views of structures formed in accordance with steps associated with a method of manufacturing a semiconductor device according to another embodiment of the present invention; fig. 4 is a schematic flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
A method of manufacturing a semiconductor device according to an embodiment of the present invention includes the following steps.
Step A1: providing a front-end device comprising a semiconductor substrate 200 and a first gate 201 and a second gate 202 on the semiconductor substrate 200, wherein the width of the first gate 201 is greater than that of the second gate 202, and a silicon nitride hard mask layer 203 is formed on the first gate 201, as shown in fig. 2A.
In the present embodiment, a front-end device refers to a device in which certain components have been formed on a semiconductor substrate but manufacturing of the entire semiconductor device has not been completed finally. Of course, the specific structure of the front-end device is not limited to fig. 2A, and other components may be included.
The semiconductor substrate 200 may be at least one of a single-crystal silicon substrate, a silicon-on-insulator (SOI) substrate, a stacked-silicon-on-insulator (SSOI) substrate, a stacked-silicon-germanium-on-insulator (S-SiGeOI) substrate, a silicon-germanium-on-insulator (SiGeOI) substrate, and a germanium-on-insulator (GeOI) substrate. The material of the first gate 201 and the second gate 202 may be polysilicon, and a Low Pressure Chemical Vapor Deposition (LPCVD) process may be used to form the polysilicon. Illustratively, the height of the first gate 201 is equal to the height of the second gate 202. Although the number of the first gate 201 and the second gate 202 shown in fig. 2A is 1, the number of the first gate 201 and the second gate 202 is not limited to this, and may be set according to actual needs.
Step A2: a bottom anti-reflective coating 205 is formed on the first gate 201, the second gate 202 and the semiconductor substrate 200, as shown in fig. 2B.
Illustratively, a bottom anti-reflective coating 205 is formed covering the first gate 201, the second gate 202, and the semiconductor substrate 200. The bottom anti-reflection coating 205 is a layer that applies an anti-reflection coating on the bottom of the photoresist to reduce reflection of bottom light. The bottom anti-reflective coating 205 may be an organic anti-reflective coating, formed by spin coating on the surface of a silicon wafer, which relies on an organic layer to directly receive incident light; the BARC layer 205 may also be an inorganic ARC layer formed by PECVD on the surface of the silicon wafer, which functions by phase cancellation at specific wavelengths, and will not be described herein.
Step A3: a photoresist mask layer 206 exposing a portion of the bottom anti-reflective coating layer over the first silicon nitride hard mask layer 203 is formed on the bottom anti-reflective coating layer 205, as shown in fig. 2C.
the photoresist mask layer 206 is formed to cover the semiconductor substrate 200 except for the BARC layer over the SiN hard mask layer 203. The width of the bottom anti-reflective coating layer above the silicon nitride hard mask layer 203, which is not covered by the photoresist mask layer 206, is smaller than the width of the silicon nitride hard mask layer 203, so that the gate can be prevented from being damaged in the following etching step.
Illustratively, the method of forming the photoresist mask layer 206 may include: a photoresist covering the bottom anti-reflection coating 205 is formed, and the photoresist is exposed and developed.
Step A4: an etching process is performed to remove the BARC layer 205 and the SiN hard mask layer 203 over the first gate 201 without being covered by the photoresist mask layer 206, as shown in FIG. 2D.
illustratively, step a4 includes the steps of:
Step A41: etching the BARC layer 205, stopping on the SiN hard mask layer 203;
Step A42: the silicon nitride hard mask layer 203 is etched.
Step A5: the BARC layer 205 and the photoresist mask layer 206 are removed, as shown in FIG. 2E.
Illustratively, step a5 includes the steps of:
Step A51: using hydrogen (H)2) And nitrogen (N)2) Removing the bottom anti-reflection coating 205 and the photoresist mask layer 206 by the mixed gas;
Step A52: a wet clean process was performed using OZ and SC 1.
In step A51, use is made ofThe removal of the bottom anti-reflective coating 205 and the photoresist mask layer 206 by the mixed gas including hydrogen and nitrogen may be performed in a reaction chamber, and the process conditions may be set as follows: the Pressure (Pressure) is 500 Mt-2000 Mt; the Power (Power) is 1000 w-5000 w; the gas flow rate is 500sccm to 5000 sccm. Wherein, the volume ratio of the hydrogen and the nitrogen can be selected according to actual needs. Illustratively, the volume ratio of hydrogen to nitrogen may be 2: 1. In addition, the mixed gas used may include other suitable gases in addition to hydrogen and nitrogen. Oxygen (O) may also be used2) The BARC layer 205 and the photoresist mask layer 206 are removed. In this step, the specific reaction gas used is not limited.
In step a52, a wet cleaning process is performed using OZ and SC1 to remove residues and impurities resulting from the etching and removal process. The cleaning liquid adopted in the wet cleaning process can be a combination of ammonia water, a mixture of hydrogen peroxide and water (SC1) and ozone water (OZ). The concentrations of the individual cleaning liquids in the above combinations and other conditions required for the wet cleaning, such as temperature and treatment time, can be selected from concentration values and implementation conditions known to those skilled in the art and are not further described herein.
Step A6: a stress proximity technique step is performed while removing the remaining portions of the silicon nitride hard mask layer 203, as shown in fig. 2F.
Since the width of the portion of the BARC layer over the first gate 201 not covered by the photoresist mask layer 206 is less than the width of the SiN hard mask layer 203, the portion of the SiN hard mask layer 203 covered by the photoresist mask layer 206 over it has not been etched after the etching step is completed. By the stress proximity technique, a stress film (e.g., silicon nitride) is deposited, and when the film is removed, the remaining portion of the silicon nitride hard mask layer 203 is removed.
Step A7: an interlevel dielectric layer 207 is deposited.
An interlayer dielectric layer is deposited on the first gate 201, the second gate 202 and the semiconductor substrate 200. An interlayer dielectric layer 207 covers the semiconductor substrate 200 and fills a gap between the first gate 201 and the second gate 202. Optionally, a step of depositing a contact hole etching stop layer is further included before depositing the interlayer dielectric layer. The interlayer dielectric layer 207 may be an oxide layer, including a doped or undoped silicon oxide layer formed by a thermal chemical vapor deposition (thermal CVD) process or a High Density Plasma (HDP) process, such as Undoped Silicate Glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric layer 207 may also be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane (PTEOS) doped with phosphorus, or tetraethoxysilane (BTEOS) doped with boron, and may also be a High Aspect Ratio Process (HARP) layer and Tetraethylorthosilicate (TEOS) layer.
In the method for manufacturing the semiconductor device, the bottom anti-reflection coating and the photoresist mask layer are deposited before ILDCMP is performed to etch the silicon nitride hard mask layer on the wider grid, so that the silicon nitride residue and the dishing recess on the wider grid are effectively avoided, the surface flatness of the polished interlayer dielectric layer is good, the performance and the yield of the device are improved, and the CMP process window is properly maintained when the contact hole etching stop layer is subsequently deposited.
A method of manufacturing a semiconductor device according to another embodiment of the present invention includes the following steps.
Step B1: providing a front-end device comprising a semiconductor substrate 300 and a first gate 301 and a second gate 302 on the semiconductor substrate 300, wherein the width of the first gate 301 is greater than that of the second gate 302, and a silicon nitride hard mask layer 303 is formed on the first gate 301, as shown in fig. 3A.
In the present embodiment, a front-end device refers to a device in which certain components have been formed on a semiconductor substrate but manufacturing of the entire semiconductor device has not been completed finally. Of course, the specific structure of the front-end device is not limited to fig. 3A, and other components may be included.
The semiconductor substrate 300 may be at least one of a single crystal silicon substrate, a silicon-on-insulator (SOI) substrate, a stacked-silicon-on-insulator (SSOI) substrate, a stacked-silicon-germanium-on-insulator (S-SiGeOI) substrate, a silicon-germanium-on-insulator (SiGeOI) substrate, and a germanium-on-insulator (GeOI) substrate. The material of the first gate 301 and the second gate 302 may be polysilicon, and a Low Pressure Chemical Vapor Deposition (LPCVD) process may be used to form the polysilicon. Illustratively, the height of the first gate 301 is equal to the height of the second gate 302. Although the number of the first gate 301 and the second gate 302 shown in fig. 3A is 1, the number of the first gate 301 and the second gate 302 is not limited to this, and may be set according to actual needs.
Step B2: an etch stop layer 304 is formed on the first gate 301, the second gate 302, and the semiconductor substrate 300, as shown in fig. 3B.
illustratively, an etch stop layer 304 is formed to cover the first gate 301, the second gate 302 and the semiconductor substrate 300, the etch stop layer 304 is, for example, a contact hole etch stop layer (CESL), and a material of the etch stop layer 304 may be silicon nitride. The etch stop layer 304 may be formed by a suitable deposition process such as physical vapor deposition, chemical vapor deposition, or other nitridation processes, which are not described in detail herein.
step B3: a bottom anti-reflective coating 305 is formed on the etch stop layer 304 as shown in figure 3C.
Illustratively, a bottom anti-reflective coating 305 is formed covering the first gate 301, the second gate 302, and the semiconductor substrate 300. The bottom anti-reflection coating 305 is a layer that applies an anti-reflection coating on the bottom of the photoresist to reduce reflection of bottom light. The bottom anti-reflective coating 305 may be an organic anti-reflective coating formed by spin coating on the surface of a silicon wafer, which relies on an organic layer to directly receive incident light; the BARC layer 305 may also be an inorganic ARC layer formed by PECVD deposition on the wafer surface, which works by phase cancellation at specific wavelengths, and is not described in detail herein.
Step B4: a photoresist mask layer 306 exposing the bottom anti-reflective coating over the first gate 301 is formed on the bottom anti-reflective coating 305, as shown in fig. 3D.
The photoresist mask layer 306 is formed to cover other regions of the semiconductor substrate 300 except for the BARC layer over the first gate electrode 301. The width of the bottom anti-reflective coating layer above the silicon nitride hard mask layer 303, which is not covered by the photoresist mask layer 306, is greater than the width of the silicon nitride hard mask layer 303.
Illustratively, the method of forming the photoresist mask layer 306 may include: a photoresist covering the bottom anti-reflection coating 305 is formed, and the photoresist is exposed and developed.
Step B5: an etch is performed to remove the BARC layer 305, the etch stop layer 304, and the SiN hard mask layer 303 over the first gate 301 that are not covered by the photoresist mask layer 306, stopping at the height of the etch stop layer surface over the second gate 302, as shown in FIG. 3E.
Exemplarily, step B5 includes the steps of:
Step B51: etching the BARC layer 305 over the first gate 301 to stop at the height of the surface of the SiN mask layer 303;
Step B52: the silicon nitride mask layer 303 over the first gate 301 is etched to stop at the height of the etch stop layer surface over the second gate 302.
Step B6: the BARC layer 305 and the photoresist mask layer 306 are removed, as shown in FIG. 3F.
Exemplarily, step B6 includes the steps of:
Step B61: using hydrogen (H)2) And nitrogen (N)2) The bottom anti-reflection coating 305 and the photoresist mask layer 306 are removed by the mixed gas;
Step B62: a wet clean process was performed using OZ and SC 1.
In step B61, the removal of the bottom anti-reflective coating 305 and the photoresist mask layer 306 using a mixed gas comprising hydrogen and nitrogen can be performed in a reaction chamber, and the process conditions can be set as follows: the Pressure (Pressure) is 500 Mt-2000 Mt; the Power (Power) is 1000 w-5000 w; the gas flow rate is 500sccm to 5000 sccm. Wherein, the volume ratio of the hydrogen and the nitrogen can be selected according to actual needs. Display deviceIllustratively, the volume ratio of hydrogen to nitrogen may be 2: 1. In addition, the mixed gas used may include other suitable gases in addition to hydrogen and nitrogen. Oxygen (O) may also be used2) The BARC layer 305 and the photoresist mask layer 306 are removed. In this step, the specific reaction gas used is not limited.
In step B62, a wet cleaning process is performed using OZ and SC1 to remove residues and impurities generated by the etching process. The cleaning liquid adopted in the wet cleaning process can be a combination of ammonia water, a mixture of hydrogen peroxide and water (SC1) and ozone water (OZ). The concentrations of the individual cleaning liquids in the above combinations and other conditions required for the wet cleaning, such as temperature and treatment time, can be selected from concentration values and implementation conditions known to those skilled in the art and are not further described herein.
Step B7: an interlevel dielectric layer 307 is deposited.
An interlayer dielectric layer 307 is deposited on the first gate 301, the second gate 302 and the semiconductor substrate 300. An interlayer dielectric layer 307 covers the semiconductor substrate 300 and fills a gap between the first gate 301 and the second gate 302. Optionally, a step of depositing a contact hole etching stop layer is further included before depositing the interlayer dielectric layer. The interlayer dielectric layer 307 may be an oxide layer, including a doped or undoped silicon oxide layer formed by a thermal chemical vapor deposition (thermal CVD) process or a High Density Plasma (HDP) process, such as Undoped Silicate Glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric layer 307 may also be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane (PTEOS) doped with phosphorus, or tetraethoxysilane (BTEOS) doped with boron, and may also be a High Aspect Ratio Process (HARP) layer and Tetraethylorthosilicate (TEOS) layer.
In the method for manufacturing the semiconductor device of the embodiment, the etching stop layer, the bottom anti-reflection coating and the photoresist mask layer are deposited before the ILDCMP is performed to etch the silicon nitride hard mask layer on the wider gate, so that the silicon nitride residue and the dishing recess on the wider gate are effectively avoided, the surface flatness of the polished interlayer dielectric layer is good, the performance and the yield of the device are improved, and the method of the invention does not cause any damage and has enough etching windows.
according to the experimental result, after the load of the silicon nitride hard mask is removed, when the grinding slurry is used for carrying out ILDCMP, the dishing and the planarization performance are better than the results of the fixed grinding ILDCMP. The following table shows a comparison of results using a fixed-abrasive ILDCMP, an abrasive slurry-based ILDCMP (with a silicon nitride hard mask), and an abrasive slurry-based ILDCMP (without a silicon nitride hard mask) according to the present invention when the interlevel dielectric layer is a High Aspect Ratio Process (HARP) layer and a Tetraethylorthosilicate (TEOS) layer.
Fig. 4 is a schematic flow chart of a manufacturing method of a semiconductor device according to an embodiment of the present invention, which is used to briefly illustrate an exemplary flow of the manufacturing method.
Step S101: providing a front-end device comprising a semiconductor substrate, a first grid and a second grid, wherein the first grid and the second grid are positioned on the semiconductor substrate, the width of the first grid is greater than that of the second grid, and a hard mask layer is formed on the first grid;
Step S102: forming a bottom anti-reflection coating on the first grid, the second grid and the semiconductor substrate;
step S103: forming a photoresist mask layer on the bottom anti-reflection coating, wherein the photoresist mask layer exposes the bottom anti-reflection coating above the first grid;
Step S104: performing an etching process to remove the bottom anti-reflection coating which is not covered by the photoresist mask layer above the first grid and the hard mask layer above the first grid;
Step S105: removing the bottom anti-reflection coating and the photoresist mask layer;
Step S106: and depositing an interlayer dielectric layer.
Embodiments of the present invention provide a semiconductor device manufactured by the method for manufacturing a semiconductor device described in the above embodiments.
the semiconductor device prepared by the method provided by the embodiment of the invention has the advantages that no hard mask silicon nitride residue is left above the grid electrode, the surface flatness of the interlayer dielectric layer is good, and the problem of dishing is avoided, so that the semiconductor device has excellent performance and yield.
An embodiment of the present invention provides an electronic device including an electronic component and a semiconductor device electrically connected to the electronic component. Wherein the semiconductor device is the above semiconductor device.
the electronic device of this embodiment may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice pen, an MP3, an MP4, and a PSP, and may also be any intermediate product including the semiconductor device. The electronic component may be any feasible component, and is not limited herein.
The electronic device of the embodiment of the invention has better performance due to the use of the semiconductor device.
the present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (9)
1. a method of manufacturing a semiconductor device, the method comprising:
Step S101: providing a front-end device comprising a semiconductor substrate, a first grid and a second grid, wherein the first grid and the second grid are positioned on the semiconductor substrate, the width of the first grid is greater than that of the second grid, and a hard mask layer is formed on the first grid;
step S102: forming a bottom anti-reflection coating on the first grid, the second grid and the semiconductor substrate;
Step S103: forming a photoresist mask layer on the bottom anti-reflection coating, wherein the photoresist mask layer exposes the bottom anti-reflection coating above the first grid;
Step S104: performing an etching process to remove the bottom anti-reflection coating which is not covered by the photoresist mask layer above the first grid and the hard mask layer above the first grid;
Step S105: removing the bottom anti-reflection coating and the photoresist mask layer;
step S106: depositing an interlayer dielectric layer;
Step S107: performing a CMP process to planarize the interlayer dielectric layer; wherein the content of the first and second substances,
when the size of the bottom anti-reflection coating exposed by the photoresist mask layer in the step S103 is smaller than the size of the hard mask layer, a stress approach technical step is further performed after the step S105 is performed and before the step S106 is performed, so as to remove the residual part of the hard mask layer;
When the size of the bottom anti-reflective coating exposed by the photoresist mask layer in the step S103 is larger than the size of the hard mask layer, the method further includes the following steps between the step S101 and the step S102: and forming an etching stop layer on the first grid electrode, the second grid electrode and the semiconductor substrate.
2. the method for manufacturing a semiconductor device according to claim 1, wherein a material of the first gate and the second gate is polysilicon.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the first gate and the second gate are equal in height.
4. The method for manufacturing a semiconductor device according to claim 1, wherein the interlayer dielectric layer is an oxide layer.
5. The method for manufacturing a semiconductor device according to claim 1, wherein in step S103, the method for forming the photoresist mask layer comprises: and forming photoresist covering the bottom anti-reflection coating, and carrying out exposure and development treatment on the photoresist.
6. the method for manufacturing a semiconductor device according to claim 1, wherein the etching stopper layer is a contact hole etching stopper layer.
7. The method for manufacturing a semiconductor device according to claim 6, wherein the etching in step S104 is stopped at a height of an etching stopper surface above the second gate electrode.
8. a semiconductor device made according to the method of any one of claims 1-7.
9. An electronic device comprising the semiconductor device according to claim 8.
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| US6924220B1 (en) * | 2001-08-03 | 2005-08-02 | Advanced Micro Devices, Inc. | Self-aligned gate formation using polysilicon polish with peripheral protective layer |
| CN100373593C (en) * | 2004-07-12 | 2008-03-05 | 海力士半导体有限公司 | Method of manufacturing flash memory device |
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| KR20010096346A (en) * | 2000-04-18 | 2001-11-07 | 박종섭 | Method For Polishing The Semiconductor Device Using The Buffer Oxide Layer |
| KR100414731B1 (en) * | 2001-06-30 | 2004-01-13 | 주식회사 하이닉스반도체 | A method for forming a contact plug of a semiconductor device |
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| US6924220B1 (en) * | 2001-08-03 | 2005-08-02 | Advanced Micro Devices, Inc. | Self-aligned gate formation using polysilicon polish with peripheral protective layer |
| CN100373593C (en) * | 2004-07-12 | 2008-03-05 | 海力士半导体有限公司 | Method of manufacturing flash memory device |
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