CN106328694B - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
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- CN106328694B CN106328694B CN201510373552.1A CN201510373552A CN106328694B CN 106328694 B CN106328694 B CN 106328694B CN 201510373552 A CN201510373552 A CN 201510373552A CN 106328694 B CN106328694 B CN 106328694B
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of forming method of semiconductor structure, it include: offer substrate, the substrate surface has fin and separation layer, and the separation layer is located at the partial sidewall surface of the fin, the surface of the separation layer is lower than the top surface of the fin, and the side wall and top surface of the fin have boundary layer；The boundary layer is removed using dry etch process, the gas of the dry etch process includes fluoro-gas；After removing the boundary layer, side wall and top surface to the fin carry out process of surface treatment, and the gas of the surface treatment includes nitrogenous gas.The forming method of the semiconductor structure can remove the remaining impurity of fin portion surface, make to be formed by fin formula field effect transistor performance improvement.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of forming methods of semiconductor structure.
Background technique
With the rapid development of semiconductor processing technology, semiconductor devices is towards higher component density and higher
The direction of integrated level is developed.Transistor is just being widely used at present as most basic semiconductor devices, therefore with semiconductor
The raising of the component density and integrated level of device, the grid size of planar transistor is also shorter and shorter, traditional planar transistor
It dies down to the control ability of channel current, generates short-channel effect, generate leakage current, the final electrical property for influencing semiconductor devices
Energy.
In order to overcome the short-channel effect of transistor, inhibit leakage current, the prior art proposes fin formula field effect transistor
(Fin FET), fin formula field effect transistor are a kind of common multi-gate devices.The structure of fin formula field effect transistor includes: position
In the fin and dielectric layer of semiconductor substrate surface, the side wall of fin described in the dielectric layer covering part, and dielectric layer surface
Lower than at the top of fin；Gate structure positioned at the top and sidewall surfaces of dielectric layer surface and fin；Positioned at the grid knot
Source region and drain region in the fin of structure two sides.
However, the performance of the formed fin formula field effect transistor of the prior art is bad, reliability is poor.
Summary of the invention
Problems solved by the invention is to provide a kind of forming method of semiconductor structure, and removal fin portion surface is remaining miscellaneous
Matter makes the performance improvement for being formed by fin field effect pipe.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, comprising: substrate is provided, it is described
Substrate surface has fin and separation layer, and the separation layer is located at the partial sidewall surface of the fin, the table of the separation layer
Face is lower than the top surface of the fin, and the side wall and top surface of the fin have boundary layer；Using dry etch process
The boundary layer is removed, the gas of the dry etch process includes fluoro-gas；After removing the boundary layer, to described
The side wall and top surface of fin carry out process of surface treatment, and the gas of the surface treatment includes nitrogenous gas.
Optionally, the material of the boundary layer is silica；The boundary layer with a thickness of 10 angstroms~30 angstroms.
Optionally, the dry etch process for removing the boundary layer is SiCoNi etching technics.
Optionally, the parameter of the SiCoNi etching technics includes: power 10W~100W, and frequency is less than 100kHz, etching
Temperature is 40 degrees Celsius~80 degrees Celsius, and pressure is 0.5 support~50 supports, and etching gas includes NH3、NF3, He, wherein NH3Stream
Amount is 0sccm~500sccm, NF3Flow be 20sccm~200sccm, the flow of He is 400sccm~1200sccm, NF3
With NH3Flow-rate ratio be 1:20~5:1.
Optionally, the step of process of surface treatment include: to the side wall and top surface of the fin carry out etc. from
Daughter treatment process.
Optionally, it includes N that the parameter of the plasma-treating technology, which includes: gas,2O、N2, one of NO or a variety of,
Power is 300 watts~1500 watts, and pressure is 10 millitorrs~100 millitorrs, and flow is 20sccm~~300sccm.
Optionally, when the gas of the plasma-treating technology includes N2When O or NO, the plasma-treating technology
The side wall and top surface exposed in the fin forms oxide layer.
Optionally, the step of process of surface treatment further include: after the plasma-treating technology, use
Wet processing process removes the oxide layer.
Optionally, the liquid of the wet processing process is hydrofluoric acid solution；Water and hydrofluoric acid in the hydrofluoric acid solution
Volume ratio be 20:1~~200:1.
Optionally, the thickness of the oxide layer is less than the thickness of the boundary layer；The oxide layer with a thickness of 5 angstroms~10
Angstrom.
Optionally, further includes: after the process of surface treatment, prerinse is carried out to the separation layer and fin portion surface
Technique.
Optionally, after forming the boundary layer, before removing the boundary layer, ion note is carried out in the fin
Enter technique；Using the ion injected in annealing process activation fin.
Optionally, the ion implantation technology carried out in the fin include channel region stop injection, threshold value adjust injection,
One of well region injection is a variety of.
Optionally, the forming step of the substrate and fin includes: offer semiconductor base；In the semiconductor base table
Face forms mask layer, and the mask layer covering needs to form the semiconductor substrate surface of fin；Using the mask layer as exposure mask, carve
The semiconductor base is lost, forms groove in the semiconductor base, forms substrate and the fin positioned at substrate surface.
Optionally, the forming step of the separation layer includes: to form isolation film in the substrate and fin portion surface；Planarization
The isolation film is until the top surface for exposing the fin；After planarizing the isolation film, it is etched back to described
Isolation film exposes part fin sidewall surfaces, forms separation layer.
Optionally, after the process of surface treatment, in the insulation surface and the side wall and top table of fin
Face is developed across the gate structure of the fin；Source region and drain region are formed in the fin of the gate structure two sides.
Optionally, the gate structure include positioned at insulation surface and fin side wall and top surface grid oxide layer,
Grid layer positioned at grid oxygen layer surface and the side wall positioned at grid oxide layer and grid layer sidewall surfaces.
Optionally, the forming step of the grid oxide layer and grid layer includes: the side in the insulation surface and fin
Wall and top surface form grid oxygen film；Gate electrode film is formed in the grid oxygen film surface；It is formed graphically in the grid film surface
Layer, the patterned layer covering need to form the corresponding region of grid layer；Using the patterned layer as exposure mask, the grid is etched
Film and grid oxygen film form grid oxide layer and grid layer until exposing the separation layer and fin portion surface.
Optionally, the material of the grid oxide layer is silica；The material of the grid layer is polysilicon.
Optionally, after forming source region and drain region, further includes: the insulation surface and fin side wall and
Top surface forms dielectric layer, and the dielectric layer is flushed with the top surface of gate structure；The grid layer is removed, is being given an account of
Opening is formed in matter layer；High-k gate dielectric layer is formed in the opening；It is formed in the high-k gate dielectric layer surface and fills full institute
State the metal gate of opening.
Compared with prior art, technical solution of the present invention has the advantage that
In method of the invention, the boundary layer is used for the protection fin when carrying out ion implanting to the fin and exposes
Side wall and top surface.The boundary layer can be removed by the dry etch process, however due to the dry etching
The etching gas of technique includes fluoro-gas, and the fluoro-gas is easy after the etching technics, is easy in the fin
Remained on surface fluorine ion, and the fluorine ion easily causes the reunion of other etch by-products, causes the rough surface of fin.Cause
This needs to remove the fluorine ion of fin side wall and top surface by process of surface treatment after removing the boundary layer；Institute
The gas for stating process of surface treatment includes nitrogenous gas, and the nitrogenous gas can interrupt the change between fluorine ion and fin portion surface
Key is learned, and fluorine ion and etch by-products are taken away by the gas of the process of surface treatment.To surface treated
Fin portion surface is smooth, and the fluorine ion and etch by-products of the fin portion surface attachment are reduced, and is conducive to the progress of subsequent technique, and
Transistor performance enhancing, the reliability raising formed with the fin.
Further, the side wall to the fin and top surface carry out plasma-treating technology, at the plasma
The gas of science and engineering skill includes N2O、N2, one of NO or a variety of.Wherein, the gas of the plasma-treating technology by it is equal from
After daughter, Nitrogen ion can be generated, is bombarded by side wall and top surface of the Nitrogen ion to the fin, energy
Chemical bond between enough fluorine ions and fin portion surface, so as to the etching for making fluorine ion and reuniting around fluorine ion
By-product and fin portion surface are detached from, and make the fluorine ion and etch by-products by the gas of the plasma-treating technology
It takes away.
Further, when the gas of the plasma-treating technology includes N2When O or NO, the plasma-treating technology
The side wall and top surface exposed in the fin forms oxide layer, and the oxide layer can will fail to be plasma treated
The etch by-products oxidation that the gas of technique is taken away.In the plasma-treating technology and then use wet processing process
The oxide layer is removed, the etch by-products for being attached to fin portion surface can be further removed.Moreover, because in the plasma
The oxidated layer thickness formed in body treatment process is less than the boundary layer, and the oxide layer is easy to be removed by wet processing process,
And it is not easy that fin portion surface is caused to damage.
Further, after the process of surface treatment, in the insulation surface and the side wall and top table of fin
Face is developed across the gate structure of the fin；The gate structure includes positioned at side wall and the top of insulation surface and fin
The grid oxide layer on surface and grid layer positioned at grid oxygen layer surface；Since the gas of the surface treatment includes nitrogenous gas,
After side wall and top surface to the fin carry out process of surface treatment, it can be remained in the side wall and top surface of fin
Nitrogen ion, the Nitrogen ion can be spread into the grid oxide layer, to improve the dielectric constant of the grid oxide layer, reduce the grid
Equivalent oxide (EOT) thickness of oxygen layer.So as to change the performance of the fin formula field effect transistor formed with the fin
It is kind.
Detailed description of the invention
Fig. 1 is a kind of the schematic diagram of the section structure of fin formula field effect transistor of the embodiment of the present invention；
Fig. 2 to Fig. 8 is the schematic diagram of the section structure of the forming process of the semiconductor structure of the embodiment of the present invention.
Specific embodiment
As stated in the background art, the performance of the formed fin formula field effect transistor of the prior art is bad, reliability is poor.
Referring to FIG. 1, Fig. 1 is a kind of the schematic diagram of the section structure of fin formula field effect transistor of the embodiment of the present invention, packet
It includes: semiconductor substrate 100；Fin 101 positioned at 100 surface of semiconductor substrate；Dielectric layer positioned at 100 surface of semiconductor substrate
102, the side wall of fin 101 described in 102 covering part of dielectric layer, and 102 surface of dielectric layer is lower than 101 top of fin；Position
Gate structure 103 in the top and sidewall surfaces of 102 surface of dielectric layer and fin 101；Positioned at the gate structure 103
Source region 104a and drain region 104b in the fin 101 of two sides.
Wherein, described before 101 surface of fin forms gate structure 103, it is also necessary to which that well region is carried out to the fin 101
Injection technology, to form well region in the fin 101.Secondly, in order to adjust the threshold value electricity of the unlatching of the channel region in fin 101
Press size, additionally it is possible to before forming the gate structure 103, threshold voltage adjustments ion is injected in the fin 101.This
Outside, with the diminution of the size of fin 101, the Doped ions concentration in the source region 104a and drain region 104b is higher, so that institute
It states source region 104a and drain region 104b to be easier to contact with each other because of the diffusion of Doped ions, to cause source region 104a and drain region 104b
Between short circuit；Therefore, before forming the gate structure 103, it is also necessary to injected in fin 101 channel region non-proliferation from
Son, to hinder the Doped ions phase counterdiffusion in source region 104a and drain region 104b.
Due to above-mentioned well region injection technology, the injection of threshold voltage adjustments ion or the injection of channel region non-proliferation ion
It is carried out before forming gate structure 103, therefore is easy that fin portion surface is caused to damage.To solve the above-mentioned problems, can
Before carrying out well region injection technology, the injection of threshold voltage adjustments ion or the injection of channel region non-proliferation ion, in fin
The side wall and top surface that portion 101 exposes form oxide layer, and the oxide layer can protect the surface of fin, to subtract
Few damage to fin 101.Also, after completing ion implantation technology, it can be removed by isotropic etching technics
The oxide layer, to carry out being subsequently formed the processing step of gate structure 103.
The isotropic etching technics for removing removing oxide layer includes wet-etching technology and dry etch process；It is described
Isotropic dry etch process is SiCoNi etching technics.The SiCoNi etching technics compared to wet-etching technology,
Side wall and top surface for fin 101 have more accurate and uniform etch rate, and more for the damage of fin 101
It is small.
However, since the etching gas of SiCoNi etching technics is fluoro-gas, the oxygen on etching removal 101 surface of fin
After changing layer, it is easy the remained on surface fluorine ion in fin 101；When the material of the fin 101 be monocrystalline silicon when, the fluorine from
Son is easy to bond together to form F-Si key with the silicon ion on 101 surface of fin；Moreover, when fluorine ion and silicon ion are bonded, also
It is easy that the impurity generated in the SiCoNi etching technics is attracted to reunite, so that it is miscellaneous to cause the surface of fin 101 to be attached with
Matter makes the rough surface of the fin 101.When the subsequent side wall in the fin 101 and top surface form gate structure 103
Later, gate structure 103 with it is second-rate at the contact interface of fin 101, make the property for being formed by fin formula field effect transistor
It can be bad.
To solve the above-mentioned problems, the present invention provides a kind of forming method of semiconductor structure, comprising: provides substrate, institute
Substrate surface is stated with fin and separation layer, the separation layer is located at the partial sidewall surface of the fin, the separation layer
Surface is lower than the top surface of the fin, and the side wall and top surface of the fin have boundary layer；Using dry etching work
Skill removes the boundary layer, and the gas of the dry etch process includes fluoro-gas；After removing the boundary layer, to institute
The side wall and top surface for stating fin carry out process of surface treatment, and the gas of the surface treatment includes nitrogenous gas.
Wherein, the boundary layer is used for the side wall and top that protection fin exposes when carrying out ion implanting to the fin
Portion surface.The boundary layer can be removed by the dry etch process, however due to the etching of the dry etch process
Gas includes fluoro-gas, and the fluoro-gas is easy after the etching technics, is easy to remain fluorine in the fin portion surface
Ion, and the fluorine ion easily causes the reunion of other etch by-products, causes the rough surface of fin.Therefore, it is removing
After the boundary layer, need to remove the fluorine ion of fin side wall and top surface by process of surface treatment；At the surface
The gas of science and engineering skill includes nitrogenous gas, and the nitrogenous gas can interrupt the chemical bond between fluorine ion and fin portion surface, and
So that fluorine ion and etch by-products are taken away by the gas of the process of surface treatment.To surface treated fin table
Face is smooth, and the fluorine ion and etch by-products of the fin portion surface attachment are reduced, and is conducive to the progress of subsequent technique, and with described
The transistor performance that fin is formed enhances, reliability improves.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 2 to Fig. 8 is the schematic diagram of the section structure of the forming process of the semiconductor structure of the embodiment of the present invention.
Referring to FIG. 2, providing substrate 200,200 surface of substrate has fin 201 and separation layer 202, the isolation
Layer 202 is located at the partial sidewall surface of the fin 201, and the surface of the separation layer 202 is lower than the top table of the fin 201
Face.
In the present embodiment, the substrate 200 includes first area 210 and second area 220；The first area 210
It is used to form PMOS transistor, the second area 220 is used to form NMOS transistor.
In the present embodiment, the fin 201 and substrate 200 are formed by etching semiconductor substrate.200 He of substrate
The forming step of fin 201 includes: offer semiconductor base；Mask layer, the exposure mask are formed in the semiconductor substrate surface
Layer covering needs to form the semiconductor substrate surface of fin 201；Using the mask layer as exposure mask, the semiconductor base is etched,
Groove is formed in the semiconductor base, forms substrate 200 and the fin 201 positioned at 200 surface of substrate；Described in formation
After fin 201, the mask layer is removed.In other embodiments, additionally it is possible to after being subsequently formed the separation layer 202,
Remove the mask layer.
The semiconductor base is body substrate or semiconductor-on-insulator (SOI) substrate；The body substrate is silicon substrate, germanium
Substrate and silicon-Germanium substrate；The semiconductor-on-insulator substrate is silicon-on-insulator substrate or germanium substrate on insulator.In this reality
It applies in example, the semiconductor base is monocrystalline substrate, i.e., the material of the described fin 201 and substrate 200 is monocrystalline silicon.
In order to reduce the size and the distance between adjacent fin of the fin 201, the mask layer can use more
The graphical masking process of weight is formed.The multiple graphical masking process includes: self-alignment duplex pattern (Self-aligned
Double Patterned, SaDP) technique, triple graphical (the Self-aligned Triple Patterned) works of autoregistration
Skill or graphical (Self-aligned Double Double Patterned, the SaDDP) technique of autoregistration quadruple.
In one embodiment, the formation process of the mask layer is self-alignment duplex pattern chemical industry skill, comprising: in semiconductor
Substrate surface deposited sacrificial film；Patterned photoresist layer is formed in the sacrifice film surface；Using the photoresist layer as exposure mask,
The expendable film is etched until exposing semiconductor substrate surface, forms sacrificial layer, and remove photoresist layer；In semiconductor
Substrate and sacrificial layer surface deposition of mask material film；The mask material film is etched back to until exposing sacrificial layer and semiconductor-based
Until bottom surface, the semiconductor substrate surface in sacrificial layer two sides forms mask layer；It is described be etched back to technique after, remove institute
State sacrificial layer.
In another embodiment, the semiconductor base can also be semiconductor-on-insulator substrate；On the insulator
Semiconductor substrate includes: substrate, the insulating layer positioned at substrate surface, the semiconductor layer positioned at surface of insulating layer.The fin 201
Formation process include: semiconductor layer surface formed mask layer；It is using the mask layer as mask etching semiconductor layer until sudden and violent
Until exposing surface of insulating layer, the fin 201 being located on insulating layer is formed, the substrate forms substrate 200.
In other embodiments, the fin 201 is formed by the semiconductor layer that etching is formed in 200 surface of substrate, institute
It states semiconductor layer and 200 surface of substrate is formed in using selective epitaxial depositing operation.The substrate 200 is silicon substrate, silicon
Germanium substrate, silicon carbide substrates, silicon-on-insulator substrate, germanium substrate on insulator, glass substrate or III-V compound substrate,
Such as gallium nitride substrate or gallium arsenide substrate etc., the selection of the semiconductor base is unrestricted, and can choose needs suitable for technique
The semiconductor base asked or be easily integrated.The material of the semiconductor layer is therefore silicon, germanium, silicon carbide or SiGe are formed by
201 material of fin is unrestricted, can satisfy a variety of process requirements, and the thickness of the semiconductor layer can pass through extension work
Skill is controlled, so that accurately control is formed by the height of fin 201.
The separation layer 202 is for being isolated adjacent fin 201, so that the active area in fin 201 is mutually isolated.
The material of the separation layer 202 is silica, silicon nitride, silicon oxynitride, (dielectric constant is greater than or equal to low-K dielectric material
2.5, less than 3.9), one of ultralow K dielectric material (dielectric constant is less than 2.5) or multiple combinations.It is described in the present embodiment
The material of separation layer 202 is silica.
The forming step of the separation layer 202 includes: to form isolation film in the substrate 200 and 201 surface of fin；It is flat
Change the isolation film until the top surface for exposing the fin 201；After planarizing the isolation film, it is etched back to
The isolation film exposes 201 sidewall surfaces of part fin, forms separation layer 202.
The formation process of the isolation film is chemical vapor deposition process or physical gas-phase deposition, such as fluid chemistry
(FCVD, Flowable Chemical Vapor Deposition) technique, the plasma enhanced chemical vapor of being vapor-deposited are heavy
Product technique or high-aspect-ratio chemical vapor deposition process (HARP)；The flatening process is CMP process；It is described
Being etched back to technique is anisotropic dry etch process.In the present embodiment, the formation process of the isolation film is fluid chemistry
Gas-phase deposition, using the fluid chemistry gas-phase deposition formed isolation film be easy to be packed into adjacent fin 201 it
Between groove in, can make to be formed by isolation film even compact, then it is good to be formed by 202 isolation performance of separation layer.
In one embodiment, in order to avoid the chemically mechanical polishing of the planarization isolation film is to the top table of fin 201
It causes to damage in face, additionally it is possible to before forming isolation film, form polishing stop layer, the throwing in substrate 200 and 201 surface of fin
The material of light stop-layer and the material of isolation film are different, when the CMP process expose the polishing stop layer it
Afterwards, polishing or wet-etching technology were carried out to the polishing stop layer, to expose the top surface of the fin 201.
Referring to FIG. 3, the side wall and top surface in the fin 201 form boundary layer 203.
The boundary layer 203 is used to protect the fin in the subsequent progress ion implantation technology to the fin 201
201 side wall and top surface reduces the damage that 201 side wall of fin and top surface are subject to.Due to the boundary layer 203
For protecting the fin 201, therefore the boundary layer 203 will receive damage, the boundary in subsequent ion implantation technology
Surface layer 203 is unfavorable for being subsequently formed gate structure, therefore, before being subsequently formed gate structure, needs to remove the boundary layer
203。
In the present embodiment, the material of the boundary layer 203 is silica.The boundary layer 203 with a thickness of 10 angstroms~
30 angstroms；The thickness of the boundary layer 203 is unsuitable blocked up, otherwise subsequent to be not easy to completely remove the boundary layer 203, is easy in fin
The material of 203 side wall or top surface residual boundary layer 203, then becomes the performance for being formed by fin formula field effect transistor
Difference；The thickness of the boundary layer 203 is also unsuitable or thin, otherwise to the protective layer scarce capacity of 203 side wall of fin and top surface,
The side wall and top surface of the fin 203 still are easy to be damaged.
The formation process of the boundary layer 203 is oxidation technology or depositing operation, and the oxidation technology can be thermal oxide
Technique or chemical oxidation process；The depositing operation can be chemical vapor deposition process, physical gas-phase deposition or atom
Layer depositing operation；202 surface of separation layer is also located at using the boundary layer 203 that depositing operation is formed.In the present embodiment, institute
The formation process for stating boundary layer 203 is atom layer deposition process；203 thickness of boundary layer formed using atom layer deposition process is equal
Even and have good gradient coating performance, the boundary layer can be in close contact with the side wall and top surface of fin 201.
Referring to FIG. 4, carrying out ion implantation technology in the fin 201 after forming the boundary layer 203；It adopts
With the ion injected in annealing process activation fin 201.
The ion implantation technology carried out in the fin 201 includes that channel region stops injection, threshold value to adjust injection, well region
One of injection is a variety of.The well region injection is for forming well region in fin 201；In the present embodiment, described first
Region 210 is used to form PMOS transistor, and the ion that well region injects in the fin 201 of first area 210 is N-type ion；Institute
It states second area 220 and is used to form NMOS transistor, the ion that well region injects in the fin 201 of the second area 220 is P
Type ion.The threshold value adjusts injection for injecting threshold voltage adjustments ion in fin 201, the threshold voltage adjustments from
The cut-in voltage for the channel region being formed in fin 201 can be adjusted in son, to meet the skill of fin formula field effect transistor
Art demand.The channel region stop the ion of injection be used to stopping to be subsequently formed in the source region and drain region in fin 201 from
Son is spread towards channel region, so that source region and drain region be avoided to be shorted；The channel region stops the ion of injection and the source region
It is opposite with the ionic conduction type in drain region.
In the present embodiment, first area 210 is used to form PMOS transistor, and second area 220 is used to form NMOS crystalline substance
Body pipe, therefore, the ion that the fin 201 of first area 210 and second area 220 injects are different.
The step of ion implantation technology is carried out in the fin 201 includes: the separation layer in the first area 210
202 and 201 surface of fin formed the first patterned layer；Using first patterned layer as exposure mask, the is carried out to second area 220
One ion implantation technology；After first ion implantation technology, first patterned layer is removed；In removal described first
After patterned layer, second graphical layer is formed in the separation layer 202 of the second area 220 and 201 surface of fin；With described
Second graphical layer exposure mask carries out the second ion implantation technology to first area 210.
First ion implantation technology and the second ion implantation technology include that channel region stops injection, threshold value to adjust note
Enter, well region injection one of or it is a variety of.First patterned layer and second graphical layer are patterned photoresist layer, institute
The photoresist layer for stating patterned layer is formed using coating process and exposure development technique.
Referring to FIG. 5, removing the boundary layer 203 (as shown in Figure 4) using dry etch process 240, the dry method is carved
The gas of etching technique includes fluoro-gas.
In the present embodiment, before removing boundary layer 203, the second graphical layer is removed；Due to second figure
Shape layer is patterned photoresist layer, and the technique of removal second graphical layer is wet process degumming process or cineration technics.
Since the boundary layer 203 is during carrying out ion implantation technology to fin 201, it is higher than isolation for protecting
201 side wall of fin and top surface of layer 202, therefore the boundary layer 203 can be disappeared during the ion implantation technology
Consumption, it is the poor surface quality of boundary layer 203, in uneven thickness, therefore, before being subsequently formed gate structure, need to remove institute
State boundary layer 203.
The dry etch process for removing the boundary layer 203 is isotropic etching technics, isotropic quarter
The etch rate of etching technique in all directions is closer to, so as to simultaneously removal be located at 201 sidewall surfaces of fin and
The boundary layer 203 of top surface.
In the present embodiment, the material of the boundary layer 203 is silica, removes the dry etching of the boundary layer 203
Technique is SiCoNi etching technics.The parameter of the SiCoNi etching technics includes: power 10W~100W, and frequency is less than
100kHz, etching temperature are 40 degrees Celsius~80 degrees Celsius, and pressure is 0.5 support~50 supports, and etching gas includes NH3、NF3, He,
Wherein, NH3Flow be 0sccm~500sccm, NF3Flow be 20sccm~200sccm, the flow of He be 400sccm~
1200sccm, NF3With NH3Flow-rate ratio be 1:20~5:1.
The SiCoNi etching technics in addition on each different directions etch rate it is uniform other than, SiCoNi etching
The etch rate of technique is slower, especially slow compared with the etch rate of wet-etching technology, therefore the quarter of the dry etch process
It loses thickness and is easy accurate control；Moreover, the SiCoNi etching technics is small to the surface damage of fin 206a, be conducive to removing
After boundary layer 203, reduces the damage to the side wall and top surface of fin 201, reduces roughness.
However, due to including fluoro-gas, such as NF in the etching gas of the SiCoNi etching technics3, described fluorine-containing
Gas is easy after etching interface layer 203 in the 201 remained on surface fluorine ion of fin, and the fluorine ion is easy and fin
The semiconductor material ionic bonding on 201 surface of portion, forms stable chemical bond.In the present embodiment, the material of the fin 201
For monocrystalline silicon, after the SiCoNi etching technics, the fluorine ion for remaining on 201 surface of fin can be with 210 surface of fin
Silicon ion bonding, forms F-Si key.
Moreover, because it is secondary also to generate other etchings during SiCoNi etching technics etching interface layer 203
Product, and during the fluorine ion is bonded with silicon ion, it is easy that other etch by-products is attracted to send out around F-Si key
It is raw to reunite, to be easy to cause after removing boundary layer 203, adhere to impurity in the side wall and top surface of fin 201, so that
The surface of fin 201 is still coarse.If directly forming grid in 201 surface of fin after using the SiCoNi etching technics
Pole structure, then the gate structure and the interfacial state at the contact interface of fin 201 are poor, are easy to make to be formed by fin field effect
Answer the degradation of transistor.It is persistently reduced especially with dimensions of semiconductor devices, the size of the fin 201 also accordingly contracts
Small, 201 width of fin in the present embodiment is 14 nanometers~20 nanometers, then is attached to the impurity on 201 surface of fin to fin
The roughness influence on 201 surfaces is bigger, thus bigger on transistor performance influence is formed by.
Therefore, the present embodiment is after removing the boundary layer 203, the side wall and top surface to the fin 201 into
Row process of surface treatment reduces the roughness on 201 surface of fin with this to remove the fluorine ion of 201 surface of fin attachment.It is described
Process of surface treatment includes plasma-treating technology, and the gas of the plasma-treating technology includes nitrogenous gas.Below
The process of surface treatment will be illustrated.
Referring to FIG. 6, the side wall and top surface to the fin 201 carry out plasma-treating technology.
The gas of the plasma-treating technology is nitrogenous gas, after the nitrogenous gas is in plasma, energy
Nitrogen ion is enough generated, is bombarded with surface of the Nitrogen ion to fin 201, it can be by fluorine ion and 201 surface material of fin
Chemical bond between material ion interrupts, and other etch by-products of fluorine ion and reunion can be made to be plasma treated
The gas of technique is taken away, to reduce the roughness on 201 surface of fin.
Secondly, using after the Nitrogen ion bombards 201 surface of fin, it can be on 201 surface of fin
Remain Nitrogen ion, when the subsequent side wall in the fin 201 and top surface be developed across the fin 201 gate structure it
Afterwards, the Nitrogen ion for remaining on 201 surface of fin can be spread in the grid oxide layer or gate dielectric layer into gate structure, so that grid oxygen
The dielectric constant (k) of layer or gate dielectric layer improves, and the equivalent oxide thickness of the grid oxide layer or gate dielectric layer reduces, and is formed
Fin formula field effect transistor performance improve.
The parameter of the plasma-treating technology includes: that gas includes N2O、N2, one of NO or a variety of, power is
300 watts~1500 watts, pressure is 10 millitorrs~100 millitorrs, and flow is 20sccm~~300sccm.
In the present embodiment, the gas of the plasma-treating technology includes N2O or NO, by the N2O or NO plasma
After body, additionally it is possible to produce oxonium ion, the oxonium ion can form oxide layer 204 on the surface of fin 201, will fail by etc.
The fluorine ion or the oxidation of other etch by-products that the gas of gas ions treatment process is taken away；It is subsequent to pass through wet-etching technology
Remove the oxide layer 204.
The oxide layer 204 with a thickness of 5 angstroms~10 angstroms.The thickness of the oxide layer 204 is less than the boundary layer 203
The thickness of thickness, the oxide layer 204 is very thin, therefore the oxide layer 204 is easy to be removed, and will not be to 201 surface of fin
It causes to damage.
Energy entrained by the generated Nitrogen ion of the plasma-treating technology should not be too large, and otherwise be easy to fin
Portion causes to damage in 201 surface；And energy entrained by the generated Nitrogen ion of the plasma-treating technology also should not mistake
It is small, it otherwise can not interrupt F-Si key.
In other embodiments, the gas of the plasma-treating technology includes N2, then in the corona treatment
After technique, the surface of fin 201 not will form oxide layer, therefore, after the plasma-treating technology, without
Wet-etching technology removes the oxide layer.
Referring to FIG. 7, removing the oxide layer using wet processing process after the plasma-treating technology
204。
In the present embodiment, the material of the oxide layer 204 is silica, and the etching liquid of the wet processing process is hydrogen fluorine
Acid solution；The volume ratio of water and hydrofluoric acid is 20:1~~200:1, the concentration of the hydrofluoric acid solution in the hydrofluoric acid solution
It is lower.Since the thickness of the oxide layer 204 is very thin, the oxidation can be removed with the hydrofluoric acid solution of low concentration
Layer.Moreover, not will cause damage to 201 surface of fin when the concentration of the hydrofluoric acid solution is lower.Further, since described
The concentration of hydrofluoric acid solution is lower, being thinned and damaging smaller to the separation layer 202.Therefore, the oxide layer 204 is being removed
Later, 201 surface topography of fin is good.
Referring to FIG. 8, after the process of surface treatment, in 202 surface of separation layer and the side of fin 201
Wall and top surface are developed across the gate structure (not indicating) of the fin 201；Fin 201 in the gate structure two sides
Interior formation source region and drain region (not indicating).
In the present embodiment, before forming the gate structure, the separation layer 202 and 201 surface of fin are carried out
Pre-cleaning processes, the pre-cleaning processes are used to remove the by-products such as the polymer of separation layer 202 and the attachment of 201 surface of fin.
The gate structure includes the grid oxide layer of the side wall and top surface positioned at 202 surface of separation layer and fin 201
205, the grid layer 206 positioned at 205 surface of grid oxide layer and the side wall positioned at 206 sidewall surfaces of grid oxide layer 205 and grid layer.
The forming step of the grid oxide layer 205 and grid layer 206 includes: in 202 surface of the separation layer and fin 201
Side wall and top surface formed grid oxygen film；Gate electrode film is formed in the grid oxygen film surface；It is formed and is schemed in the grid film surface
Shape layer, the patterned layer covering need to form the corresponding region of grid layer 206；Using the patterned layer as exposure mask, etching
The gate electrode film and grid oxygen film form grid oxide layer 205 and grid until exposing 201 surface of the separation layer 202 and fin
Pole layer 206.
The material of the grid oxide layer 205 is silica；The grid oxygen film can be with thermal oxidation technology formation, atomic layer deposition
Technique is formed or chemical vapor deposition process is formed.The material of the grid layer 206 is polysilicon.In the present embodiment, described
Gate structure is dummy gate structure, subsequent to need to remove the grid layer 206, and is substituted with high-k gate dielectric layer and metal gate.
In another embodiment, the gate structure is directly used in form transistor, then the grid oxide layer 205 is used as gate dielectric layer.
In the present embodiment, after forming source region and drain region, further includes: in 202 surface of separation layer and fin
201 side wall and top surface forms dielectric layer, and the dielectric layer is flushed with the top surface of gate structure；Remove the grid
Layer 206 forms opening in the dielectric layer；High-k gate dielectric layer is formed in the opening；In the high-k gate dielectric layer table
Face forms the metal gate for filling the full opening.
It in the present embodiment, can be in fin 201 since the gas of the plasma-treating technology includes nitrogenous gas
Remained on surface Nitrogen ion, the Nitrogen ion can be spread into the grid oxide layer 205 and high-k gate dielectric layer, so that grid oxide layer
205 and high-k gate dielectric layer dielectric constant improve, equivalent oxide thickness reduce so that formed transistor performance improve.
In the present embodiment, when being formed by fin formula field effect transistor and being used to form input and output (IO) circuit, therefore,
The operating voltage for being formed by fin formula field effect transistor is higher, then the equivalent oxide thickness of grid oxide layer 205 is reduced to crystal
The performance improvement of pipe becomes apparent from.
In addition, when being formed by transistor is PMOS transistor, since the material of the grid oxide layer 205 is turned by silica
Become silicon oxynitride, grid oxide layer 205 and the dielectric constant raising of high-k gate dielectric layer, equivalent oxide thickness reduce, can make
Negative Bias Temperature Instability (NBTI) problem of PMOS transistor is inhibited, so that the performance of PMOS transistor is more preferably.
To sum up, in the present embodiment, the boundary layer is used for the protection fin exposure when carrying out ion implanting to the fin
Side wall and top surface out.The boundary layer can be removed by the dry etch process, however since the dry method is carved
The etching gas of etching technique includes fluoro-gas, and the fluoro-gas is easy after the etching technics, is easy in the fin
Portion's remained on surface fluorine ion, and the fluorine ion easily causes the reunion of other etch by-products, causes the rough surface of fin.
Therefore, after removing the boundary layer, need to remove the fluorine ion of fin side wall and top surface by process of surface treatment；
The gas of the process of surface treatment includes nitrogenous gas, and the nitrogenous gas can interrupt between fluorine ion and fin portion surface
Chemical bond, and fluorine ion and etch by-products are taken away by the gas of the process of surface treatment.To by surface treatment
Fin portion surface it is smooth, the fluorine ion and etch by-products of fin portion surface attachment are reduced, be conducive to the progress of subsequent technique,
And transistor performance enhancing, the reliability raising formed with the fin.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of semiconductor structure characterized by comprising
Substrate is provided, the substrate surface has fin and separation layer, and the separation layer is located at the partial sidewall table of the fin
Face, the surface of the separation layer are lower than the top surface of the fin, and the side wall and top surface of the fin have boundary layer；
The boundary layer is removed using dry etch process, the gas of the dry etch process includes fluoro-gas；
After removing the boundary layer, side wall and top surface to the fin carry out process of surface treatment, the surface
The gas of processing includes nitrogenous gas.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of the boundary layer is oxidation
Silicon；The boundary layer with a thickness of 10 angstroms~30 angstroms.
3. the forming method of semiconductor structure as claimed in claim 2, which is characterized in that the dry method for removing the boundary layer is carved
Etching technique is SiCoNi etching technics.
4. the forming method of semiconductor structure as claimed in claim 3, which is characterized in that the ginseng of the SiCoNi etching technics
Number includes: power 10W~100W, and frequency is less than 100kHz, and etching temperature is 40 degrees Celsius~80 degrees Celsius, and pressure is 0.5 support
~50 supports, etching gas include NH3、NF3, He, wherein NH3Flow be 0sccm~500sccm, NF3Flow be 20sccm
The flow of~200sccm, He are 400sccm~1200sccm, NF3With NH3Flow-rate ratio be 1:20~5:1.
5. the forming method of semiconductor structure as described in claim 1, which is characterized in that the step of the process of surface treatment
It include: that plasma-treating technology is carried out to the side wall and top surface of the fin.
6. the forming method of semiconductor structure as claimed in claim 5, which is characterized in that the plasma-treating technology
Parameter includes: that gas includes N2O、N2, one of NO or a variety of, power is 300 watts~1500 watts, and pressure is 10 millitorr~100
Millitorr, flow are 20sccm~300sccm.
7. the forming method of semiconductor structure as claimed in claim 6, which is characterized in that when the plasma-treating technology
Gas include N2When O or NO, the side wall and top surface that the plasma-treating technology is exposed in the fin are formed
Oxide layer.
8. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that the step of the process of surface treatment
Further include: after the plasma-treating technology, the oxide layer is removed using wet processing process.
9. the forming method of semiconductor structure as claimed in claim 8, which is characterized in that the liquid of the wet processing process
For hydrofluoric acid solution；The volume ratio of water and hydrofluoric acid is 20:1~200:1 in the hydrofluoric acid solution.
10. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that the thickness of the oxide layer is less than
The thickness of the boundary layer；The oxide layer with a thickness of 5 angstroms~10 angstroms.
11. the forming method of semiconductor structure as described in claim 1, which is characterized in that further include: in the surface treatment
After technique, pre-cleaning processes are carried out to the separation layer and fin portion surface.
12. the forming method of semiconductor structure as described in claim 1, which is characterized in that after forming the boundary layer,
Before removing the boundary layer, ion implantation technology is carried out in the fin；It is activated in fin and is injected using annealing process
Ion.
13. the forming method of semiconductor structure as claimed in claim 12, which is characterized in that carried out in the fin from
Sub- injection technology includes that channel region stops injection, threshold value to adjust one of injection, well region injection or a variety of.
14. the forming method of semiconductor structure as described in claim 1, which is characterized in that the formation of the substrate and fin
Step includes: offer semiconductor base；Mask layer is formed in the semiconductor substrate surface, the mask layer covering needs to form
The semiconductor substrate surface of fin；Using the mask layer as exposure mask, the semiconductor base is etched, in the semiconductor base
Groove is formed, substrate and the fin positioned at substrate surface are formed.
15. the forming method of semiconductor structure as described in claim 1, which is characterized in that the forming step of the separation layer
It include: to form isolation film in the substrate and fin portion surface；The isolation film is planarized until exposing the top of the fin
Until surface；After planarizing the isolation film, it is etched back to the isolation film, exposes part fin sidewall surfaces, formed
Separation layer.
16. the forming method of semiconductor structure as described in claim 1, which is characterized in that the process of surface treatment it
Afterwards, the gate structure of the fin is developed across in the side wall and top surface of the insulation surface and fin；Described
Source region and drain region are formed in the fin of gate structure two sides.
17. the forming method of semiconductor structure as claimed in claim 16, which is characterized in that the gate structure includes being located at
The grid oxide layer of the side wall and top surface of insulation surface and fin, positioned at grid oxygen layer surface grid layer and be located at grid oxygen
The side wall of layer and grid layer sidewall surfaces.
18. the forming method of semiconductor structure as claimed in claim 17, which is characterized in that the grid oxide layer and grid layer
Forming step includes: the side wall and top surface formation grid oxygen film in the insulation surface and fin；In the grid oxygen film
Surface forms gate electrode film；Patterned layer is formed in the grid film surface, the patterned layer covering needs to form grid layer
Corresponding region；Using the patterned layer as exposure mask, the gate electrode film and grid oxygen film are etched, until exposing the separation layer and fin
Until portion surface, grid oxide layer and grid layer are formed.
19. the forming method of semiconductor structure as claimed in claim 17, which is characterized in that the material of the grid oxide layer is oxygen
SiClx；The material of the grid layer is polysilicon.
20. the forming method of semiconductor structure as claimed in claim 19, which is characterized in that formed source region and drain region it
Afterwards, further includes: form dielectric layer, the dielectric layer and grid in the side wall and top surface of the insulation surface and fin
The top surface of pole structure flushes；The grid layer is removed, forms opening in the dielectric layer；It is formed in the opening high
K gate dielectric layer；The metal gate for filling the full opening is formed in the high-k gate dielectric layer surface.
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| EP0789400A2 (en) * | 1996-02-07 | 1997-08-13 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| CN104701168A (en) * | 2013-12-05 | 2015-06-10 | 中芯国际集成电路制造(上海)有限公司 | Forming method of fin field-effect transistor |
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| EP0789400A2 (en) * | 1996-02-07 | 1997-08-13 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| CN104701168A (en) * | 2013-12-05 | 2015-06-10 | 中芯国际集成电路制造(上海)有限公司 | Forming method of fin field-effect transistor |
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