CN104752215B - The forming method of transistor - Google Patents

The forming method of transistor Download PDF

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CN104752215B
CN104752215B CN201310745735.2A CN201310745735A CN104752215B CN 104752215 B CN104752215 B CN 104752215B CN 201310745735 A CN201310745735 A CN 201310745735A CN 104752215 B CN104752215 B CN 104752215B
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layer
dielectric layer
gate
stop
dummy gate
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CN104752215A (en
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禹国宾
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A kind of forming method of transistor, including：Substrate is provided, the substrate surface has dummy gate structure, and the dummy gate structure includes：Pseudo- gate dielectric layer positioned at substrate surface and the dummy gate layer positioned at pseudo- gate dielectric layer surface；Stop-layer is formed in the substrate and dummy gate structure surface, there are Doped ions in the stop-layer；Dielectric layer is formed in the stopping layer surface, the dielectric layer surface flushes with the stopping layer surface at the top of dummy gate layer；Stop-layer, dummy gate layer and the pseudo- gate dielectric layer at the top of dummy gate layer are removed, opening is formed in the dielectric layer；Gate dielectric layer and grid layer are formed in the opening, the gate dielectric layer is located at the side wall and lower surface of opening, and the grid layer is located at gate dielectric layer surface and forms the full opening of filling.The stable performance of the transistor formed, pattern are good.

Description

The forming method of transistor
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of forming method of transistor.
Background technology
With the fast development of ic manufacturing technology, promote the semiconductor devices in integrated circuit, especially MOS （Metal Oxide Semiconductor, Metal-oxide-semicondutor）The size of device constantly reduces, and meets to collect with this Miniaturization and integrated requirement into circuit development.During the size of MOS transistor device persistently reduces, existing work Skill is challenged using silica or silicon oxynitride as the technique of gate dielectric layer.Gate medium is used as using silica or silicon oxynitride There is some problems, including leakage current increase and the diffusion of impurity in the transistor that layer is formed, so as to influence transistor Threshold voltage, and then influence the performance of semiconductor devices.
To solve problem above, it is suggested with the transistor that high-K gate dielectric layer and metal gate are formed, i.e. high-K metal gate （HKMG, High K Metal Gate）Transistor.The high-K metal gate transistor uses high K（Dielectric constant）Material replaces normal Silica or silicon oxynitride gate dielectric material, the generation of leakage current can be reduced while transistor size is reduced, and Improve the performance of transistor.
Specifically, Fig. 1 is refer to, Fig. 1 is a kind of cross-sectional view of high-K metal gate transistor, including：Positioned at lining The dielectric layer 105 and grid structure 110 on the surface of bottom 100, the top surface of the grid structure 110 and the dielectric layer 105 Surface flushes, and the grid structure 110 includes：High-K gate dielectric layer 101 positioned at the surface of substrate 100, positioned at high-K gate dielectric layer The metal gate 103 on 101 surfaces, the side wall 104 positioned at the surface of substrate 100 of high-K gate dielectric layer 101 and the both sides of metal gate 103；Position In the source region in the substrate 100 of the grid structure both sides and drain region 106.
However, the performance for the high-K metal gate transistor that prior art is formed is unstable.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of forming method of transistor, the pattern of the formed transistor of improvement, Improve the performance of formed transistor.
To solve the above problems, the present invention provides a kind of forming method of transistor, including：Substrate, the substrate are provided Surface has dummy gate structure, and the dummy gate structure includes：It is situated between positioned at the pseudo- gate dielectric layer of substrate surface and positioned at pseudo- grid The dummy gate layer of matter layer surface；Stop-layer is formed in the substrate and dummy gate structure surface, there is doping in the stop-layer Ion；Dielectric layer, the dielectric layer surface and the stopping layer surface at the top of dummy gate layer are formed in the stopping layer surface Flush；Stop-layer, dummy gate layer and the pseudo- gate dielectric layer at the top of dummy gate layer are removed, opening is formed in the dielectric layer； Gate dielectric layer is formed in the opening and grid layer, the gate dielectric layer are located at the side wall and lower surface of opening, the grid Layer is positioned at gate dielectric layer surface and forms the full opening of filling.
Optionally, the material of the stop-layer is silicon nitride, and the Doped ions are carbon ion.
Optionally, the concentration of the Doped ions in the stop-layer be 0.5E15 atoms/square centimeter~12E15 atoms/ Square centimeter.
Optionally, the technique that the Doped ions are adulterated in stop-layer is ion implantation technology or doping process in situ.
Optionally, when the technique that the Doped ions are adulterated in stop-layer is ion implantation technology, Implantation Energy is 200 electron-volts~50 kilo electron volts.
Optionally, removing the technique of the stop-layer at the top of dummy gate layer, dummy gate layer and pseudo- gate dielectric layer includes：Etching is pseudo- Stop-layer at the top of grid layer, untill dummy gate layer top surface is exposed；Stop-layer at the top of etching dummy gate layer Afterwards, the dummy gate layer and pseudo- gate dielectric layer are etched, untill substrate surface is exposed.
Optionally, the material of the pseudo- gate dielectric layer is silica, and the material of the dummy gate layer is polysilicon.
Optionally, the formation process of the pseudo- gate dielectric layer includes thermal oxidation technology.
Optionally, the technique for removing pseudo- gate dielectric layer is wet-etching technology or dry etch process.
Optionally, in addition to：Formed before gate dielectric layer, liner oxidation is formed in the side wall and lower surface of the opening Layer, the gate dielectric layer are formed at the liner oxidation layer surface.
Optionally, the material of the pad silicon oxide layer is silica, and the formation process of the cushion oxide layer is chemistry Gas-phase deposition.
Optionally, the formation process of the gate dielectric layer and gate electrode layer includes：In dielectric layer surface and the side of opening Wall and lower surface deposition gate dielectric film；The gate electrode film of filling full gate mouth is deposited on gate dielectric film surface；Thrown using chemical machinery Light technique planarizes the gate electrode film and gate dielectric film, and untill dielectric layer surface is exposed, the gate electrode film forms grid Layer, the gate dielectric film form gate dielectric layer.
Optionally, the material of the gate dielectric layer is high K dielectric material, and the material of the grid layer is metal.
Optionally, the dummy gate structure also includes：Side wall table positioned at the dummy gate layer and pseudo- gate dielectric layer both sides Face and the side wall of substrate surface.
Optionally, the material of the dielectric layer is silica, and the formation process of the dielectric layer includes：Stopping layer surface Deposition medium film；The deielectric-coating is planarized using CMP process, until exposing dummy gate layer top surface Stop-layer, form dielectric layer.
Optionally, in addition to：Before stop-layer is formed, source region and leakage are formed in the substrate of the dummy gate structure both sides Area.
Compared with prior art, technical scheme has advantages below：
In the forming method of the transistor of the present invention, stop-layer is formed in the substrate and dummy gate structure surface, it is described There are Doped ions, the dielectric layer surface being subsequently formed flushes with the stopping layer surface at the top of dummy gate layer in stop-layer. In order to remove dummy gate layer and pseudo- gate dielectric layer, it is necessary to remove the stop-layer at the top of dummy gate layer first, then positioned at dummy grid knot Flushed at the top of the stop-layer of structure sidewall surfaces with dummy gate layer surface, and the dielectric layer surface is higher than stop-layer top and pseudo- grid Pole layer surface.After dummy gate layer is removed, during removing pseudo- gate dielectric layer, due in the stop-layer have doping from Son, makes the etch rate of stop-layer reduce, and the top surface of the stop-layer will not be cut down；Meanwhile the dielectric layer Surface accordingly reduces during pseudo- gate dielectric layer is removed, until being flushed with the top surface of the stop-layer.Therefore, going After the pseudo- gate dielectric layer, the stop-layer and dielectric layer surface can keep flat, the grid layer and grid being subsequently formed The material of dielectric layer is not easy to residue in stop-layer and dielectric layer surface, ensure that formed transistor performance is stable；Moreover, nothing Excessive change need to be carried out to the forming process of transistor can reach the effect for improving transistor performance.
Further, the material of the stop-layer is silicon nitride, and the Doped ions are carbon ion.Due to the pseudo- gate medium The material of layer be silica, in the etching technics of the removal pseudo- gate dielectric layer, the etching technics for doped with carbon from The silicon nitride etch speed of son is extremely slow, therefore after the pseudo- gate dielectric layer is removed, the pattern and size of the stop-layer are not It can change, and dielectric layer surface can accordingly be reduced to the position with being flushed at the top of stop-layer so that dielectric layer and stopping The surface of layer is flat dry.
Brief description of the drawings
Fig. 1 is a kind of cross-sectional view of high-K metal gate transistor；
Fig. 2 to Fig. 4 is a kind of cross-sectional view for the process for forming grid structure as shown in Figure 1；
Fig. 5 to Figure 11 is the cross-sectional view of the forming process of the transistor of the embodiment of the present invention.
Embodiment
As stated in the Background Art, the performance for the high-K metal gate transistor that prior art is formed is unstable.
Found by research, the existing technique for forming high-K metal gate transistor is rear grid technique（Gate Last）, and institute Stating rear grid technique can cause damage to the size of the grid structure formed.Fig. 2 to Fig. 4 specifically is refer to, Fig. 2 to Fig. 4 is one Kind forms the cross-sectional view of the process of grid structure 110 as shown in Figure 1.
It refer to Fig. 2, there is provided substrate 100, the surface of substrate 100 have dummy gate structure 120, the dummy gate structure 120 include：Pseudo- gate dielectric layer 121 positioned at substrate surface, the dummy gate layer 122 positioned at the pseudo- surface of gate dielectric layer 121, Yi Jiwei Side wall 123 in dummy gate layer 122 and the surface of 121 both sides substrate of pseudo- gate dielectric layer 100, the surface of substrate 100, which also has, to be situated between Matter layer 105, the surface of the dielectric layer 105 flush with the surface of dummy gate layer 122.
Fig. 3 is refer to, removes the dummy gate layer 122（As shown in Figure 2）, opening is formed in the dielectric layer 105 124。
Fig. 4 is refer to, removes the pseudo- gate dielectric layer 121 of 124 bottoms of the opening（As shown in Figure 3）.
Wherein, because the material of dummy gate layer 122 is polysilicon, and the generally use silicon substrate of substrate 100, therefore dummy grid Etch selectivity between layer 122 and substrate 100 is poor, it is therefore desirable to is formed between pseudo- gate dielectric layer 121 and substrate 100 pseudo- Gate dielectric layer 121, the pseudo- gate dielectric layer 121 can protect the surface of substrate 100 injury-free when removing dummy gate layer 122. The material of the pseudo- gate dielectric layer 121 is silica, and formation process is thermal oxidation technology, the silica formed with thermal oxidation technology It is combined preferably dummy gate layer 122 and substrate 100, is advantageous to the progress of technique.However, formed with thermal oxidation technology Silica equivalent oxide thickness（EOT, Equivalent Oxide Thickness）It is larger, with dimensions of semiconductor devices Diminution, the pseudo- gate dielectric layer 121 positioned at the bottom of opening 124 can adversely affect to the transistor performance being subsequently formed, and And after the etching technics by removing dummy gate layer 122, the thickness of the pseudo- gate dielectric layer 121 is difficult to control.Therefore, exist The dummy gate layer 122 is removed afterwards, it is necessary to remove the pseudo- gate dielectric layer 121 and expose the surface of substrate 100, so as to follow-up Cushion oxide layer, gate dielectric layer and gate electrode layer are formed on the surface of substrate 100 of the bottom of opening 124.
However, because the material of the dielectric layer 105 is generally also silica, therefore removing the pseudo- gate dielectric layer When 121, the thickness of the dielectric layer 105 can accordingly be thinned, moreover, the side wall 123 also can be accordingly by a certain degree of quarter Erosion, cause the uneven surface of the dielectric layer 105 and side wall 123.The subsequently filling high-K gate dielectric layer in the opening 124 With metal gate afterwards, it is necessary to the metal gate material on the surface of dielectric layer 105 be removed using glossing, due to the dielectric layer 105 With the uneven surface of side wall 123, the material of metal gate is easily set to residue in the surface of dielectric layer 105 or the top of side wall 123, easily Make to produce leakage current at the top of metal gate, influence the performance of formed transistor.
A kind of solution to the problems described above is to form barrier layer in substrate 100 and the surface of dummy gate structure 120, subsequently It is open when source region and drain region surface form conductive structure, it is necessary to be formed using etching technics in dielectric layer 105, and the resistance Barrier can define the stop position of the etching technics, to protect the surface of substrate 100 from damage.The shape of dielectric layer 105 Barrier layer surface described in Cheng Yu, and the surface of dielectric layer 105 flushes with the barrier layer surface at the top of dummy gate layer 122, i.e., it is described The surface of dielectric layer 105 is higher than the surface of dummy gate layer 122.Subsequently remove dummy gate layer 122 and pseudo- gate dielectric layer 121 it It is preceding, it is necessary to first remove the barrier layer at the top of dummy gate layer 122, then at the top of remaining barrier layer with the surface of dummy gate layer 122 or side The top of wall 123 flushes, and when subsequently removing pseudo- gate dielectric layer 121, dielectric layer 105 can be made correspondingly to level off to and stopped with remaining Equal position at the top of layer top or side wall 123, to reach the purpose for making dielectric layer 105 flat with the surface of side wall 123.So And because the material on the barrier layer is usually silicon nitride, the silicon nitride can still etch the process of gate dielectric layer 121 In by a certain degree of etching, cause to reduce at the top of remaining barrier layer so that described after gate dielectric layer 121 is removed Barrier layer is still difficult to reach to flush with the surface of dielectric layer 105, can still be pushed up on the surface of dielectric layer 105 or barrier layer and side wall 123 The material of portion's kish grid.
In order to solve the above problems, after further research, the present invention proposes a kind of forming method of transistor.Wherein, Stop-layer is formed in the substrate and dummy gate structure surface, there is Doped ions, the medium being subsequently formed in the stop-layer Layer surface flushes with the stopping layer surface at the top of dummy gate layer.In order to remove dummy gate layer and pseudo- gate dielectric layer, it is necessary to head The stop-layer at the top of dummy gate layer is first removed, then positioned at the stop-layer top of dummy gate structure sidewall surfaces and dummy gate layer surface Flush, and the dielectric layer surface is higher than at the top of stop-layer and dummy gate layer surface.After dummy gate layer is removed, remove pseudo- grid and be situated between During matter layer, due to having Doped ions in the stop-layer, make the etch rate of stop-layer reduce, the stop-layer Top surface will not be cut down；Meanwhile the surface of the dielectric layer accordingly reduces during pseudo- gate dielectric layer is removed, directly Extremely flushed with the top surface of the stop-layer.Therefore, after the pseudo- gate dielectric layer is removed, the stop-layer and dielectric layer Surface can keep flat, and the grid layer and the material of gate dielectric layer being subsequently formed are not easy to residue in stop-layer and dielectric layer table Face, it ensure that formed transistor performance is stable；Moreover, i.e. can without carrying out excessive change to the forming process of transistor Reaching improves the effect of transistor performance.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.
Fig. 5 to Figure 11 is the cross-sectional view of the forming process of the transistor of the embodiment of the present invention.
It refer to Fig. 5, there is provided substrate 200, the surface of substrate 200 have dummy gate structure 201, the dummy gate structure 201 include：Pseudo- gate dielectric layer 210 positioned at the surface of substrate 200 and the dummy gate layer positioned at the pseudo- surface of gate dielectric layer 210 211。
The substrate 200 is silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator（SOI）On substrate, insulator Germanium（GOI）Substrate, glass substrate or III-V substrate（Such as silicon nitride or GaAs etc.）.It is described in the present embodiment The surface of substrate 200 forms high-K metal gate transistor, and the high-K metal gate transistor is formed using rear grid technique, it is necessary to shape first Into the dummy gate structure 201 for substituting the high-K metal gate structure.
In the present embodiment, the substrate 200 has first area I and second area II, and the first area I and second The region II surface of substrate 200 is respectively provided with dummy gate structure 201, and the first area I and second area II can be used in being formed The transistor of difference in functionality or type.In one embodiment, the first area I is used to form PMOS transistor, and described second Region II is used to form nmos pass transistor.In another embodiment, the first area I is used to form core devices, and described the Two region II are used to form input and output device.
The dummy gate structure 201 takes up space for the gate dielectric layer and grid layer being subsequently formed, the pseudo- gate dielectric layer 210 material is silica, and the material of the dummy gate layer 211 is polysilicon.The formation process of dummy gate structure 201 includes： Pseudo- gate dielectric film is formed on the surface of substrate 200；In the pseudo- gate dielectric film surface deposition dummy grid film；In the dummy grid film table Face forms patterned photoresist layer, and the photoresist layer defines the corresponding position of pseudo- gate dielectric layer 210 and dummy gate layer 211 Put；Using the photoresist layer as dummy grid film described in mask etching and pseudo- gate dielectric film, it is up to exposing the surface of substrate 200 Only.
Wherein, the pseudo- gate dielectric layer 210 be used for subsequently remove dummy gate layer 211 when, protect the surface of substrate 200 from Damage.In the present embodiment, it is thermal oxidation technology to form the pseudo- technique of gate dielectric layer 210, the energy of pseudo- gate dielectric layer 210 formed It is enough dummy gate layer 211 is combined with substrate 200.However, the pseudo- gate dielectric layer 210 formed using thermal oxidation technology is equivalent Oxidated layer thickness is higher, is unfavorable for the size reduction of semiconductor devices, moreover, when subsequently removing dummy gate layer 211, can not keep away Understand damaged portion puppet gate dielectric layer 210 with exempting from, make the size of pseudo- gate dielectric layer 210 be difficult to accurately control, it is therefore, follow-up to need to go Except the pseudo- gate dielectric layer 210, and the cushion oxide layer for meeting technical need is formed, as the gate dielectric layer and lining being subsequently formed Binder course between bottom.
In the present embodiment, the dummy gate structure 201 also includes：Positioned at the dummy gate layer 211 and pseudo- gate dielectric layer The sidewall surfaces of 210 both sides and the side wall 212 on the surface of substrate 200.
The side wall 212 defines the source region being formed in the substrate 200 of the both sides of dummy gate structure 201 and 213, drain region Put.The material of the side wall 212 is one or more overlapping combinations in silica, silicon nitride, silicon oxynitride.The side wall 212 formation process includes：Side wall film is deposited on substrate 200, pseudo- gate dielectric layer 210 and the surface of dummy gate layer 211；It is etched back to institute Side wall film is stated, untill the top surface of dummy gate layer 211 and the surface of substrate 200 is exposed.
After side wall 212 is formed, using substrate 200 of the ion implantation technology in dummy gate layer 211 and the both sides of side wall 212 Interior doped p-type ion or N-type ion, form source region and drain region 213.After source region and drain region 213 is formed, dummy grid is being removed Layer 211 and pseudo- gate dielectric layer 210, and being substituted with high-K gate dielectric layer and metal gate layers, after the formation process of the transistor is Grid technique, i.e., after source region and drain region 213 is formed, form grid layer.
Fig. 6 is refer to, stop-layer 202, the stop-layer 202 are formed in the substrate 200 and the surface of dummy gate structure 201 It is interior that there are Doped ions.
Due to subsequently being formed after grid layer and gate dielectric layer, it is necessary to which formation is located at source region and drain region in dielectric layer The conductive structure on 213 surfaces, to realize source region and drain region 213 and the electrical connection of chip circuit；Wherein, in order to form the conduction Structure exposes source region and the opening in drain region 213, it is necessary to etch to be formed in the dielectric layer being subsequently formed, in order in the etching The surface of substrate 200 is protected in technique, before the dielectric layer is formed, stop-layer 202 is formed on the surface of substrate 200, is given an account of Matter layer is formed at the surface of stop-layer 202, and the stop-layer 202 is different from the material of dielectric layer, makes the stop-layer There is Etch selectivity between 202 and dielectric layer.
Moreover, after stop-layer 202 is formed, after subsequent technique forms gate dielectric layer and grid layer, due to grid The side wall of layer and side wall 212 has the protection of stop-layer 202, and the conductive structure for being formed at source region and the surface of drain region 213 can be residual Autoregistration is stayed to make electrical contact with（Self-Align Contact）Technique is formed, and is advantageous to improve the density of semiconductor devices and is integrated Degree, reduce the size of semiconductor devices and chip.
Because the stop-layer 202 is formed at the top surface of dummy gate layer 211, and the dielectric layer being subsequently formed is with being located at puppet The surface of stop-layer 202 at the top of grid layer 211 is flushed, and the dielectric layer surface can be made to be higher than the surface of dummy gate layer 211, then after During the pseudo- gate dielectric layer 210 of continuous removal, the thickness of dielectric layer can be made to be reduced to the position flushed with the top of stop-layer 202.
In order to ensure during subsequently gate dielectric layer 210 is removed, the accurate size of the stop-layer 202 is stable, needs The stop-layer 202 is set not influenceed and height reduction by etching, it is therefore desirable to make the etching work of removal gate dielectric layer 210 Skill reduces to the etch rate of stop-layer 202, and the Doped ions in the stop-layer 202 can improve stop-layer 202 Etch selectivity, make the technique of subsequent etching gate dielectric layer 210 extremely low for the etch rate of stop-layer 202.
In the present embodiment, the material of the stop-layer 202 is silicon nitride, and the Doped ions in the stop-layer 202 are Carbon ion.Because the material of the pseudo- gate dielectric layer 210 is silica, and the technique of etching oxidation silicon is for the silicon nitride of carbon dope Etch rate is extremely low, thus can ensure subsequently remove gate dielectric layer 210 during, the pattern of the stop-layer 202 and Size can keep stable, and the height of the stop-layer 202 will not reduce.
The formation process of the stop-layer 202 includes：Stopper film is deposited on the surface of substrate 200 and grid structure 201；Adopt With doping process Doped ions are formed in the stopper film.Wherein, the concentration of the Doped ions in the stop-layer 202 is 0.5E15 atoms/square centimeter~12E15 atoms/square centimeter；And the technique that the Doped ions are adulterated in stop-layer 202 For ion implantation technology or doping process in situ.In the present embodiment, the technique that the Doped ions are adulterated in stop-layer 202 For ion implantation technology, and Implantation Energy is 200 electron-volts~50 kilo electron volts.
Fig. 7 is refer to, dielectric layer 203 is formed on the surface of stop-layer 202, the surface of dielectric layer 203 is with being located at puppet The surface of stop-layer 202 at the top of grid layer 211 flushes.
The material of the dielectric layer 203 is the one or more in silica, silicon nitride, silicon oxynitride, low-K dielectric material Combination, and the material of the dielectric layer 203 is different from the material of stop-layer 202, makes the stop-layer 202 and dielectric layer 203 Between there is Etch selectivity；In the present embodiment, the material of the dielectric layer 203 is silica.
The formation process of the dielectric layer 203 includes：In the surface deposition medium film of stop-layer 202；Thrown using chemical machinery Light technique planarizes the deielectric-coating, until exposing the stop-layer 202 of the top surface of dummy gate layer 211, forms dielectric layer 203.After the CMP process, the surface of the dielectric layer 203 and the stopping positioned at the top of dummy gate layer 211 202 surface of layer flush, i.e., the surface of described dielectric layer 203 is higher than the surface of dummy gate layer 211, then subsequently removes pseudo- gate dielectric layer After 210, the surface of dielectric layer 203 can be made to be flushed with the top of stop-layer 202 given birth to, be advantageous to make stop-layer 202, medium Layer 203 and side wall 212 keep flat, so as to avoid being subsequently formed after grid layer dielectric layer 203, the top of stop-layer 202 or The material of the top surface kish grid of side wall 212.
In the present embodiment, the surface of substrate 200 has some dummy gate structures 201, and has between adjacent dummy gate structure 201 There is the groove for exposing substrate 200 or source region and drain region 213.In order to reduce the size of semiconductor devices and chip, the pseudo- grid The distance between the size of pole structure 201 and adjacent dummy gate structure 201 accordingly reduce, so as to improve formed crystal The density or integrated level of pipe, cause groove between adjacent dummy gate structure 201 parallel to the surface direction of substrate 20 size compared with It is small.And the depth of the groove will not change, then the depth-to-width ratio of the groove（AR, Aspect Ratio）Increase, easily Cause to be difficult to enter the groove for forming the material of dielectric layer 203, the dielectric layer for being formed at groove is internally formed space （void）, cause the performance of formed semiconductor devices unstable.
Therefore, in the present embodiment, the technique for forming the deielectric-coating is high-aspect-ratio depositing operation（HARP, High Aspect Ratio Process）, the high-aspect-ratio depositing operation can make the deielectric-coating that is formed in groove fine and close.It is described The parameter of high-aspect-ratio depositing operation includes：Deposition gases include tetraethyl orthosilicate and ozone, the flow of the tetraethyl orthosilicate For the mg minute of 500 mg minutes~8000, the flow of ozone for the standard milliliters of 5000 standard milliliters/minute~3000/point Clock, air pressure are the support of 300 supports~600, and temperature is 400 degrees Celsius~600 degrees Celsius；In addition, the deposition gases can also include： Nitrogen, oxygen and helium, the flow of nitrogen are 1000 standard milliliters/minute~10000 standard milliliters/minute, the flow of oxygen For 0 standard milliliters/minute~5000 standard milliliters/minute, the flow of helium is the standard of 5000 standard milliliters/minute~20000 Ml/min.
Fig. 8 is refer to, after dielectric layer 203 is formed, removes the stop-layer 202 at the top of dummy gate layer 211, until exposure Untill going out the top surface of dummy gate layer 211.
The technique for removing dummy gate layer 211 is dry etch process or wet-etching technology.In the present embodiment, go It is described dry because the material of the dummy gate layer 211 is polysilicon except the technique of pseudo- gate dielectric layer 211 is dry etch process The etching gas of method etching technics include the mixture of chlorine, helium, hydrogen bromide or helium and oxygen.In another embodiment In, the technique for removing dummy gate layer 211 is wet-etching technology, and etching liquid includes TMAH, the tetramethyl hydrogen Mass percent concentration of the amine-oxides in etching liquid is 2%~4%, and etching temperature is 50 DEG C~90 DEG C.
Described in the technique of the removal dummy gate layer 211 can cause to pseudo- gate dielectric layer 210, make the pseudo- gate medium The thickness of layer 210 is difficult to keep uniformly accurate；Moreover, the formation process of the pseudo- gate dielectric layer 210 is thermal oxidation technology, make institute It is larger to state the equivalent oxide thickness of pseudo- gate dielectric layer 210, the process requirements of high-K metal gate transistor can not be met.Therefore, exist After removing dummy gate layer 211, also need to remove the pseudo- gate dielectric layer 210.
Fig. 9 is refer to, after the stop-layer 202 at the top of dummy gate layer 211 is removed, removes dummy gate layer 211（Such as Fig. 8 It is shown）With pseudo- gate dielectric layer 210（As shown in Figure 8）, untill the surface of substrate 200 is exposed, the shape in the dielectric layer 203 Into opening 204.
The technique for removing pseudo- gate dielectric layer 210 is wet-etching technology or dry etch process.In the present embodiment, remove The technique of pseudo- gate dielectric layer 210 is dry etch process, described dry because the material of the pseudo- gate dielectric layer 210 is silica The gas of method etching technics includes CHF3、CF4, one or more combinations in HF.In another embodiment, pseudo- gate medium is removed The technique of layer 210 is wet-etching technology, and etching liquid includes hydrofluoric acid.
Because the material of the dielectric layer 203 is also silica, therefore in the process for removing the pseudo- gate dielectric layer 210 In, the dielectric layer 203 can also be etched, and make the thickness of the dielectric layer 203 can accordingly reduce as the top of stop-layer 202 The position flushed.Simultaneously as there are Doped ions in the stop-layer 202, carry the Etch selectivity of the stop-layer 202 Height, it is extremely low to the etch rate of the stop-layer 202 in the technique of the pseudo- gate dielectric layer 210 of etching, therefore the stop-layer 202 will not be damaged by etching technics, the pattern of the stop-layer 202 and size is kept stable, the stop-layer 202 Height will not reduce.Therefore can ensure after gate dielectric layer 210 is removed, the dielectric layer 203 can be neat with stop-layer 202 It is flat, then, will not be at the top of stop-layer 202 and the material of the remained on surface metal gate of dielectric layer 203 when being subsequently formed grid layer.
Figure 10 is refer to, in the surface of dielectric layer 203 and opening 204（As shown in Figure 9）Side wall and lower surface deposition Gate dielectric film 205；The gate electrode film 206 of filling full gate mouth 204 is deposited on the surface of gate dielectric film 205.
The material of the gate dielectric film 205 is high K dielectric material, the high K dielectric material include hafnium oxide, zirconium oxide, Hafnium silicon oxide, lanthana, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium or aluminum oxide. The formation process of the gate dielectric film 205 is chemical vapor deposition method or physical gas-phase deposition.
In order to improve the binding ability between gate dielectric film 205 and substrate 200, before the gate dielectric film 205 is formed, Cushion oxide layer 207 is formed in the side wall and lower surface of the surface of dielectric layer 203 and opening 204, the gate dielectric film 205 is formed In the surface of liner oxide film 207.The material of the liner oxidation silicon fiml 207 is silica, the liner oxide film 207 Formation process is chemical vapor deposition method.And the not only thickness of liner oxide film 207 for using chemical vapor deposition method to be formed Uniformly, and equivalent electrical thickness is relatively low, the technical need of compound high-K metal gate transistor.
The material of the gate electrode film 206 is metal, and the metal includes copper, tungsten or aluminium, the formation work of the gate electrode film 206 Skill is chemical vapor deposition method, physical gas-phase deposition or electroplating technology.In one embodiment, in order to adjust what is formed The threshold voltage of transistor, before the gate electrode film 206 is formed, work-function layer can be formed on the surface of gate dielectric film 205. The material of the work-function layer is conductive material, for adjusting the threshold voltage of transistor, and the material root of the work-function layer According to the type selecting of the transistor of required formation, work function value is set to be more suitable for forming PMOS transistor or nmos pass transistor.
In other embodiments, in order to prevent gate dielectric film 205 of the metal material of gate electrode film 206 to high K dielectric material Interior diffusion, before the good gate electrode film 206 of work-function layer is formed, barrier layer, the barrier layer can be formed on the surface of gate dielectric film 205 Material be titanium, titanium nitride, tantalum, one or more combinations in tantalum nitride, the formation process on the barrier layer is chemical gaseous phase Depositing operation.
Figure 11 is refer to, the gate electrode film 206 is planarized using CMP process（As shown in Figure 9）And gate medium Film 205（As shown in Figure 9）, untill the surface of dielectric layer 203 is exposed, in the opening 204（As shown in Figure 9）Interior formation grid Dielectric layer 205a and grid layer 206a, the gate dielectric layer 205a are located at the side wall and lower surface of opening 204, the grid layer 206a is located at gate dielectric layer 205a surfaces and forms the full opening 204 of filling.
In the present embodiment, due to also having liner oxide film 207 between gate dielectric film 205 and substrate 200（Such as Fig. 9 institutes Show）, therefore liner oxidation layer 207a is formed between gate dielectric layer 205a and 204 side walls of opening and lower surface.
The CMP process is used for liner oxide film 207, the gate dielectric film 205 for removing the surface of dielectric layer 203 With gate electrode film 206, formed gate dielectric layer 205a and grid layer 206a is set only to be formed in opening 204.Due to the medium The surface of layer 203 and stop-layer 202 can keep flushing, therefore the surface of the dielectric layer 203 and stop-layer 202 is flat, In the CMP process, the material of gate dielectric film 205 and gate electrode film 206 will not residue in the surface of dielectric layer 203 or The top of stop-layer 202, it can avoid and produce leakage current because metal material remains at the top of grid layer 206a, so as to ensure that The stable performance of the transistor formed.
In the present embodiment, stop-layer is formed in the substrate and dummy gate structure surface, there is doping in the stop-layer Ion, the dielectric layer surface being subsequently formed flush with the stopping layer surface at the top of dummy gate layer.In order to remove dummy gate layer With pseudo- gate dielectric layer, it is necessary to remove the stop-layer at the top of dummy gate layer first, then positioned at the stopping of dummy gate structure sidewall surfaces Layer top flushes with dummy gate layer surface, and the dielectric layer surface is higher than at the top of stop-layer and dummy gate layer surface.Removing After dummy gate layer, during removing pseudo- gate dielectric layer, due to having Doped ions in the stop-layer, make the etching of stop-layer Rate reduction, the top surface of the stop-layer will not be cut down；Meanwhile the surface of the dielectric layer is removing pseudo- gate medium Accordingly reduced during layer, until being flushed with the top surface of the stop-layer.Therefore, remove the pseudo- gate dielectric layer it Afterwards, the stop-layer and dielectric layer surface can keep flat, and the grid layer and the material of gate dielectric layer being subsequently formed are not easy residual Stay in stop-layer and dielectric layer surface, ensure that formed transistor performance is stable；Moreover, without the formation to transistor Cheng Jinhang, which excessively changes, can reach the effect for improving transistor performance.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute The scope of restriction is defined.

Claims (15)

  1. A kind of 1. forming method of transistor, it is characterised in that including：
    Substrate is provided, the substrate surface has dummy gate structure, and the dummy gate structure includes：Positioned at the pseudo- grid of substrate surface Dielectric layer and the dummy gate layer positioned at pseudo- gate dielectric layer surface；
    Stop-layer is formed in the substrate and dummy gate structure surface, there is Doped ions, the stop-layer in the stop-layer Material be silicon nitride, the Doped ions are carbon ion；
    Dielectric layer is formed in the stopping layer surface, the dielectric layer surface and the stopping layer surface at the top of dummy gate layer are neat It is flat；
    Stop-layer, dummy gate layer and the pseudo- gate dielectric layer at the top of dummy gate layer are removed, opening is formed in the dielectric layer；
    Gate dielectric layer is formed in the opening and grid layer, the gate dielectric layer are located at the side wall and lower surface of opening, institute Grid layer is stated to be located at gate dielectric layer surface and form the full opening of filling.
  2. 2. the forming method of transistor as claimed in claim 1, it is characterised in that Doped ions in the stop-layer it is dense Spend for 0.5E15 atoms/square centimeter~12E15 atoms/square centimeter.
  3. 3. the forming method of transistor as claimed in claim 1, it is characterised in that the Doped ions are adulterated in stop-layer Technique be ion implantation technology or doping process in situ.
  4. 4. the forming method of transistor as claimed in claim 3, it is characterised in that when adulterated in stop-layer it is described adulterate from When the technique of son is ion implantation technology, Implantation Energy is 200 electron-volts~50 kilo electron volts.
  5. 5. the forming method of transistor as claimed in claim 1, it is characterised in that remove dummy gate layer at the top of stop-layer, Dummy gate layer and the technique of pseudo- gate dielectric layer include：The stop-layer at the top of dummy gate layer is etched, until exposing dummy gate layer top Untill portion surface；After the stop-layer at the top of etching dummy gate layer, the dummy gate layer and pseudo- gate dielectric layer are etched, until sudden and violent Untill exposing substrate surface.
  6. 6. the forming method of transistor as claimed in claim 1, it is characterised in that the material of the pseudo- gate dielectric layer is oxidation Silicon, the material of the dummy gate layer is polysilicon.
  7. 7. the forming method of transistor as claimed in claim 6, it is characterised in that the formation process bag of the pseudo- gate dielectric layer Include thermal oxidation technology.
  8. 8. the forming method of transistor as claimed in claim 6, it is characterised in that the technique for removing pseudo- gate dielectric layer is wet method Etching technics or dry etch process.
  9. 9. the forming method of transistor as claimed in claim 1, it is characterised in that also include：Formed before gate dielectric layer, The side wall and lower surface of the opening form cushion oxide layer, and the gate dielectric layer is formed at the liner oxidation layer surface.
  10. 10. the forming method of transistor as claimed in claim 9, it is characterised in that the material of the pad silicon oxide layer is Silica, the formation process of the cushion oxide layer is chemical vapor deposition method.
  11. 11. the forming method of transistor as claimed in claim 1, it is characterised in that the gate dielectric layer and gate electrode layer Formation process includes：In dielectric layer surface and side wall and lower surface the deposition gate dielectric film of opening；On gate dielectric film surface The gate electrode film of deposition filling full gate mouth；The gate electrode film and gate dielectric film are planarized using CMP process, until sudden and violent Untill exposing dielectric layer surface, the gate electrode film forms grid layer, and the gate dielectric film forms gate dielectric layer.
  12. 12. the forming method of transistor as claimed in claim 1, it is characterised in that the material of the gate dielectric layer is situated between for high K Material, the material of the grid layer is metal.
  13. 13. the forming method of transistor as claimed in claim 1, it is characterised in that the dummy gate structure also includes：It is located at The side wall of the sidewall surfaces and substrate surface of the dummy gate layer and pseudo- gate dielectric layer both sides.
  14. 14. the forming method of transistor as claimed in claim 1, it is characterised in that the material of the dielectric layer is silica, The formation process of the dielectric layer includes：Stopping layer surface deposition medium film；Institute is planarized using CMP process Plasma membrane is given an account of, until exposing the stop-layer of dummy gate layer top surface, forms dielectric layer.
  15. 15. the forming method of transistor as claimed in claim 1, it is characterised in that also include：Before stop-layer is formed, Source region and drain region are formed in the substrate of the dummy gate structure both sides.
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