CN106328604B - 芯片封装 - Google Patents

芯片封装 Download PDF

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Publication number
CN106328604B
CN106328604B CN201610191287.XA CN201610191287A CN106328604B CN 106328604 B CN106328604 B CN 106328604B CN 201610191287 A CN201610191287 A CN 201610191287A CN 106328604 B CN106328604 B CN 106328604B
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layer
chip
dielectric material
chip package
copper
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CN106328604A (zh
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卓尔·赫尔维茨
黄士辅
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Zhuhai Yueya Semiconductor Co ltd
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Zhuhai Yueya Semiconductor Co ltd
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Abstract

一种嵌入式芯片封装，其包括芯片，所述芯片具有在钝化层中的芯片接触焊盘，所述芯片接触焊盘通过粘附/阻挡层连接至特征层的第一面，从所述特征层的第二面延伸出通孔柱层，所述芯片、特征层和通孔柱层被介电材料包封。

Description

芯片封装
技术领域
本发明涉及电子芯片封装及其制造方法。
背景技术
消费电子产品，例如计算机和电信设备，包含有集成电路芯片。
实现芯片与外界连接的常规方法是将IC基板作为芯片封装的一部分。封装芯片具有诸如球栅阵列BGA或触点栅格阵列LGA的连接件，用于连接到印刷电路板PCB等基板上，而这些基板则连接其它元件。
IC基板要求具有高平整度、高强度和抗翘曲性以确保与PCB及其它基础基板具有良好的接触。具体而言，对于IC基板和芯片封装的总体要求是可靠性和合适的电气性能、厚度、硬度、平整度，良好的散热性以及有竞争力的单价。
引线框架(lead frame)是一种完善且常见的芯片封装类型，其价格相对低廉并且能够实现IC电路与外界连接。引线框架使用延伸出壳体外的金属引线。引线框架技术回到了DIP芯片的初期，但仍然被广泛应用于许多种封装中。
引线框架作为IC封装的“骨架”，其在芯片组装成最终产品的过程中为芯片提供机械支撑。引线框架包括芯片附着其上的芯片焊盘以及作为连接至外界的外部电连接装置的引线。芯片经由导线通过导线接合或带式自动接合的方式连接至引线。
在利用连接导线连接至引线框架后，芯片被称为模塑料的塑料保护材料覆盖。
用于制造更先进的多层基板的技术包括连接焊盘的层或嵌入介电材料内的特征结构。提供穿过介电材料的通孔，用以将不同层中的特征结构电连接在一起。
用于制造此类通孔的一种方法是钻填法，其中通常利用激光钻出穿过介电材料的孔，并且利用导电材料例如铜来填充该孔以形成通孔。
制造通孔的另一种方法是通过在适当波长的光(通常是紫外光)下选择性曝光光刻胶形成的图案内沉积铜或其它金属，其中通过在灯下经由模版选择性曝光形成图案或利用激光划线创建图案。这种在光刻胶显影形成的图案中进行电镀的技术称为“图案镀覆”。随后移除光刻胶，并且在直立的通孔柱上层压介电材料，该介电材料优选为聚合物浸渍增强玻璃纤维垫预浸料。
在图案镀覆中，首先沉积种子层。然后在其上沉积光刻胶层并随后曝光以创建图案，其中光刻胶被选择性移除以形成暴露出种子层的沟槽。通过在光刻胶沟槽中沉积铜而形成通孔柱。随后移除残余的光刻胶，蚀刻掉种子层，并且在其上及其周围再次层压通常为聚合物浸渍玻璃纤维垫预浸料的介电材料以包围通孔柱。然后可以采用各种技术和工艺来减薄介电材料，将其平坦化，并暴露出通孔柱的顶部，由此允许导电连接至接地面或参考面，用于在其上构建下一个金属层。可以在其上沉积具有金属导体和通孔柱的后续层，通过重复该过程来构建所期望的多层结构。
在一个可选但密切相关的下文称为“面板镀覆”的技术中，在基板上沉积金属或合金的连续层。在其上表面上沉积光刻胶层并在光刻胶中显影出图案。随后，将被显影的光刻胶选择性剥除，选择性地暴露出其下方的金属，该暴露的金属可以随后被蚀刻掉。未显影光刻胶保护其下方的金属不被蚀刻，并且留下直立的特征结构和通孔的图案。在未显影光刻胶被剥除之后，可以在直立的铜特征结构和/或通孔柱上及其周围层压介电材料，例如聚合物浸渍玻璃纤维垫。在其它变化方案中，未显影光刻胶图案被剥除，保留显影光刻胶作为掩膜。
通过图案镀覆或面板镀覆方法形成的通孔层，例如上文所述的那些，通常被称为“通孔柱”。特征层可以采用类似的技术来制造。
一种制造高密度互连的灵活技术是构建由介电基质中的金属通孔或特征结构构成的图案或面板镀覆的多层结构。用于通孔和特征结构的金属可以是铜，并且介电材料可以由纤维增强聚合物基质构成。通常，采用具有高玻璃化转变温度(Tg)的聚合物，例如聚酰亚胺。这些互连可以是有芯的或无芯的，并且可以包括用于堆叠元件的空腔。它们可以具有奇数或偶数的层数。授予Amitec Advanced Multilayer Interconnect TechnologiesLtd.的在先专利，例如Hurwitz等人的题为“Advanced Multilayer Coreless SupportStructures and Method for their Fabrication”的US 7,682,972中描述的实施技术公开了一种制造自支持膜的方法，所述膜包括在介电材料中的通孔阵列，用作构建优良电子支撑结构的构造前体。该方法包括在牺牲载体上的介电材料围绕物中制造导电通孔膜以及从牺牲载体上分离所述膜以形成一个自支持的层压阵列的步骤。可以通过将该层压阵列减薄和平坦化并随后将通孔端子化来形成基于该自支持膜的电子基板。该出版物通过引用全文并入本文。
Hurwitz等人的题为“Integrated Circuit Support Structures and theirFabrication”的US 7,635,641描述了一种制造电子件的方法，包括以下步骤： (A)选择第一基层；(B)在第一基层上沉积第一抗蚀阻挡层；(C)构建由交替的导电层和绝缘层构成的第一半堆叠体，导电层经由穿过绝缘层的通孔互连；(D)在第一半堆叠体上施加第二基层；(E)在第二基层上施加光刻胶保护涂层；(F)蚀刻掉第一基层；(G)移除光刻胶保护涂层；(H)移除第一抗蚀阻挡层；(Ⅰ)构建由交替的导电层和绝缘层构成的第二半堆叠体，导电层经由穿过绝缘层的通孔互连，其中第二半堆叠体具有与第一半堆叠体基本对称的层；(J)在由交替的导电层和绝缘层构成的第二半堆叠体上施加绝缘层；(K)移除第二基层；和(L)通过在堆叠体的外表面上暴露出通孔端部并对其施加端子来对基板进行端子化。该出版物通过引用全文并入本文。
多层基板实现了更高密度的互连并且被用于更为复杂的IC芯片。它们比简单的单层引线框架更为昂贵，并且对于许多电子应用而言，更经济的引线框架才是适用的。
即使用于封装相对简单的芯片，尽管单层就足够，但是引线框架技术仍有其局限性。芯片通过导线接合连接至引线框架，连接导线越长则导线断裂、产生短路从而导致失效的危险性就越高。此外，导线在一起排列得越紧密，则短路的可能性就越大。
介电材料中的通孔柱方法适合用于多层基板，但通常过于单薄而无法应用于单层中，因为应该认识到，翘曲和弯曲会导致接触不良、不可靠和短路。
Hurwitz等人的题为“Single Layer Coreless Substrate”的US 8,866,286描述了一种电子芯片封装，包括与插件布线层接合的至少一个芯片，所述插件布线层包括布线层和通孔柱层，其中通孔柱层被介电材料包围，介电材料包括在聚合物树脂中的玻璃纤维，并且芯片和布线层嵌入在第二介电材料层中，该第二介电材料层包封芯片和布线层。在这种封装技术中，通孔柱的铜端部与介电材料齐平。
该封装相当坚固，但是可能会过热。此外，这种封装可能会由于导线接合而导致具有杂散电感，并且可能会由于组装过程以及芯片附着、导线接合和成型所需的材料导致制造成本高昂。
仍然存在对于薄、可靠且低成本的芯片封装的需求，本发明的实施方案满足了这一需求。
发明内容
本发明的实施方案涉及提供一种新型芯片封装解决方案。
本发明第一方面涉及一种嵌入式芯片封装，其包括芯片，所述芯片具有在钝化层中的芯片接触焊盘，所述芯片接触焊盘通过粘附/阻挡层连接至特征层的第一面，从所述特征层的第二面延伸出通孔柱，所述芯片、特征层和通孔柱被介电材料包封。
通常，所述芯片接触焊盘包括铝。
通常，所述钝化层包括PI(聚酰亚胺)或SiN。
一般而言，所述粘附/阻挡层选自Ti/Cu、Ti/W/Cu、Ti/Ta/Cu、Cr/Cu、 Ni/Cu和Cr/Ni/Cu。
通常，所述粘附/阻挡层的厚度为0.05微米至1微米。
通常，所述特征层包括铜。
通常，所述特征层的厚度为1微米至25微米。
在一些实施方案中，所述特征层具有扇出形式。
在一些实施方案中，所述特征层具有扇入形式。
在一些实施方案中，所述芯片和通孔柱嵌入在不同的聚合物介电材料内。
在一些实施方案中，通孔柱层提供焊盘的栅格阵列，用作芯片与基板连接的接触。
任选地，所述基板是印刷电路板。
任选地，所述基板是用于制造封装上封装(PoP)的封装。
通常，根据工业标准将所述焊盘栅格阵列端子化。
在一些实施方案中，通孔柱的栅格阵列延伸超出介电材料至多10微米或是与介电材料齐平，从而提供LGA焊盘。
任选地，通孔柱的栅格阵列利用选自Ni/Au、ENIG或ENEIG的端子进行端子化。
在一些实施方案中，通孔柱的栅格阵列凹陷低于介电材料至多10微米或者与介电材料齐平，由此提供BGA焊盘。
在一些实施方案中，通孔柱的栅格阵列利用有机保焊剂(OSP)进行端子化。
本发明第二方面涉及一种制造如本文所述的新型芯片封装的方法，包括：
·获得由聚合物框架包围的芯片插座栅格；
·将所述芯片插座栅格放置在胶带上；
·将芯片面朝下(倒装芯片)放入栅格的插座中；
·在所述芯片和栅格上层压介电材料；
·在所述介电材料上施加载体；
·沉积粘附/阻挡层，所述粘附/阻挡层包括选自钛、钽、钨、铬和/或镍中的至少其一，随后在新暴露的表面上沉积铜种子层；
·施加第一光刻胶层，并显影出具有特征层的图案；
·在所述图案中电镀铜，形成特征结构；
·剥除所述第一光刻胶层；
·施加第二光刻胶层，并将其图案化形成通孔柱图案；
·在所述通孔柱图案中电镀铜以形成通孔柱；
·剥除第二光刻胶层；
·蚀刻掉粘附/阻挡层和铜种子层的暴露部分；
·施加介电材料阻挡层以覆盖铜特征结构、通孔柱和芯片的底面；
·移除载体；
·在芯片阵列的背面上层压黑色介电材料薄层；
·减薄介电材料以暴露出铜通孔柱；
·施加端子；和
·将所述栅格切割成独立的封装芯片。
·任选地，芯片阵列被定位在每个插座内。
在一个变型的制造路线中，将其上具有芯片阵列的晶片定位在每个插座内。
在一些实施方案中，铜通孔柱包括LGA(触点栅格阵列)并且其特征在于以下限制条件中的至少其一：
·正方形或长方形的形状；
·外表面镀有最终金属镀层，包括化学镀镍/化学镀钯/浸金(ENEPIG) 或化学镀镍/浸金(ENIG)或电解镍和金(Ni/Au)的端子化技术，以及
·任选从周围介电材料突起至多10微米。
在一些实施方案中，铜通孔柱包括焊盘BGA(球栅阵列)，其特征在于以下至少其一：
·相对于周围介电材料凹陷至多10微米；
·具有圆形端部的圆柱体形状，以易于被焊料润湿；和
·涂有OSP(有机保焊剂)。
通常，在所述黑色介电材料上进行激光标记。
附图说明
为了更好地理解本发明并示出本发明的实施方式，纯粹以举例的方式参照附图。
现在具体参照附图，必须强调的是，具体图示仅为示例且出于示意性讨论本发明优选实施方案的目的，提供图示的原因是确信附图是最有用且易于理解本发明的原理和概念的说明。就此而言，没有试图将本发明的结构细节以超出对本发明基本理解所必需的详细程度来图示；参照附图的说明使本领域技术人员能够知晓本发明的几种实施方式可如何实施。在附图中：
图1是根据一个实施方案的电子芯片封装的简化截面图，其中实现封装芯片与基板通过触点栅格阵列(LGA)的连接；
图2是根据一个实施方案的电子芯片封装的简化截面图，其中实现封装芯片与基板通过球栅阵列(BGA)的连接；
图3是示出图1的电子芯片封装的制造方法的流程图；
图3(a)-3(u)是对应于图3流程图的各个步骤的中间结构的附属侧视图；
在各个附图中，相同的附图标记指示相同的要素。
术语“微米”是指1x10-6米，并可表示为“μm”。
具体实施方式
在下文的说明中，所涉及的是支撑结构，其由介电材料中的金属通孔，特别是在聚合物基质中的铜通孔柱构成，所述介电材料例如是玻璃纤维增强的聚酰亚胺、环氧树脂或BT(双马来酰亚胺/三嗪)、聚苯醚(PPE)或其共混物。
参照图1，示出根据一个实施方案的电子芯片封装的简化截面图，该封装实现了芯片10与基板通过触点栅格阵列(LGA)20、22、24的连接。
电子芯片封装8包括芯片10以及在钝化层14中的铝柱12，钝化层14 包含PI或氮化硅。
芯片10和在钝化层14中的铝柱12通过层压第一介电材料16而被包封，第一介电材料16具有聚合物基质，例如聚酰亚胺、环氧树脂或BT(双马来酰亚胺/三嗪)、聚苯醚(PPE)、聚苯醚(PPO)或它们的共混物，该聚合物基质作为膜提供或者作为玻璃纤维增强预浸料提供以增加强度。
焊盘18与铝柱12连接。
在焊盘18的设置有IC芯片10的一面相反的另一面上制造铜柱层20、 22、24。
有用的是，焊盘18扇出，并且这些柱22、24中的一个或多个设置为超出IC芯片10的周边，这通常称为扇出构造，以便于连接到基板，如具有较大规模触点的印刷电路板。
这些柱20中的一个或多个可以是芯片下方的大柱，它们除了提供连接选定的柱12的电连接外，还可以将多个柱12连接到一起，也可以接地，还用作散热器，带走芯片10的热量并使其在大体积上耗散。应当指出的是，介电材料16、26通常是良好的热绝缘体，即差的热导体，因此倒装芯片构造会遭受过热，从而引起数据损坏或噪声。
作为扇出构造的替代，应该认识到在技术上可以根据需要提供扇入构造。此外，在切割之前，如果加工的是“在晶片上”的多个芯片而不是独立芯片，则通常不可能采用扇出构造。
焊盘18和柱20、22、24可以包封在介电材料26中，介电材料26可以是与包封芯片10的介电材料16不同的介电材料。可以在芯片封装8上层压黑色介电材料薄层28以利于激光标记的可视性。黑色介电材料层28可以作为预浸料或作为聚合物膜提供。
为了利用触点栅格阵列(LGA)连接到基板如印刷电路板(PCB)，柱 20、22、24通常为正方形或长方形，不过也可以具有其它形状，例如可以是圆形的。
为了易于附着到基板，柱20、22、24的端部可突起超出介电材料至多 10微米。柱20、22、24的暴露端部通常在其外表面上涂覆最终金属镀层 30，包括电解Ni/Au(有时称为化学镀镍浸金)或Ni/Pd/Au(在金的下方和镍的上方具有钯层)，该工艺称为ENEPIG。
参照图2，示出根据一个实施方案的电子芯片封装108的第二简化截面图，该封装实现了将芯片110与基板通过球栅阵列(BGA)120、122、124 连接。
电子芯片封装108包括芯片110以及在钝化层114中的铝柱112，该钝化层114包含PI或SiN。
芯片110和在钝化层114中的铝柱112通过层压第一介电材料116而被包封，第一介电材料16具有聚合物基质，例如聚酰亚胺、环氧树脂或BT (双马来酰亚胺/三嗪)、聚苯醚(PPE)、聚苯醚(PPO)或它们的共混物，该聚合物基质作为膜提供或者作为玻璃纤维增强预浸料提供以增加强度。
焊盘118连接铝柱112。
在焊盘118的设置有IC芯片110的一面相反的另一面上制造铜柱层 120、122、124。
有用的是，焊盘118扇出，并且这些柱122、124中的一个或多个设置为超出IC芯片110的周边，这通常称为扇出构造，以便于连接到基板，如具有较大规模触点的印刷电路板。这些柱120中的一个或多个可以是芯片下方的大柱，它们除了提供连接选定的柱112的电连接外，还可以将多个柱112连接到一起，也可以接地，还用作散热器，带走芯片110的热量并使其在大体积上耗散。应当指出的是，介电材料116、126通常是良好的热绝缘体，即差的热导体，因此倒装芯片构造会遭受过热，从而引起数据损坏或噪声。
作为扇出构造的替代，应该认识到在技术上可以根据需要提供扇入构造。此外，在切割之前，如果多个芯片在晶片上被封装和端子化，则通常不可能采用扇出构造。
焊盘118和柱120、122、124可以包封在介电材料126中，介电材料 126可以是与包封芯片110的介电材料116不同的介电材料。可以在芯片封装108上层压黑色介电材料薄层128以利于激光标记的可视性。黑色介电材料层128可以作为预浸料或作为聚合物膜提供。
为了利用球栅阵列(BGA)连接到基板如印刷电路板(PCB)，在焊料球附着至柱的端部并展开成半球形帽时，柱120、122、124通常是具有圆形截面的圆柱体以易于被焊料球润湿，然而，柱120、122、124也可以具有其它形状，例如可以是椭圆形、正方形或长方形。
与图1中的柱20、22、25的突起端部不同，对于BGA而言，柱120、 122、124的端部通常埋入介电材料126中，介电材料126延伸超出柱120、 122、124的端部至多10微米，这有助容纳后续施加在封装上的焊料球。为了防止在施加球栅阵列(BGA)之前焊料球变色，柱120、122、124的端部通常涂覆有有机保焊剂(OSP)130的表面涂层。
此外，应当指出的是，分别用作图1和图2中描述的封装中的LGA和 BGA焊盘的两个铜柱具有柱结构，通常具有至少200微米的宽度(或直径) 以及通常为15微米至50微米的厚度。铜柱的尺寸还可以有助于减少对于进出芯片的电流的直流电阻-由此增加了芯片的功能范围和整体封装可靠性- 尤其是对于高功率芯片的应用。
参照图3的流程图以及示出在聚合物框架4中的插座6的阵列和嵌入其中并连接的芯片10的截面的示意侧视图的图3(a)-3(u)，下文具体说明一种制造图1和2的结构的方法。
首先，获取由聚合物框架4包围的插座6的栅格-步骤3(a)。图3(a)示出一对相邻的插座。以下说明描述了将一对独立的芯片拾取和放置在单芯片插座中的处理过程。在实践中，可以对插座的大二维阵列一起处理。此外，在一个变型过程中，可利用单个插座来处理其上具有芯片栅格的晶片，随后可以将该晶片切割。
框架6可包括作为聚合物片材施加的聚合物，或者该聚合物可以是作为预浸料施加的玻璃纤维增强聚合物。框架6可具有一个或多个层。贯穿插座 4可以是冲压成型的，或者框架6可制造在牺牲铜桩上，牺牲铜桩随后被溶解而提供贯穿插座4。
珠海越亚的面板可为21"×25"，并且封装芯片可为5mm×5mm。因此，这种制造技术能够实现在单个面板上封装10000个芯片。
然而，应该理解的是，并不是面板的所有区块都需要相同尺寸的芯片插座。此外，不仅一个或多个区块可用于不同尺寸的插座以容纳不同尺寸的芯片，而且任意尺寸的任意子阵列可用于制造任意特定的芯片封装，所以尽管生产量很大，但是可以制造少量少批的芯片封装，使得能够为特定客户同时加工处理不同的芯片封装或为不同的客户制造不同的封装。因此，面板可包括用于容纳一种类型芯片的具有第一组尺寸的插座的至少一个区域以及具有用于容纳第二类型芯片的具有第二组尺寸的插座的第二区域。此外，在一个或多个晶片上的芯片阵列可设置在该面板中具有晶片尺寸大小的插座中，并且芯片可以随后被封装，然后进行晶片切割。
如图所示3(a)所示，每个芯片插座4被聚合物框架6包围。芯片插座栅格4放置在胶带30上-步骤3(b)，图3(b)。芯片10面朝下(倒装芯片)放置在框架6的插座4中-步骤3(c)，图3(c)，使得钝化层14中的铝触点12 (参见图1及图2)接触胶带30。
在芯片10和栅格6上层压介电材料16，通常为聚合物膜或纤维增强聚合物预浸料-步骤3(d)，图3(d)。
接着，在介电材料16上施加载体32-步骤3(e)，图3(e)。然后移除胶带 30-步骤3(f)，图3(f)，暴露出芯片触点12。在新暴露出的表面上沉积粘附层34，其包括钛、钽、钨、铬和/或镍中的至少其一，然后沉积铜种子层- 步骤3(g)，图3(g)。通常采用物理气相沉积(PVD)。粘附金属34的选择取决于聚合物6和钝化层14。粘附层34的典型组合是Ti/Cu、Ti/W/Cu、 Ti/Ta/Cu和Cr/Cu，厚度范围为0.05微米至1微米。
施加并图案化光刻胶层36以形成特征层-步骤3(h)，图3(h)。然后，在该图案中电镀铜以形成特征结构18-步骤3(i)，图3(i)。通常，特征结构 18的厚度范围为1微米至25微米。特征结构18可从芯片扇出或可向内扇入。某些特征结构可向外扇出并且某些特征结构可向内扇入。当加工处理晶片上的芯片阵列时，一般不可能采用扇出构造。
剥除光刻胶层36-步骤3(j)，图3(j)，并且施加第二光刻胶层38并图案化形成具有通孔柱的图案-步骤3(k)，图3(k)。在该图案中电镀铜以形成通孔柱层20、22、24-步骤3(l)，图3(l)。通常，通孔柱20的长度范围为15 微米至50微米。
剥除第二光刻胶层38-步骤3(m)，图3(m)，并且溅射具有Ti、Ta、 Ni、Cr、W中的一种或多种的粘附层34，随后蚀刻掉铜种子层3(n)。
接着，施加介电材料阻挡层26以覆盖铜特征结构18和通孔柱20、22、 24以及芯片10的底面-步骤3(o)，图3(o)。
接下来，移除载体32。通常，载体是铜并且简单地蚀刻掉。载体可以是两层铜载体，包括厚层和可剥离地附着在厚层上的薄层，在这种情况下，厚层被剥离而薄层被蚀刻掉-步骤3(p)，图3(p)。
聚合物可以通过抛光、研磨或通过化学机械抛光(CMP)进行减薄。
在该阶段，可以在框架6和芯片阵列10的背面层压黑色介电材料28的薄层(膜或预浸料)-步骤3(r)，图3(r)。
将光刻胶或其它聚合物介电材料26减薄，以暴露出铜通孔柱20、22、 24-步骤3(s)，图3(s)。
施加端子30-步骤3(t)，图3 (t)，然后将阵列分割(切割)成单个封装芯片8-步骤3(u)，图3(u)。
如图3(u)和图1所示，铜通孔柱20、22、24包括用作LGA(触点栅格阵列)的触点的焊盘栅格阵列和铜通孔柱20、22、24的上表面，铜通孔柱 20、22、24的上表面可与其周围的介电材料齐平图(3 u)或可突出超过介电材料背面至多约10微米(图1)，在其外表面上镀覆有最终金属镀层，包括化学镀镍/化学镀钯/浸金(ENEPIG)或化学镀镍/浸金(ENIG)或电解镍和金(Ni/Au)的端子化技术。在触点栅格阵列结构中，通孔柱20、22、24可以是正方形或长方形的。
综上，已经示出了制造图1结构的方法。其特征在于，芯片封装可以包括2种或3种不同的介电材料，框架6与填料16可以是相同或不同的聚合物或纤维增强聚合物，包围通孔柱柱26的介电材料是第三介电材料。
应当理解的是，由图3的方法得到的图3(u)所示的结构可以进一步改进，使得铜柱层包括用作BGA(球栅阵列)形式触点的焊盘栅格阵列。在这种实施方案中，如图2所示，铜通孔柱120、122、124的外表面可与周围的介电材料126齐平，或者可以从周围介电材料126的表面处凹陷至多10微米。用于BGA的通孔柱通常是具有圆形端部的圆柱体，以利于被焊料球润湿。
当构造为球栅阵列时，通孔柱端部通常涂覆有OSP 130(有机保焊剂)。
本领域技术人员将会认识到，本发明不限于上文中具体图示和描述的内容。而且，本发明的范围由所附权利要求限定，包括上文所述的各个技术特征的组合和子组合以及其变化和改进，本领域技术人员在阅读前述说明后将会预见到这样的组合、变化和改进。
在权利要求书中，术语“包括”及其变体例如“包含”、“含有”等是指所列举的组件被包括在内，但一般不排除其他组件。

Claims (23)

1.一种嵌入式芯片封装，其包括多个芯片插座栅格和聚合物框架，所述芯片插座栅格被所述聚合物框架包围，所述芯片插座栅格中的芯片具有在钝化层中的芯片接触焊盘，所述芯片接触焊盘通过粘附/阻挡层连接至特征层的第一面，从所述特征层的第二面延伸出通孔柱层，所述芯片、特征层和通孔柱层被介电材料包封,其中所述芯片和所述通孔柱层嵌入在不同的聚合物介电材料中。
2.如权利要求1所述的嵌入式芯片封装，其中所述芯片接触焊盘包括铝。
3.如权利要求1所述的嵌入式芯片封装，其中所述钝化层包括聚酰亚胺或SiN。
4.如权利要求1所述的嵌入式芯片封装，其中所述粘附/阻挡层选自Ti/Cu、Ti/W/Cu、Ti/Ta/Cu、Cr/Cu和Ni/Cr。
5.如权利要求4所述的嵌入式芯片封装，其中所述粘附/阻挡层的厚度范围为0.05～1微米。
6.如权利要求1所述的嵌入式芯片封装，其中所述特征层包括铜。
7.如权利要求6所述的嵌入式芯片封装，其中所述特征层的厚度范围为1～25微米。
8.如权利要求6所述的嵌入式芯片封装，其中所述通孔柱层的高度范围为15～50微米。
9.如权利要求1所述的嵌入式芯片封装，其中所述特征层具有扇出形式。
10.如权利要求1所述的嵌入式芯片封装，其中所述特征层具有扇入形式。
11.如权利要求1所述的嵌入式芯片封装，其中所述通孔柱层包括焊盘栅格阵列，所述焊盘栅格阵列用作连接所述芯片与基板的触点。
12.如权利要求11所述的嵌入式芯片封装，其中所述基板是印刷电路板。
13.如权利要求11所述的嵌入式芯片封装，其中所述基板是用于制造封装上封装的封装。
14.如权利要求11所述的嵌入式芯片封装，其中所述焊盘栅格阵列延伸超出介电材料至多10微米或者与所述介电材料齐平，从而提供LGA焊盘。
15.如权利要求14所述的嵌入式芯片封装，其中所述焊盘栅格阵列采用选自电解Ni/Au、ENIG或ENEIG的端子进行端子化。
16.如权利要求11所述的嵌入式芯片封装，其中所述焊盘栅格阵列凹陷低于所述介电材料至多10微米或者与所述介电材料齐平，从而提供BGA焊盘。
17.如权利要求16所述的嵌入式芯片封装，其中所述焊盘栅格阵列采用有机保焊剂OSP进行端子化。
18.一种制造嵌入式芯片封装的方法，包括：
·获得由聚合物框架包围的芯片插座栅格；
·将所述芯片插座栅格放置在胶带上；
·将芯片面朝下的倒装芯片放入所述芯片插座栅格的插座中；
·在所述芯片和芯片插座栅格上层压介电材料；
·在所述介电材料上施加载体；
·沉积粘附/阻挡层，所述粘附/阻挡层包括选自钛、钽、钨、铬和/或镍中的至少其一，随后在新暴露的表面上沉积铜种子层；
·施加第一光刻胶层，并显影出具有特征层的图案；
·在所述具有特征层的图案中电镀铜，形成铜特征结构；
·剥除所述第一光刻胶层；
·施加第二光刻胶层，并将其图案化形成通孔柱图案；
·在所述通孔柱图案中电镀铜以形成通孔柱；
·剥除所述第二光刻胶层；
·蚀刻掉所述粘附/阻挡层和所述铜种子层的暴露部分；
·施加介电材料阻挡层以覆盖所述铜特征结构、通孔柱和芯片的底面；
·移除载体；
·在芯片阵列的背面上层压黑色介电材料薄层；
·减薄所述介电材料阻挡层以暴露出铜通孔柱；
·施加端子；和
·将所述栅格切割成单独的封装芯片。
19.如权利要求18所述的方法，还包括激光标记所述黑色介电材料的附加步骤。
20.如权利要求18所述的方法，其中芯片阵列被定位在每个插座内。
21.如权利要求18所述的方法，其中其上具有芯片阵列的晶片被定位在每个插座内。
22.如权利要求18所述的方法，其中所述通孔柱包括触点栅格阵列LGA，其特征在于以下限制条件中的至少其一：
·正方形或长方形的形状；
·外表面镀有最终金属镀层，包括化学镀镍/化学镀钯/浸金或化学镀镍/浸金或电解镍和金的端子化技术，以及
·任选从周围介电材料突起至多10微米。
23.如权利要求18所述的方法，其中所述铜通孔柱包括球栅阵列BGA，其特征在于以下限制条件中的至少其一：
·相对于周围介电材料凹陷至多10微米；
·具有圆形端部的圆柱形状，以易于被焊料润湿；和
·涂有有机保焊剂OSP。
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