CN106299125B - A kind of Organic Thin Film Transistors and preparation method thereof - Google Patents
A kind of Organic Thin Film Transistors and preparation method thereof Download PDFInfo
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- CN106299125B CN106299125B CN201610956686.0A CN201610956686A CN106299125B CN 106299125 B CN106299125 B CN 106299125B CN 201610956686 A CN201610956686 A CN 201610956686A CN 106299125 B CN106299125 B CN 106299125B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/10—Deposition of organic active material
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/60—Forming conductive regions or layers, e.g. electrodes
Abstract
The invention discloses a kind of Organic Thin Film Transistors and preparation method thereof.The production method includes: to provide a substrate；Organic semiconductor patterns, the source drain pattern with two side contacts of organic semiconductor patterns are formed on substrate, wherein, organic semiconductor patterns include the first doped region contacted with source drain pattern and the second doped region far from source drain pattern, and the first doped region and the second doped region have different conductivity.By the above-mentioned means, the present invention can greatly improve the contact of source drain pattern and organic semiconductor patterns, and then reduce the electrical leakage problems in Organic Thin Film Transistors.
Description
Technical field
The present invention relates to field of liquid crystal display, more particularly to a kind of Organic Thin Film Transistors and preparation method thereof.
Background technique
In Organic Thin Film Transistors (OTFT), usually metal source drain pattern directly with organic semiconductor (OSC) layer
It directly contacts, metal source drain pattern increases metal work function by the method for monolayer surface self assembly (SAM), is allowed to and has
The HOMO level-density parameter of machine semiconductor layer.But SAM is used to handle, to improvement metal source drain pattern and organic semiconductor layer
Contact performance be limited so that the electric leakage in Organic Thin Film Transistors is larger.
Summary of the invention
The invention mainly solves the technical problem of providing a kind of Organic Thin Film Transistors and preparation method thereof, can be significantly
The contact of source drain pattern and organic semiconductor layer is improved, and then reduces the electrical leakage problems in Organic Thin Film Transistors.
In order to solve the above technical problems, one technical scheme adopted by the invention is that: a kind of Organic Thin Film Transistors is provided
Production method, the production method include: provide a substrate；Organic semiconductor patterns and organic semiconductor are formed on substrate
The source drain pattern of two side contacts of pattern, wherein organic semiconductor patterns include the first doping contacted with source drain pattern
Second doped region in area and separate source drain pattern, the first doped region and the second doped region have different conductivity；It is being formed
Have and forms the first insulating layer, gate pattern, signal transmssion line, second on organic semiconductor patterns and the substrate of source drain pattern
Insulating layer and pixel electrode.
Wherein, organic semiconductor patterns, the source drain pattern with two side contacts of organic semiconductor patterns are formed on substrate
The step of include: formed on substrate organic semiconductor layer, with the source drain patterns of two side contacts of organic semiconductor layer；It is formed
Cover the electrolyte thin film layer of organic semiconductor layer and source drain pattern；Auxiliary electrode is formed in electrolyte thin film layer,
In, the face position in the region that auxiliary electrode is arranged in source drain pattern and organic semiconductor layer is in contact；In auxiliary electrode and
Apply bias voltage between source drain pattern so that the conductive ion in electrolyte thin film layer flows into organic semiconductor layer, with shape
At the organic semiconductor patterns including the first doped region and the second doped region；Remove auxiliary electrode and electrolyte thin film layer.
Wherein, the material of electrolyte thin film layer is gel-type polymer electrolyte, full solid state polymer electrolyte, porous type
At least one of polymer dielectric and compound polymer electrolyte.
Wherein, the first insulating layer, grid figure are formed on the substrate for being formed with organic semiconductor patterns and source drain pattern
The step of case, signal transmssion line, second insulating layer and pixel electrode includes: to form covering organic semiconductor patterns and source/drain
First insulating layer of pattern, wherein the first insulating layer is provided with the first via hole for exposing a source drain pattern；Absolutely first
Gate pattern and signal transmssion line are formed in edge layer, wherein signal transmssion line passes through the first via hole and corresponding source drain pattern
Contact；Formed covering gate pattern and signal transmssion line second insulating layer, wherein second insulating layer be provided with expose it is another
Second via hole of source drain pattern；Form pixel electrode over the second dielectric, wherein pixel electrode by the second via hole with
Corresponding source drain pattern contact.
Wherein, the first insulating layer, grid figure are formed on the substrate for being formed with organic semiconductor patterns and source drain pattern
The step of case, signal transmssion line, second insulating layer and pixel electrode includes: to form covering organic semiconductor patterns and source/drain
First insulating layer of pattern, wherein the first insulating layer is provided with two the first mistakes for exposing corresponding source drain pattern respectively
Hole；Gate pattern and two bars transmission lines are formed on the first insulating layer, wherein two bars transmission lines pass through corresponding the
One via hole is contacted with source drain pattern；Form the second insulating layer of covering gate pattern and signal transmssion line, wherein second absolutely
Edge layer is provided with the second via hole for exposing a bars transmission line；Pixel electrode is formed over the second dielectric, wherein pixel
Electrode is contacted by the second via hole with corresponding signal transmssion line.
In order to solve the above technical problems, another technical solution used in the present invention is: providing a kind of organic thin-film transistor
Pipe, which includes substrate, organic semiconductor patterns and source drain pattern；Wherein, organic semiconductor patterns and
Source drain pattern is disposed on the substrate, two side contacts of source drain pattern and organic semiconductor patterns；Wherein, organic semiconductor
Pattern include the first doped region contacted with source drain pattern and far from source drain pattern the second doped region, the first doped region and
Second doped region has different conductivity.
Wherein, organic semiconductor patterns are coated on organic semiconductor layer by forming organic semiconductor layer on substrate
Electrolyte thin film layer prepares auxiliary electrode in electrolyte thin film layer, applies biasing between auxiliary electrode and source drain pattern
Voltage is formed.
Wherein, the material of electrolyte thin film layer is gel-type polymer electrolyte, full solid state polymer electrolyte, porous type
At least one of polymer dielectric and compound polymer electrolyte.
Wherein, thin film transistor (TFT) further comprise the first insulating layer, gate pattern, signal transmssion line, second insulating layer and
Pixel electrode；First insulating layer covers organic semiconductor patterns and source drain pattern, wherein the first insulating layer is provided with exposure
First via hole of a source drain pattern out；Gate pattern and signal transmssion line setting are on the first insulating layer, wherein signal passes
Defeated line is contacted by the first via hole with corresponding source drain pattern；Second insulating layer covers gate pattern and signal transmssion line,
In, second insulating layer is provided with the second via hole for exposing another source drain pattern；Pixel electrode is arranged in second insulating layer
On, wherein pixel electrode is contacted by the second via hole with corresponding source drain pattern.
Wherein, thin film transistor (TFT) further comprise the first insulating layer, gate pattern, signal transmssion line, second insulating layer and
Pixel electrode；First insulating layer covers organic semiconductor patterns and source drain pattern, wherein the first insulating layer is provided with exposure
Two the first via holes of corresponding source drain pattern out；Gate pattern and two bars transmission lines are arranged on the first insulating layer,
Wherein, two bars transmission lines are contacted by the first via hole with corresponding source drain pattern；Second insulating layer covers gate pattern
And signal transmssion line, wherein second insulating layer is provided with the second via hole for exposing a bars transmission line；Pixel electrode setting
Over the second dielectric, wherein pixel electrode is contacted by the second via hole with corresponding signal transmssion line.
The beneficial effects of the present invention are: being in contrast to the prior art, Organic Thin Film Transistors and its system of the invention
Make method by formed on substrate organic semiconductor patterns, with the source drain patterns of two side contacts of organic semiconductor patterns,
In, organic semiconductor patterns include the first doped region contacted with source drain pattern and the second doping far from source drain pattern
Area, the first doped region and the second doped region have different conductivity.By the above-mentioned means, the present invention can greatly improve source/
The contact of drain pattern and organic semiconductor patterns, and then reduce the electrical leakage problems in Organic Thin Film Transistors.
Detailed description of the invention
Fig. 1 is the flow diagram of the production method of the Organic Thin Film Transistors of first embodiment of the invention；
Fig. 2 is the flow diagram of the production method of the Organic Thin Film Transistors of second embodiment of the invention；
Fig. 2A -2E is the structural schematic diagram of the Organic Thin Film Transistors of production method shown in Fig. 2 in the production process；
Fig. 3 is the structural schematic diagram of Organic Thin Film Transistors made from production method shown in Fig. 2；
Fig. 4 is the flow diagram of the production method of the Organic Thin Film Transistors of third embodiment of the invention；
Fig. 4 A is the structural schematic diagram of the Organic Thin Film Transistors of production method shown in Fig. 4 in the production process；
Fig. 5 is the structural schematic diagram of Organic Thin Film Transistors made from production method shown in Fig. 4.
Specific embodiment
Some vocabulary is used in specification and claims to censure specific component, the skill in fields
Art personnel are, it is to be appreciated that manufacturer may call same component with different nouns.Present specification and claims
Not in such a way that the difference of title is as component is distinguished, but with the difference of component functionally as the base of differentiation
It is quasi-.The present invention is described in detail with reference to the accompanying drawings and examples.
Fig. 1 is the flow diagram of the production method of the Organic Thin Film Transistors of first embodiment of the invention.Such as Fig. 1 institute
Show, this method comprises the following steps:
Step S1: a substrate is provided.
Step S2: organic semiconductor patterns, the source/drain pole figure with two side contacts of organic semiconductor patterns are formed on substrate
Case, wherein organic semiconductor patterns include the first doped region contacted with source drain pattern and far from source drain pattern the
Two doped regions, the first doped region and the second doped region have different conductivity.
Step S3: the first insulating layer, grid are formed on the substrate for being formed with organic semiconductor patterns and source drain pattern
Pattern, signal transmssion line, second insulating layer and pixel electrode.
Fig. 2 is the flow diagram of the production method of the Organic Thin Film Transistors of second embodiment of the invention.Fig. 2A -2E is
The structural schematic diagram of the Organic Thin Film Transistors of production method shown in Fig. 2 in the production process.It is noted that if having substantially
It is identical as a result, method of the invention is not limited with process sequence shown in Fig. 2.As shown in Fig. 2, this method includes following step
It is rapid:
Step S101: a substrate is provided.
In step s101, substrate includes glass substrate, coated and cured flexible base board and sets on the glass substrate
Set the buffer layer on glass substrate and flexible base board.
Step S102: organic semiconductor layer, the source/drain pole figure with two side contacts of organic semiconductor layer are formed on substrate
Case.
In step s 102, organic semiconductor layer and source drain pattern pass through corresponding film forming and pattern definition system respectively
Journey is made.
It is the cross-section structure for being formed with the substrate of organic semiconductor layer and source drain pattern please also refer to Fig. 2A, Fig. 2A
Schematic diagram.As shown in Figure 2 A, organic semiconductor layer 140 and source drain pattern 130 are arranged on the substrate 100, source drain pattern
130 respectively with 140 liang of side contacts of organic semiconductor layer.
Step S103: the electrolyte thin film layer of covering organic semiconductor layer and source drain pattern is formed.
In step s 103, electrolyte thin film layer is coated on organic semiconductor layer and source drain pattern, wherein electrolysis
The material of matter film layer is gel-type polymer electrolyte, full solid state polymer electrolyte, porous type polymer dielectric and answers
At least one of mould assembly polymer dielectric.Preferably, electrolyte thin film layer is gel-type polymer electrolyte, and gel-type is poly-
Polymer electrolyte is made of polymer, plasticizer and different kinds of ions.
Step S104: auxiliary electrode is formed in electrolyte thin film layer, wherein auxiliary electrode is arranged in source drain pattern
The face position in the region being in contact with organic semiconductor layer.
Please also refer to Fig. 2 B, Fig. 2 B is the cross-section structure signal for being formed with the substrate of electrolyte thin film layer and auxiliary electrode
Figure.As shown in Figure 2 B, electrolyte thin film layer 150 covers organic semiconductor layer 140 and source drain pattern 130, auxiliary electrode 160
It is arranged in electrolyte thin film layer 150.Wherein, auxiliary electrode 160 is arranged in source drain pattern 130 and organic semiconductor layer 140
The face position in the region being in contact.
Step S105: apply bias voltage between auxiliary electrode and source drain pattern so that in electrolyte thin film layer
Conductive ion flows into organic semiconductor layer, to form the organic semiconductor patterns for including the first doped region and the second doped region.
In step s105, apply the bias voltage of scheduled voltage between auxiliary electrode and source drain pattern, then it is electric
Conductive ion in solution matter film layer can penetrate the interface of electrolyte thin film layer and organic semiconductor layer under the action of electric field,
Enter organic semiconductor layer and region that source drain pattern is in contact, wherein point of the organic semiconducting materials in the region
The free radical that will form electrification in subchain introduces the polaron of electrification, so that organic semiconductor layer and source/drain pole figure
The conductivity in the region that case is in contact is enhanced.
It changes for an angle, after the bias voltage for applying scheduled voltage between auxiliary electrode and source drain pattern, has
Machine semiconductor layer become include the first doped region and the second doped region organic semiconductor patterns, the conductivity of the first doped region is big
In the conductivity of the second doped region.Wherein, the first doped region is in contact with source drain pattern, and the second doped region is far from source/drain
Pattern and the second doped region are arranged between two the first doped regions.Wherein, the polaron of electrification is introduced in the first doped region,
So as to improve the contact of source drain pattern and organic semiconductor patterns, in addition, the polaron distribution gradient of electrification
That is the first doped region introduces impurity concentration gradient and effectively reduces organic thin-film transistor so as to prevent thermoelectron degradation effect
The electric leakage of pipe.In addition, the second doped region can be understood as it is equally undoped.
It will be understood to those skilled in the art that when bias voltage is greater than specific threshold, leading under this electric field action
Electron ion penetrate namely the doping process of organic semiconductor layer be it is irreversible, thus reached further promotion source/drain
The contact of pole figure case and organic semiconductor patterns and the purpose for further decreasing leakage current.
Please also refer to Fig. 2 C, Fig. 2 C is to form the organic semiconductor patterns including the first doped region and the second doped region
The schematic diagram of the section structure of substrate.As shown in Figure 2 C, apply predetermined voltage between auxiliary electrode 160 and source drain pattern 130
After the bias voltage of value, organic semiconductor layer 140 becomes including that the first doped region 141 and the second the organic of doped region 142 partly lead
Body pattern 140 ".Wherein, the first doped region 141 is in contact with source drain pattern 130, and the second doped region 142 is far from source/drain
Pattern 130 and the second doped region 142 are arranged between two the first doped regions 141.
Specifically, apply the bias voltage of scheduled voltage between auxiliary electrode 160 and source drain pattern 130
Circuit are as follows: the first power supply VG1One end connect with an auxiliary electrode 160, second source VG2One end and another auxiliary electrode 160
Connection, the first power supply VG1The other end, second source VG1The other end connect respectively with ground GND and a source drain pattern 130,
Wherein, the source drain pattern 130 and it is connected to the first power supply VG1Auxiliary electrode 160 be correspondingly arranged.Third power supply VDOne end
It is connect with another source drain pattern 130, third power supply VDThe other end with ground GND connect.
Wherein, as shown in Figure 2 C, as the first power supply VG1With second source VG2When identical, then the first doped region 141 and second
Doped region 142 is symmetrical；As the first power supply VG1With second source VG2When not identical, then due to forming 141 He of the first doped region
You are same for the potential barrier of second doped region 142, so that 142 asymmetric distribution of the first doped region 141 and the second doped region.This field
Technical staff be appreciated that in other embodiments, can also be with the first power supply VG1With second source VG2Timesharing accesses above-mentioned electricity
Lu Zhong, as long as the first doped region 141 can be formed and the second doped region 142 is within the scope of the present invention.
Step S106: remove auxiliary electrode and electrolyte thin film layer.
In step s 106, can be washed off with corresponding solvent or using etching method remove electrolyte thin film layer with
And the auxiliary electrode being arranged on.
Please also refer to Fig. 2 D, Fig. 2 D is the cross-section structure signal for removing the substrate after auxiliary electrode and electrolyte thin film layer
Figure.As shown in Figure 2 D, organic semiconductor patterns 140 " and source drain pattern 130 are arranged on the substrate 100, organic semiconductor figure
Case 140 " includes the first doped region 141 and the second doped region 142.
Step S107: the first insulating layer of covering organic semiconductor patterns and source drain pattern is formed, wherein first absolutely
Edge layer is provided with the first via hole for exposing a source drain pattern.
In step s 107, it is coated with the first insulating layer on organic semiconductor patterns and source drain pattern, uses etching
Method forms the first via hole in the first insulating layer.Wherein, the first insulating layer is organic grid dielectric layer, it is preferable that the first insulation
The material of layer is GI.
Step S108: forming gate pattern and signal transmssion line on the first insulating layer, and wherein signal transmssion line passes through the
One via hole is contacted with corresponding source drain pattern.
In step S108, gate pattern is formed using the method for vapor deposition or etching on the first insulating layer and signal transmits
Conducting wire.Preferably, the intermediate region of gate pattern and organic semiconductor patterns is correspondingly arranged.
Please also refer to Fig. 2 E, Fig. 2 E is to be formed with the substrate of the first insulating layer, gate pattern and signal transmssion line to cut open
Face structural schematic diagram.As shown in Figure 2 E, the first insulating layer 170 covering organic semiconductor patterns 140 " and source drain pattern 130,
First insulating layer 170 is provided with the first via hole 171 for exposing source drain pattern 130.Gate pattern 180 and signal transmssion line
181 are arranged on the first insulating layer 170, wherein gate pattern 180 is corresponding with the intermediate region of organic semiconductor patterns 140 " to be set
It sets, signal transmssion line 181 is contacted by the way that the first via hole 171 is corresponding with source drain pattern 130.
Step S109: the second insulating layer of covering gate pattern and signal transmssion line is formed, wherein second insulating layer setting
There is the second via hole for exposing another source drain pattern.
In step S109, second insulating layer includes inorganic passivation layer (PV layers) and organic planarization layer (PLN layers).It is specific next
It says, in the present embodiment, forms inorganic passivation layer using the method for vapor deposition first on gate pattern and signal transmssion line, then
It is coated with organic planarization layer on electrodeless passivation layer, is finally formed using the method for etching and runs through inorganic passivation layer, organic planarization layer
With the first insulating layer, while the second via hole of another source drain pattern is exposed.
Step S110: form pixel electrode over the second dielectric, wherein pixel electrode by the second via hole with it is corresponding
Source drain pattern contact.
In step s 110, the step of forming pixel electrode over the second dielectric includes: to pass through physical vaporous deposition
The pixel deposition electrode thin film layer on the substrate for be formed with second insulating layer；Yellow light system is successively implemented to pixel electrode film layer
Journey, wet etching processing procedure and photoresist removing processing procedure are to form pixel electrode.Wherein, the material of pixel electrode layer is preferably tin indium oxide,
Pixel electrode is contacted by the second via hole with another source drain pattern.
Since then, Organic Thin Film Transistors completes.
It is the structural schematic diagram of Organic Thin Film Transistors made from production method shown in Fig. 2 please also refer to Fig. 3, Fig. 3.Such as
Shown in Fig. 3, Organic Thin Film Transistors includes substrate 100, organic semiconductor patterns 140 ", the insulation of source drain pattern 130, first
Layer 170, gate pattern 180, signal transmssion line 181, second insulating layer 190 and pixel electrode 200.
Organic semiconductor patterns 140 " and source drain pattern 130 are arranged on the substrate 100, source drain pattern 130 with have
Two side contacts of machine semiconductor pattern 140 ".In the present embodiment, substrate 100 includes glass substrate, is coated on the glass substrate
And cured flexible base board and the buffer layer being arranged on glass substrate and flexible base board.
Wherein, organic semiconductor patterns 140 " include the first doped region 141 contacted with source drain pattern 130 and separate
Second doped region 142 of source drain pattern 130, the first doped region 141 and the second doped region 142 have different conductivity.Tool
For body, organic semiconductor patterns 140 " are coated with electricity by forming organic semiconductor layer on substrate on organic semiconductor layer
Matter film layer is solved, auxiliary electrode is prepared in electrolyte thin film layer, applies biased electrical between auxiliary electrode and source drain pattern
Swaging at.Preferably, the material of electrolyte thin film layer be gel-type polymer electrolyte, it is full solid state polymer electrolyte, porous
At least one of type polymer dielectric and compound polymer electrolyte.
The principle that first doped region 141 and the second doped region 142 are formed is: between auxiliary electrode and source drain pattern
Apply the bias voltage of scheduled voltage, then the conductive ion in electrolyte thin film layer can penetrate electrolysis under the action of electric field
The interface of matter film layer and organic semiconductor layer enters organic semiconductor layer and region that source drain pattern is in contact,
In, the free radical that will form electrification on the strand of the organic semiconducting materials in the region introduces the polaron of electrification,
To which formation has the first doped region and the second doped region of the polaron of the electrification of different number.Wherein, due to the first doping
The polaron quantity of the electrification introduced in area is more and distribution gradient, so that organic semiconductor layer and source drain pattern are in contact
The conductivity in region be enhanced, the second doped region can be understood as being equal to it is undoped so that being tied in Organic Thin Film Transistors
Maximum field position separated with the maximum current path in channel, to prevent thermoelectron degradation effect, effectively reduce organic
The electric leakage of thin film transistor (TFT).
First insulating layer 170 covers organic semiconductor patterns 140 " and source drain pattern 130, wherein the first insulating layer
170 are provided with the first via hole 171 for exposing a source drain pattern 130.In the present embodiment, the first insulating layer 170 is organic
Gate dielectric, it is preferable that the material of the first insulating layer is preferably GI.
Gate pattern 180 and signal transmssion line 181 are arranged on the first insulating layer 170, wherein signal transmssion line 181 is logical
The first via hole 171 is crossed to contact with corresponding source drain pattern 130.In this embodiment, it is preferred that gate pattern 180 with it is organic
The intermediate region of semiconductor pattern 140 " is correspondingly arranged.
Second insulating layer 190 covers gate pattern 180 and signal transmssion line 181, wherein second insulating layer 190 is provided with
Expose the second via hole 191 of another source drain pattern.In the present embodiment, second insulating layer 190 includes inorganic passivation layer
(PV layers) and the organic planarization layer being arranged on inorganic passivation layer (PLN layers).
Pixel electrode 200 be arranged in second insulating layer 190, wherein pixel electrode 200 by the second via hole 191 with it is right
The source drain pattern 130 answered contacts.
Fig. 4 is the flow diagram of the production method of the Organic Thin Film Transistors of third embodiment of the invention.Fig. 4 A is Fig. 4
The structural schematic diagram of the Organic Thin Film Transistors of shown production method in the production process.It is noted that if having substantial phase
With as a result, method of the invention is not limited with process sequence shown in Fig. 4.As shown in figure 4, this method includes following step
It is rapid:
Step S201: a substrate is provided.
Step S202: organic semiconductor layer, the source/drain pole figure with two side contacts of organic semiconductor layer are formed on substrate
Case.
Step S203: the electrolyte thin film layer of covering organic semiconductor layer and source drain pattern is formed.
Step S204: auxiliary electrode is formed in electrolyte thin film layer, wherein auxiliary electrode and source drain pattern and have
The region that machine semiconductor layer is in contact is correspondingly arranged.
Step S205: apply bias voltage between auxiliary electrode and source drain pattern so that in electrolyte thin film layer
Conductive ion flows into organic semiconductor layer to form the organic semiconductor patterns including the first doped region and the second doped region
Step S206: remove auxiliary electrode and electrolyte thin film layer.
In the present embodiment, step S201~step S206 shown in Fig. 4 and step S101~step S106 shown in Fig. 2
Identical, for the sake of brief, this will not be detailed here.
Step S207: the first insulating layer of covering organic semiconductor patterns and source drain pattern is formed, wherein first absolutely
Edge layer is provided with two the first via holes for exposing corresponding source drain pattern.
In step S207, it is coated with the first insulating layer on organic semiconductor patterns and source drain pattern, uses etching
Method forms two the first via holes in the first insulating layer.Wherein, the first insulating layer is organic grid dielectric layer, it is preferable that first
The material of insulating layer is GI.
Step S208: gate pattern and two bars transmission lines are formed on the first insulating layer, wherein the transmission of two bars
Line is contacted by corresponding first via hole with source drain pattern.
In step S208, gate pattern and two bars are formed using the method for vapor deposition or etching on the first insulating layer
Transfer wire.Preferably, the intermediate region of gate pattern and organic semiconductor patterns is correspondingly arranged.
Please also refer to Fig. 4 A, Fig. 4 A is to be formed with the substrate of the first insulating layer, gate pattern and signal transmssion line to cut open
Face structural schematic diagram.As shown in Figure 4 A, the first insulating layer 270 covering organic semiconductor patterns 140 " and source drain pattern 130,
First insulating layer 270 is provided with two the first via holes 271 for exposing corresponding source drain pattern 130.280 He of gate pattern
Two bars transmission lines 281 are arranged on the first insulating layer 270, wherein gate pattern 280 and organic semiconductor patterns 140 "
Intermediate region is correspondingly arranged, and two bars transmission lines 281 pass through corresponding first via hole 271 and corresponding source/drain pole figure respectively
Case 130 contacts.
Step S209: the second insulating layer of covering gate pattern and signal transmssion line is formed, wherein second insulating layer setting
There is the second via hole for exposing a bars transmission line.
In step S209, second insulating layer includes inorganic passivation layer (PV layers) and organic planarization layer (PLN layers).It is specific next
It says, in the present embodiment, forms inorganic passivation layer using the method for vapor deposition first on gate pattern and signal transmssion line, then
It is coated with organic planarization layer on electrodeless passivation layer, is finally formed using the method for etching and runs through inorganic passivation layer and organic planarization
Layer and the second via hole for exposing a bars transmission line.
Step S210: form pixel electrode over the second dielectric, wherein pixel electrode by the second via hole with it is corresponding
Signal transmssion line contact.
In the present embodiment, after the completion of step S210, Organic Thin Film Transistors completes.
It is the structural schematic diagram of Organic Thin Film Transistors made from production method shown in Fig. 4 please also refer to Fig. 5, Fig. 5.Such as
Shown in Fig. 5, Organic Thin Film Transistors includes substrate 100, organic semiconductor patterns 140 ", the insulation of source drain pattern 130, first
Layer 270, gate pattern 280, signal transmssion line 281, second insulating layer 290 and pixel electrode 300.
Organic semiconductor patterns 140 " and source drain pattern 130 are arranged on the substrate 100, source drain pattern 130 with have
Two side contacts of machine semiconductor pattern 140 ".
Wherein, organic semiconductor patterns 140 " include the first doped region 141 contacted with source drain pattern 130 and separate
Second doped region 142 of source drain pattern 130.
First insulating layer 270 covers organic semiconductor patterns 140 " and source drain pattern 130, wherein the first insulating layer
270 are provided with two the first via holes 271 for exposing corresponding source drain pattern 130.
Gate pattern 280 and two bars transmission lines 281 are arranged on the first insulating layer 270, wherein the transmission of two bars
Line 281 is contacted by corresponding first via hole 271 with source drain pattern 130.In this embodiment, it is preferred that gate pattern
280 are correspondingly arranged with the intermediate regions of organic semiconductor patterns 140 ".
Second insulating layer 290 covers gate pattern 280 and signal transmssion line 281, wherein second insulating layer 20 is provided with cruelly
Expose the second via hole 291 of a bars transmission line 281.In the present embodiment, second insulating layer 290 includes inorganic passivation layer
(PV layers) and the organic planarization layer being arranged on inorganic passivation layer (PLN layers).
Pixel electrode 300 be arranged in second insulating layer 290, wherein pixel electrode 300 by the second via hole 291 with it is right
The signal transmssion line 281 answered contacts.
The beneficial effects of the present invention are: being in contrast to the prior art, Organic Thin Film Transistors and its system of the invention
Make method by formed on substrate organic semiconductor patterns, with the source drain patterns of two side contacts of organic semiconductor patterns,
In, organic semiconductor patterns include the first doped region contacted with source drain pattern and the second doping far from source drain pattern
Area, the first doped region and the second doped region have different conductivity.By the above-mentioned means, the present invention can greatly improve source/
The contact of drain pattern and organic semiconductor patterns, and then reduce the electrical leakage problems in Organic Thin Film Transistors.
Mode the above is only the implementation of the present invention is not intended to limit the scope of the invention, all to utilize this
Equivalent structure or equivalent flow shift made by description of the invention and accompanying drawing content, it is relevant to be applied directly or indirectly in other
Technical field is included within the scope of the present invention.
Claims (10)
1. a kind of production method of Organic Thin Film Transistors, which is characterized in that the production method includes:
One substrate is provided；
Organic semiconductor patterns, the source drain pattern with two side contacts of organic semiconductor patterns are formed on the substrate,
Wherein, the organic semiconductor patterns include the first doped region contacted with the source drain pattern and the separate source/drain
Second doped region of pattern, first doped region and second doped region have different conductivity；
The first insulating layer, grid are formed on the substrate for being formed with the organic semiconductor patterns and the source-drain electrode pattern
Pattern, signal transmssion line, second insulating layer and pixel electrode；
Wherein, the conductivity of first doped region is greater than the conductivity of second doped region.
2. manufacturing method according to claim 1, which is characterized in that on the substrate formed organic semiconductor patterns,
Include: with the step of source drain patterns of two side contacts of organic semiconductor patterns
Organic semiconductor layer, the source drain pattern with two side contacts of organic semiconductor layer are formed on the substrate；
Form the electrolyte thin film layer of the covering organic semiconductor layer and the source drain pattern；
Form auxiliary electrode in the electrolyte thin film layer, wherein auxiliary electrode setting in the source drain pattern and
The face position in the region that the organic semiconductor layer is in contact；
Apply bias voltage between the auxiliary electrode and the source drain pattern so that leading in the electrolyte thin film layer
Electron ion flows into the organic semiconductor layer, includes the described organic of first doped region and second doped region to be formed
Semiconductor pattern；
Remove the auxiliary electrode and the electrolyte thin film layer.
3. production method according to claim 2, which is characterized in that the material of the electrolyte thin film layer is poly- for gel-type
In polymer electrolyte, full solid state polymer electrolyte, porous type polymer dielectric and compound polymer electrolyte at least
It is a kind of.
4. production method according to any one of claims 1 to 3, which is characterized in that described to be formed with described organic half
The first insulating layer, gate pattern, signal transmssion line, second are formed on conductive pattern and the substrate of the source drain pattern
The step of insulating layer and pixel electrode includes:
Form the first insulating layer of the covering organic semiconductor patterns and the source drain pattern, wherein first insulation
Layer is provided with the first via hole for exposing a source drain pattern；
The gate pattern and the signal transmssion line are formed on the first insulating layer, wherein the signal transmssion line is logical
First via hole is crossed to contact with the corresponding source drain pattern；
Form the second insulating layer for covering the gate pattern and the signal transmssion line, wherein the second insulating layer setting
There is the second via hole for exposing another source drain pattern；
Form the pixel electrode on the second insulating layer, wherein the pixel electrode by second via hole with it is right
The source drain pattern contact answered.
5. production method according to any one of claims 1 to 3, which is characterized in that described to be formed with described organic half
The first insulating layer, gate pattern, signal transmssion line, second are formed on conductive pattern and the substrate of the source drain pattern
The step of insulating layer and pixel electrode includes:
Form the first insulating layer of the covering organic semiconductor patterns and the source drain pattern, wherein first insulation
Layer is provided with two the first via holes for exposing the corresponding source drain pattern respectively；
The gate pattern and two signal transmssion lines are formed on the first insulating layer, wherein two signals
Transmission line is contacted by corresponding first via hole with the source drain pattern；
Form the second insulating layer for covering the gate pattern and the signal transmssion line, wherein the second insulating layer setting
There is the second via hole for exposing the signal transmssion line；
Form the pixel electrode on the second insulating layer, wherein the pixel electrode by second via hole with it is right
The signal transmssion line contact answered；
Wherein, the conductivity of first doped region is greater than the conductivity of second doped region.
6. a kind of Organic Thin Film Transistors, which is characterized in that the Organic Thin Film Transistors includes substrate, organic semiconductor patterns
And source drain pattern；
Wherein, the organic semiconductor patterns and the source drain pattern are arranged on the substrate, the source drain pattern
With two side contacts of the organic semiconductor patterns；
Wherein, the organic semiconductor patterns include the first doped region contacted with the source drain pattern and far from the source/
The second doped region of pattern is leaked, first doped region and second doped region have different conductivity.
7. thin film transistor (TFT) according to claim 6, which is characterized in that the organic semiconductor patterns pass through in the base
Organic semiconductor layer is formed on plate, electrolyte thin film layer is coated on the organic semiconductor layer, in the electrolyte thin film layer
On prepare auxiliary electrode, between the auxiliary electrode and the source drain pattern apply bias voltage formed.
8. thin film transistor (TFT) according to claim 7, which is characterized in that the material of the electrolyte thin film layer is gel-type
In polymer dielectric, full solid state polymer electrolyte, porous type polymer dielectric and compound polymer electrolyte extremely
Few one kind.
9. according to the described in any item thin film transistor (TFT)s of claim 6 to 8, which is characterized in that the thin film transistor (TFT) is further
Including the first insulating layer, gate pattern, signal transmssion line, second insulating layer and pixel electrode；
First insulating layer covers the organic semiconductor patterns and the source drain pattern, wherein first insulating layer
It is provided with the first via hole for exposing a source drain pattern；
The gate pattern and signal transmssion line setting are on the first insulating layer, wherein the signal transmssion line is logical
First via hole is crossed to contact with the corresponding source drain pattern；
The second insulating layer covers the gate pattern and the signal transmssion line, wherein the second insulating layer is provided with
Expose the second via hole of another source drain pattern；
Pixel electrode setting is on the second insulating layer, wherein the pixel electrode by second via hole with it is right
The source drain pattern contact answered.
10. according to the described in any item thin film transistor (TFT)s of claim 6 to 8, which is characterized in that the thin film transistor (TFT) is further
Including the first insulating layer, gate pattern, signal transmssion line, second insulating layer and pixel electrode；
First insulating layer covers the organic semiconductor patterns and the source drain pattern, wherein first insulating layer
It is provided with two the first via holes for exposing the corresponding source drain pattern；
The gate pattern and two signal transmssion line settings are on the first insulating layer, wherein two signals
Transmission line is contacted by first via hole with the corresponding source drain pattern；
The second insulating layer covers the gate pattern and the signal transmssion line, wherein the second insulating layer is provided with
Expose second via hole of the signal transmssion line；
Pixel electrode setting is on the second insulating layer, wherein the pixel electrode by second via hole with it is right
The signal transmssion line contact answered.
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