CN106298810A - 阵列基板制造方法、阵列基板、显示面板及显示装置 - Google Patents

阵列基板制造方法、阵列基板、显示面板及显示装置 Download PDF

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CN106298810A
CN106298810A CN201610848316.5A CN201610848316A CN106298810A CN 106298810 A CN106298810 A CN 106298810A CN 201610848316 A CN201610848316 A CN 201610848316A CN 106298810 A CN106298810 A CN 106298810A
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layer
hole
grid
underlay substrate
gate insulator
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CN106298810B (zh
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许传志
谢正芳
李雄平
童晓阳
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Tianma Microelectronics Co Ltd
Shanghai Tianma Microelectronics Co Ltd
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Tianma Microelectronics Co Ltd
Shanghai Tianma Microelectronics Co Ltd
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Abstract

本发明实施例公开了一种阵列基板制造方法、阵列基板、显示面板及显示装置。所述方法包括：在衬底基板一侧形成栅极层、位于栅极层上的栅极绝缘层以及位于栅极绝缘层上的半导体层，栅极层和半导体层的图形形状相同；在半导体层上形成刻蚀阻挡层；图案化刻蚀阻挡层形成第一通孔、第二通孔和第三通孔；在刻蚀阻挡层上形成源极层和漏极层，源极层通过第一通孔与半导体层电连接，漏极层通过第二通孔与半导体层电连接；刻蚀第三通孔对应位置处的半导体层，形成有源层，栅极层包括第三通孔对应位置处的第一部分和除第一部分之外的第二部分，栅极层的第二部分和有源层的图形形状相同。本发明实施例降低了阵列基板制作的工艺成本和工艺复杂度。

Description

阵列基板制造方法、阵列基板、显示面板及显示装置
技术领域
本发明实施例涉及液晶显示技术，尤其涉及一种阵列基板制造方法、阵列基板、显示面板及显示装置。
背景技术
随着显示技术的发展，液晶显示产品的显示效果不断地得到改善，从而使液晶显示产品的应用越来越广泛。
现有的液晶显示产品的阵列基板在制作的过程中需要多道工序，各膜层在制作时，需要分别制作掩膜版，并分别进行成膜、曝光和刻蚀，工艺复杂并且成本高。
发明内容
本发明提供了一种阵列基板制造方法、阵列基板、显示面板及显示装置，以降低阵列基板制作的工艺成本和工艺复杂度。
第一方面，本发明实施例提供了一种阵列基板制造方法，所述方法包括：
在衬底基板一侧形成栅极层、位于所述栅极层上的栅极绝缘层以及位于所述栅极绝缘层上的半导体层，其中，所述栅极层和所述半导体层的图形形状相同；
在所述半导体层上形成刻蚀阻挡层；
图案化所述刻蚀阻挡层形成有第一通孔、第二通孔和第三通孔；
在所述刻蚀阻挡层上形成源极层和漏极层，其中，所述源极层通过所述第一通孔与所述半导体层电连接，所述漏极层通过所述第二通孔与所述半导体层电连接；
刻蚀所述第三通孔对应位置处的所述半导体层，形成有源层，其中，所述栅极层包括所述第三通孔对应位置处的第一部分和除所述第一部分之外的第二部分，所述栅极层的第二部分和所述有源层的图形形状相同。
第二方面，本发明实施例还提供了一种阵列基板，所述阵列基板包括：
衬底基板；
位于所述衬底基板上的栅极层；
位于所述栅极层上的栅极绝缘层；
位于所述栅极绝缘层上的有源层；
位于所述有源层上的刻蚀阻挡层；
位于所述刻蚀阻挡层上的源极层和漏极层；
其中，所述刻蚀阻挡层设置有第一通孔、第二通孔和第三通孔；所述源极层通过所述第一通孔与所述有源层连接，所述漏极层通过所述第二通孔与所述有源层连接；所述有源层在所述第三通孔对应位置处断开，所述栅极层包括所述第三通孔对应位置处的第一部分和除所述第一部分之外的第二部分，所述栅极层的第二部分和所述有源层的图形形状相同。
第三方面，本发明实施例还提供了一种显示面板，所述显示面板包括本发明任意实施例所述的阵列基板。
第四方面，本发明实施例还提供了一种显示装置，所述显示装置包括本发明任意实施例所述的显示面板。
本发明实施例的方案通过设置栅极层和半导体层的形状相同，在刻蚀阻挡层上设置第一通孔、第二通孔和第三通孔，源极层通过所述第一通孔与所述半导体层电连接，漏极层通过所述第二通孔与所述半导体层电连接，并通过刻蚀所述第三通孔对应位置处的所述半导体层来形成有源层，简化了有源层的制作工艺，无需另外配置有源层掩膜版，节省了工艺成本，并且有源层和栅极层可以自动对位，降低工艺难度。
附图说明
图1是本发明实施例提供的一种阵列基板制造方法的流程图；
图2a是本发明实施例提供的栅极层、栅极绝缘层以及半导体层的平面图；
图2b是图2a沿剖面线A-A的一种剖面图；
图2c是本发明实施例提供的一种栅极绝缘层的示意图；
图2d是本发明实施例提供的栅极层、栅极绝缘层和半导体层形成工艺图；
图2e是本发明实施例提供的又一种栅极层、栅极绝缘层和半导体层形成工艺图；
图2f是本发明实施例提供的又一种栅极层、栅极绝缘层和半导体层形成工艺图；
图2g是图2a沿剖面线A-A的又一种剖面图；
图3a是本发明实施例提供的形成刻蚀阻挡层的平面图；
图3b是图3a沿剖面线B-B的剖面图；
图4a是本发明实施例提供的形成源漏极层的平面图；
图4b是图4a沿剖面线C-C的剖面图；
图5a是本发明实施例提供的形成有源层的平面图；
图5b是图5a沿剖面线D-D的剖面图；
图6是本发明实施例提供的形成像素电极的平面图；
图7是本发明实施例提供的形成公共电极的平面图；
图8是本发明实施例提供的一种显示面板的结构示意图；
图9是本发明实施例提供的一种显示面板的结构示意图。
具体实施方式
下面结合附图和实施例对本发明作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本发明，而非对本发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本发明相关的部分而非全部结构。
现有技术的阵列基板在制作过程中需要多道工序，例如，栅极层和有源层需要分别制作掩膜版，并分别进行成膜、曝光和刻蚀等，工艺成本高，且工序较多；并且在制作过程中栅极层和有源层需要进行对位，对工艺要求较高。为解决上述问题，本实施例提供了一种阵列基板制作方法。
图1是本发明实施例提供的一种阵列基板制造方法的流程图，参考图1，所述方法包括：
步骤110、在衬底基板一侧形成栅极层、位于所述栅极层上的栅极绝缘层以及位于所述栅极绝缘层上的半导体层，其中，所述栅极层和所述半导体层的图形形状相同。
具体的，图2a是本发明实施例提供的栅极层、栅极绝缘层以及半导体层的平面图，图2b是图2a沿剖面线A-A的一种剖面图。参考图2a和图2b，栅极层210和半导体层230的图形形状相同，使得在形成半导体层230时可以采用栅极层掩膜版或以栅极层210作掩膜的形式形成。需要说明的是，图2a中并未示出栅极绝缘层220。
具体的，参考图2b，栅极绝缘层220覆盖栅极层210，栅极绝缘层220可以为硅氧化物。图2c是本发明实施例提供的一种栅极绝缘层的示意图，参考图2c，栅极绝缘层220还可以为包括第一绝缘层221和第二绝缘层222的多层结构。第一绝缘层221设置于第二绝缘层222临近栅极层210的一侧，第一绝缘层221可以为硅氮化物，如二氧化硅；第二绝缘层222可以为硅氧化物，如氮化硅。
图2d是本发明实施例提供的栅极层、栅极绝缘层和半导体层形成工艺图，参考图2b和图2d，可以采用如下工艺过程形成栅极层210、栅极绝缘层220和半导体层230：在衬底基板200上形成第一金属层，图案化所述第一金属层形成栅极层210；在栅极层210上形成栅极绝缘层220；在栅极绝缘层220上形成半导体材料层231，以栅极层210为掩膜版，图案化半导体材料层231形成半导体层230。通过采用栅极层210作为掩膜版，以背部曝光(即光源设置衬底基板200远离栅极层210的一侧)的形式图案化半导体材料层231，形成半导体层230，无需另外设置掩膜版，节省了工艺成本，另外采用栅极层210作为掩膜版，使形成的半导体层230与栅极层210可以自动对位，降低了工艺难度，减少了工艺步骤。
图2e是本发明实施例提供的又一种栅极层、栅极绝缘层和半导体层形成工艺图，参考图2b和图2e，还可以采用如下工艺过程形成栅极层210、栅极绝缘层220和半导体层230：在衬底基板200上形成第一金属层，图案化所述第一金属层形成栅极层210；在栅极层210上形成栅极绝缘层220；在栅极绝缘层220上形成半导体材料层231；采用形成栅极层210的栅极层掩膜版100，图案化半导体材料层231形成半导体层230。
具体的，采用栅极层掩膜版100形成半导体层230，无需另外设置掩膜版，节省了工艺成本，以栅极层掩膜版100形成的半导体层230与栅极层210可以自动对位，降低了工艺难度，减少了工艺步骤。
可以理解的是，采用图2d或图2e提供的栅极层、栅极绝缘层和半导体层形成工艺图形成的栅极层、栅极绝缘层以及半导体层的剖面图可以如图2b或图2c所示。
图2f是本发明实施例提供的又一种栅极层、栅极绝缘层和半导体层形成工艺图，参考图2b和图2f，还可以采用如下工艺过程形成栅极层210、栅极绝缘层220和半导体层230：在衬底基板200上形成第一金属层211、第一绝缘层223以及半导体材料层231；使用栅极层掩膜版100通过一次构图工艺图案化第一金属层211、第一绝缘层223以及半导体材料层231形成半导体层230、栅极绝缘层220以及栅极层210。
具体的，使用栅极层掩膜版100，通过一次构图工艺形成半导体层230、栅极绝缘层220以及栅极层210，半导体层230和栅极层210采用同一掩膜版，无需分别设置掩膜版，节省了工艺成本，并且半导体层230与栅极层210可以自动对位，降低了工艺难度，减少了工艺步骤。另外，采用图2f所示工艺形成的栅极绝缘层220与栅极层210和半导体层230具有相同的形状，如图2g所示，图2g是图2a沿剖面线A-A的又一种剖面图。
步骤120、在半导体层230上形成刻蚀阻挡层。
图3a是本发明实施例提供的形成刻蚀阻挡层的平面图，图3b是图3a沿剖面线B-B的剖面图。参考图3a和图3b，刻蚀阻挡层240覆盖半导体层230。在薄膜晶体管的制作过程中，由于半导体层230容易受损伤，在半导体层上方制作一层刻蚀阻挡层240，可以起到保护半导体层的作用。
步骤130、图案化刻蚀阻挡层240形成第一通孔241、第二通孔242和第三通孔243。
具体的，刻蚀阻挡层240为面状，只需进行一次刻蚀即可形成，相对于岛状刻蚀阻挡层，无需通过多次刻蚀或灰化，节省了工序，降低了制作工艺的难度。
步骤140、在刻蚀阻挡层240上形成源极层和漏极层。
图4a是本发明实施例提供的形成源漏极层的平面图，图4b是图4a沿剖面线C-C的剖面图。参考图4a和图4b，源极层251通过第一通孔241与半导体层230电连接，漏极层252通过第二通孔242与半导体层230电连接。具体的，源极层251和漏极层252分别通过相应的通孔与半导体层230电连接，通过调整第一通孔241和第二通孔242之间的距离可以方便的调整薄膜晶体管沟道区的长度。另外，由于通孔在形成时，尺寸的控制精度较高，可以精确的调整通孔的大小，从而可以精确的调整源极层251和漏极层252与半导体层230的接触电阻，提高薄膜晶体管和阵列基板的制作精度。另外，由于源极层251和漏极层252在面状刻蚀阻挡层240上形成，在成膜后只需采用普通的掩膜版进行曝光和刻蚀即可，无需采用昂贵的半色调掩膜版，降低了工艺成本和工艺难度。
步骤150、刻蚀第三通孔243对应位置处的半导体层230，形成有源层。
图5a是本发明实施例提供的形成有源层的平面图，图5b是图5a沿剖面线D-D的剖面图。参考图5a和图5b，栅极层210包括第三通孔243对应位置处的第一部分212和除第一部分212之外的第二部分213，栅极层210的第二部分213和有源层230a的图形形状相同。具体的，由于半导体层230与栅极层210的形状相同且自动对位，在刻蚀第三通孔243对应位置处的半导体层230之后形成的有源层230a与栅极层210的第二部分213形状相同，且栅极层210和有源层230a自动对位，减小了工序并降低了工艺复杂度。
本实施例的方案通过设置栅极层和半导体层的形状相同，在刻蚀阻挡层上设置第一通孔、第二通孔和第三通孔，源极层通过所述第一通孔与所述半导体层电连接，漏极层通过所述第二通孔与所述半导体层电连接，并通过刻蚀所述第三通孔对应位置处的所述半导体层来形成有源层，简化了有源层的制作工艺，无需另外配置有源层掩膜版，节省了工艺成本，并且有源层和栅极层可以自动对位，降低工艺难度。
可选的，有源层230a的材料为金属氧化物半导体。可以采用形成源极层251和漏极层252的第一刻蚀液或者采用金属氧化物半导体刻蚀液去除第三通孔243对应位置处露出的半导体层230，在半导体层230中形成断口结构，形成有源层230a。
具体的，在形成源极层251和漏极层252后，可以采用形成源极层251和漏极层252的第一刻蚀液继续刻蚀，将半导体层230与第三通孔243对应位置刻断。若所述第一刻蚀液不能将半导体层230刻断或者形成源极层251和漏极层252时采用的为干刻等，则可以采用金属氧化物半导体刻蚀液去除第三通孔243对应位置处露出的半导体层230。
可选的，有源层230a的材料为铟镓锌氧化物(indium gallium zinc oxide，IGZO)。IGZO是一种含有铟、镓和锌的非晶氧化物，载流子迁移率是非晶硅的20～30倍，可以大大提高薄膜晶体管对像素电极的充放电速率，提高像素的响应速度，实现更快的刷新率，同时更快的响应也大大提高了像素的行扫描速率。
可选的，参考图4a，沿与栅极层210延伸方向垂直的方向，第三通孔243的长度a大于第三通孔243对应位置露出的半导体层230的长度b。参考图5a，通过设置第三通孔243的长度a大于半导体层230的长度b，使得第三通孔243对应位置处的半导体层230能够完全裸露出来，保证了在刻蚀半导体层230时能够完全刻断，以形成多个薄膜晶体管。
可选的，参考图4a，沿与栅极层210延伸方向垂直的方向，第三通孔243的边界在衬底基板200上的垂直投影与第三通孔243对应位置露出的半导体层230的边界在衬底基板200上的垂直投影之间的距离差d大于或等于1.5μm。这样设置，使得第三通孔243对应位置处的半导体层230的两边界均能裸露出来，进一步保证了在刻蚀半导体层230时能够完全刻断，并且设置d大于或等于1.5μm，在工艺上较易实现，降低了工艺难度。
可选的，参考图5a，有源层230a在衬底基板200上的垂直投影位于栅极层210在衬底基板200上的垂直投影内。这样设置，使得栅极层210能够完全遮挡有源层230a，避免了显示面板的光源照射有源层而产生光电流，从而减小了薄膜晶体管的漏电流。具体的，在形成半导体层230时，可以通过调整曝光强度、曝光时间、刻蚀液浓度或刻蚀时间等来调整半导体层230的尺寸，从调整有源层230a的尺寸，以保证有源层230a在衬底基板200上的垂直投影位于栅极层210在衬底基板200上的垂直投影内。
可选的，参考图5a，栅极层210的边界在衬底基板200上的垂直投影与有源层230a的边界在衬底基板200上的垂直投影之间的距离差s大于或等于1μm。这样设置，保证了有源层230a在衬底基板200上的垂直投影位于栅极层210在衬底基板200上的垂直投影内，进而保证了栅极层210能够完全遮挡有源层230a，避免了显示面板的光源照射有源层而产生光电流，从而减小了薄膜晶体管的漏电流。
图6是本发明实施例提供的形成像素电极的平面图，参考图6，在形成有源层230a后，在漏极层252上方形成像素电极260，像素电极260与漏极层252电连接，像素电极260可以为面状。
图7是本发明实施例提供的形成公共电极的平面图，参考图7，在形成像素电极260之后，在像素电极260上方形成公共电极270，公共电极270具有条形狭缝，以与像素电极260形成电场驱动液晶。
需要说明的是，图7中仅示例性的示出了公共电极270的轮廓，并非对本发明的限定。另外，本实施例仅示例性的示出了公共电极270位于像素电极260远离衬底基板200一侧的情况，并非对本发明的限定，在其他实施方式中，像素电极260还可以位于公共电极270远离衬底基板200的一侧，像素电极260也可以和公共电极270同层设置。
本实施例还提供了一种阵列基板，参考图5a和图5b，所述阵列基板包括:衬底基板200，位于衬底基板200上的栅极层210，位于栅极层210上的栅极绝缘层220，位于栅极绝缘层220上的有源层230a，位于有源层230a上的刻蚀阻挡层240，位于刻蚀阻挡层240上的源极层251和漏极层252。
其中，刻蚀阻挡层240设置有第一通孔241、第二通孔242和第三通孔243。源极层251通过第一通孔241与有源层230a连接，漏极层252通过第二通孔242与有源层230a连接。有源层230a在第三通孔243对应位置处断开，栅极层210包括第三通孔243对应位置处的第一部分212和除第一部分212之外的第二部分213，栅极层210的第二部分213和有源层230a的图形形状相同。
进一步的，有源层230a在所衬底基板200上的垂直投影可以位于栅极层210在衬底基板200上的垂直投影内。
进一步的，栅极层210的边界在衬底基板200上的垂直投影与有源层230a的边界在衬底基板200上的垂直投影之间的距离差s可以大于或等于1μm。
进一步的，有源层230a的材料可选为金属氧化物半导体。
进一步的，有源层230a的材料可选为铟镓锌氧化物。
本发明实施例还提供了一种显示面板，图8是本发明实施例提供的一种显示面板的结构示意图，参考图8，所述显示面板包括本发明任意实施例所述的阵列基板300。所述显示面板还包括与阵列基板300相对设置的彩膜基板400，以及位于阵列基板300和彩膜基板400之间的液晶层500。
本发明实施例还提供了一种显示装置，图9是本发明实施例提供的一种显示面板的结构示意图，参考图9，所述显示装置包括本发明任意实施例所述的显示面板600。
本实施例提供的阵列基板与本发明任意实施例提供的阵列基板制造方法属于同一发明构思，具有相应的有益效果，未在本实施例中详述的技术细节可以参见本发明任意实施例提供的阵列基板制造方法。
注意，上述仅为本发明的较佳实施例及所运用技术原理。本领域技术人员会理解，本发明不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本发明的保护范围。因此，虽然通过以上实施例对本发明进行了较为详细的说明，但是本发明不仅仅限于以上实施例，在不脱离本发明构思的情况下，还可以包括更多其他等效实施例，而本发明的范围由所附的权利要求范围决定。

Claims (18)

1.一种阵列基板制造方法，其特征在于，包括：
在衬底基板一侧形成栅极层、位于所述栅极层上的栅极绝缘层以及位于所述栅极绝缘层上的半导体层，其中，所述栅极层和所述半导体层的图形形状相同；
在所述半导体层上形成刻蚀阻挡层；
图案化所述刻蚀阻挡层形成第一通孔、第二通孔和第三通孔；
在所述刻蚀阻挡层上形成源极层和漏极层，其中，所述源极层通过所述第一通孔与所述半导体层电连接，所述漏极层通过所述第二通孔与所述半导体层电连接；
刻蚀所述第三通孔对应位置处的所述半导体层，形成有源层，其中，所述栅极层包括所述第三通孔对应位置处的第一部分和除所述第一部分之外的第二部分，所述栅极层的第二部分和所述有源层的图形形状相同。
2.根据权利要求1所述的方法，其特征在于，所述在衬底基板一侧形成栅极层、位于所述栅极层上的栅极绝缘层以及位于所述栅极绝缘层上的半导体层，包括：
在所述衬底基板上形成第一金属层，图案化所述第一金属层形成所述栅极层；
在所述栅极层上形成所述栅极绝缘层；
在所述栅极绝缘层上形成半导体材料层；
以所述栅极层为掩膜版，图案化所述半导体材料层形成所述半导体层。
3.根据权利要求1所述的方法，其特征在于，所述在衬底基板一侧形成栅极层、位于所述栅极层上的栅极绝缘层以及位于所述栅极绝缘层上的半导体层，包括：
在所述衬底基板上形成第一金属层，图案化所述第一金属层形成所述栅极层；
在所述栅极层上形成所述栅极绝缘层；
在所述栅极绝缘层上形成半导体材料层；
采用形成所述栅极层的栅极层掩膜版，图案化所述半导体材料层形成所述半导体层。
4.根据权利要求1所述的方法，其特征在于，所述在衬底基板一侧形成栅极层、位于所述栅极层上的栅极绝缘层以及位于所述栅极绝缘层上的半导体层，包括：
在所述衬底基板上形成第一金属层、第一绝缘层以及半导体材料层；
使用栅极层掩膜版通过一次构图工艺图案化所述第一金属层、所述第一绝缘层以及所述半导体材料层形成所述半导体层、所述栅极绝缘层以及所述栅极层。
5.根据权利要求1所述的方法，其特征在于，沿与所述栅极层延伸方向垂直的方向，所述第三通孔的长度大于所述第三通孔对应位置露出的所述半导体层的长度。
6.根据权利要求5所述的方法，其特征在于，沿与所述栅极层延伸方向垂直的方向，所述第三通孔的边界在所述衬底基板上的垂直投影与所述第三通孔对应位置露出的所述半导体层的边界在所述衬底基板上的垂直投影之间的距离差大于或等于1.5μm。
7.根据权利要求1所述的方法，其特征在于，所述有源层在所述衬底基板上的垂直投影位于所述栅极层在所述衬底基板上的垂直投影内。
8.根据权利要求7所述的方法，其特征在于，所述栅极层的边界在所述衬底基板上的垂直投影与所述有源层的边界在所述衬底基板上的垂直投影之间的距离差大于或等于1μm。
9.根据权利要求1-8任一项所述的方法，其特征在于，所述有源层的材料为金属氧化物半导体。
10.根据权利要求9所述的方法，其特征在于，所述有源层的材料为铟镓锌氧化物。
11.根据权利要求9所述的方法，其特征在于，所述刻蚀所述第三通孔对应位置处的所述半导体层，形成有源层，包括：
采用形成所述源极层和所述漏极层的第一刻蚀液或者采用金属氧化物半导体刻蚀液去除所述第三通孔对应位置处露出的所述半导体层，在所述半导体层中形成断口结构，形成所述有源层。
12.一种阵列基板，其特征在于，包括:
衬底基板；
位于所述衬底基板上的栅极层；
位于所述栅极层上的栅极绝缘层；
位于所述栅极绝缘层上的有源层；
位于所述有源层上的刻蚀阻挡层；
位于所述刻蚀阻挡层上的源极层和漏极层；
其中，所述刻蚀阻挡层设置有第一通孔、第二通孔和第三通孔；所述源极层通过所述第一通孔与所述有源层连接，所述漏极层通过所述第二通孔与所述有源层连接；所述有源层在所述第三通孔对应位置处断开，所述栅极层包括所述第三通孔对应位置处的第一部分和除所述第一部分之外的第二部分，所述栅极层的第二部分和所述有源层的图形形状相同。
13.根据权利要求12所述的阵列基板，其特征在于，所述有源层在所述衬底基板上的垂直投影位于所述栅极层在所述衬底基板上的垂直投影内。
14.根据权利要求13所述的阵列基板，其特征在于，所述栅极层的边界在所述衬底基板上的垂直投影与所述有源层的边界在所述衬底基板上的垂直投影之间的距离差大于或等于1μm。
15.根据权利要求12-14任一项所述的阵列基板，其特征在于，所述有源层的材料为金属氧化物半导体。
16.根据权利要求15所述的阵列基板，其特征在于，所述有源层的材料为铟镓锌氧化物。
17.一种显示面板，其特征在于，包括权利要求12-16任一项所述的阵列基板。
18.一种显示装置，其特征在于，包括权利要求17所述的显示面板。
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