CN106298667B - The forming method of semiconductor structure - Google Patents

The forming method of semiconductor structure Download PDF

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Publication number
CN106298667B
CN106298667B CN201510271980.3A CN201510271980A CN106298667B CN 106298667 B CN106298667 B CN 106298667B CN 201510271980 A CN201510271980 A CN 201510271980A CN 106298667 B CN106298667 B CN 106298667B
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area
layer
grid
pseudo
groove
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CN106298667A (en
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胡华勇
林益世
宋伟基
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A kind of forming method of semiconductor structure, comprising: form the first metal layer in high-K dielectric layer and the sidewall surfaces of the first groove, the second groove and third groove；Second metal layer is formed on the first metal layer；Inorganic fill layer is formed in second metal layer, inorganic fill layer fills full first groove, the second groove and third groove, and the thickness of the inorganic fill layer of second area is greater than the thickness of the inorganic fill layer of first area；Reflowable organic coating is formed on the inorganic fill layer, the thickness of the reflowable organic coating of second area is less than the thickness of the reflowable organic coating of first area；Reflowable organic coating, inorganic fill layer and the second metal layer on NMOS area in etching removal second area and first area, exposes the surface of the first metal layer.Method of the invention prevents the etching injury of the metal layer using single inorganic fill layer bring difference in thickness and caused different zones.

Description

The forming method of semiconductor structure
Technical field
The present invention relates to field of semiconductor fabrication, in particular to a kind of forming method of semiconductor structure.
Background technique
With the rapid development of integrated circuit (abbreviation IC) manufacturing technology, behind sub-micron features size field, Traditional integrated circuit size constantly reduces, and such as channel length and gate oxide (generally SiO in MOS transistor2) thickness presses After scale smaller, loss, high gate resistance and the dopant (such as boron) for exacerbating polysilicon penetrate into the channel region of device Domain and the defects of cause grid leakage current to increase.For this purpose, the gate stack structure of high K gate dielectric layer and metal gate electrode is introduced into Into MOS transistor.
In order to improve the performance of transistor, NMOS and PMOS generally adjust material using different work functions, existing to have The NMOS of different work function regulating courses and the integration making technology of PMOS transistor are as follows: semiconductor substrate is provided, it is described partly to lead Body substrate includes first area and second area, and it is pseudo- that several first are formed in the semiconductor substrate of first area and second area Grid and the second pseudo- grid；Form the dielectric layer for covering the semiconductor substrate, the first pseudo- grid and the second pseudo- grid surface, the dielectric layer Surface flushed with the top surface of the first pseudo- grid and the second pseudo- grid；It removes the described first pseudo- grid and forms the first groove, remove institute It states the second pseudo- grid and forms the second groove；The first metal layer, institute are formed on the surface of first groove, the second groove and dielectric layer The first metal layer is stated as work function regulating course, in the second metal layer that the surface of the first metal layer is formed, described second Metal layer is as work function regulating course；Form the mask layer for covering the second metal layer surface of the second area；It is covered with described Film layer is exposure mask, and the second metal layer of etching removal first area exposes the surface of the first metal layer；Remove the exposure mask Layer forms the first metal gate electrode of NMOS transistor, the filling of the first metal gate electrode on the first metal layer of first area First groove forms the second metal gate electrode of PMOS transistor, the second metal gate electricity in the second metal layer of second area Fill the second groove in pole.
But the performance of NMOS transistor that is formed of existing NMOS and PMOS integrated technique still have it is to be hoisted.
Summary of the invention
Problems solved by the invention is how to prevent NMOS and PMOS integrated technique to the etching injury of metal layer.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, comprising:
Semiconductor substrate is provided, the semiconductor substrate includes first area and second area, and the first area includes NMOS area and the area PMOS have the several first pseudo- grid in the semiconductor substrate in the area PMOS, have in the semiconductor substrate of NMOS area Several second pseudo- grid, have several third puppet grid in the semiconductor substrate of second area, the described first pseudo- grid and the second pseudo- grid Density is greater than the density of third puppet grid, has between the described first pseudo- grid, the second pseudo- grid and third puppet grid and semiconductor substrate High-K dielectric layer；Formed cover the semiconductor substrate, the first pseudo- grid, the second pseudo- grid and third puppet grid dielectric layer, the medium The surface of layer is flushed with the top surface of the first pseudo- grid, the second pseudo- grid and third puppet grid；Remove the described first pseudo- grid, the second pseudo- grid With third puppet grid, the first groove, the second groove and third groove are formed；In the high-K dielectric layer and the first groove, second The first metal layer is formed in the sidewall surfaces of groove and third groove；Second metal layer is formed on the first metal layer；? Inorganic fill layer is formed in second metal layer, inorganic fill layer fills full first groove, the second groove and third groove, and second The thickness of the inorganic fill layer in region is greater than the thickness of the inorganic fill layer of first area；Being formed on the inorganic fill layer can The organic coating of reflux, the thickness of the reflowable organic coating of second area are less than the reflowable organic coating of first area Thickness；Patterned photoresist layer, the patterned photoresist layer exposure are formed on the reflowable organic coating Out in second area and first area NMOS area reflowable organic coating layer surface；Etching removal second area and first area Reflowable organic coating, inorganic fill layer and second metal layer on interior NMOS area, expose the surface of the first metal layer.
It optionally, include element silicon in the inorganic fill layer.
Optionally, the formation process of the inorganic fill layer is spin coating.
Optionally, the difference in thickness of the first area and second area inorganic fill layer is 400~600 angstroms.
Optionally, the forming process of the reflowable organic coating are as follows: use spin coating proceeding shape on inorganic fill layer At reflowable antireflection material layer；The first heat treatment is carried out to the reflowable antireflection material layer at the first temperature； After first heat treatment, the second heat treatment is carried out to the reflowable antireflection material layer at the second temperature, is formed reflowable Organic coating, second temperature be greater than the first temperature.
Optionally, first temperature is higher than the glass transition temperature of organic-containing materials and is lower than Cross-linked temperature, described Second temperature is higher than the crosslinking temperature of reflowable organic-containing materials.
Optionally, first temperature is 50~160 degrees Celsius, and the time of the first heat treatment is 1min-30min.
Optionally, the second temperature is 180~350 degrees Celsius, and the time of the second heat treatment is 1min-30min.
Optionally, the overall thickness of the inorganic fill layer and reflowable organic coating is 500~3000 angstroms.
Optionally, the overall thickness of the inorganic fill layer and reflowable organic coating of the first area and second area is poor Different value is less than 100 angstroms.
Optionally, the first metal layer and the material of second metal layer be not identical.
Optionally, the material of the first metal layer is one in Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN, TiAlN Kind is several.
Optionally, the material of the second metal layer is one in Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN, TiAlN Kind is several.
Optionally, the remaining reflowable organic coating of removal, inorganic fill layer are further comprised the steps of:, the area PMOS is exposed On second metal layer surface；The first metal gate electrode, the first metal gate electrode are formed in the second metal layer in the area PMOS The first groove is filled, forms the second metal gate electrode on the first metal layer on NMOS area, the second metal gate electrode filling the Two grooves, form third metal gate electrode on the first metal layer on the second region, and third metal gate electrode fills full third Groove.
Optionally, etching removal second area and reflowable organic coating, inorganic fill layer and second on NMOS area The step of metal layer includes the first etch step, the second etch step and third etch step, carries out the first etch step, etching Remove second area and reflowable organic coating and part inorganic fill layer on NMOS area；The second etch step is carried out, is gone Except inorganic fill layer remaining on second area and NMOS area, the second metal layer table on second area and NMOS area is exposed Face；Carry out third etch step, etching removal second area and NMOS area on second metal layer, expose second area and The first metal layer surface on NMOS area.
Optionally, after carrying out the first etch step, the thickness of remaining inorganic fill layer on second area and NMOS area≤ 50 angstroms.
Optionally, the first etch step is plasma etching industrial, and the gas that the plasma etching industrial uses is carbon Fluorine compound gas and oxygen.
Optionally, the second etch step is plasma etching industrial, and the gas that the plasma etching industrial uses is carbon Fluorine compound gas and oxygen.
Optionally, the third etch step is wet etching.
Optionally, the etching solution that the wet etching uses is the mixed solution of hydrochloric acid, hydrogen peroxide and water.
Compared with prior art, technical solution of the present invention has the advantage that
The forming method of semiconductor structure of the invention forms inorganic fill layer, inorganic fill layer in second metal layer Full first groove, the second groove and third groove are filled, and the thickness of the inorganic fill layer of second area is greater than first area The thickness of inorganic fill layer；Reflowable organic coating is formed on the inorganic fill layer, the reflowable of second area has The thickness of organic coating is less than the thickness of the reflowable organic coating of first area；It is formed on the reflowable organic coating Patterned photoresist layer, the patterned photoresist layer expose the reflowable organic coating of second area and NMOS area Surface；Etching removal second area and reflowable organic coating, inorganic fill layer and second metal layer on NMOS area, exposure The surface of the first metal layer out.Form the reflowable organic coating on inorganic fill layer, it is on the one hand reflowable organic Coating as it is subsequent be exposed technique to photoresist layer when organic coating；On the other hand, the reflowable organic coating The difference in thickness on first area and second area for eliminating inorganic fill layer, so that inorganic fill layer and reflowable having The overall structure that organic coating is constituted has flat surface, i.e., so that second metal layer surface on first area and second area On the integrally-built thickness being made of inorganic fill layer and reflowable organic coating is equal or difference in thickness very little, carving Etching off is except reflowable organic coating, the inorganic fill layer and when second metal layer on second area and NMOS area, second area Or difference in thickness very little equal with thickness layer to be etched on NMOS area, thus etching process will not be to second area or NMOS area On the first metal layer generate etching injury so that after third etch step exposure second area or NMOS area on the first gold medal The thickness for belonging to layer is consistent.
Further, first temperature is 50~160 degrees Celsius, and the time of the first heat treatment is 1min-30min, described Second temperature is 180~350 degrees Celsius, and the time of the second heat treatment is 1min-30min, so that is formed is reflowable organic The effect that coating eliminates the difference in thickness on the first area and second area of inorganic fill layer is preferable.
Detailed description of the invention
Fig. 1~Figure 11 is the structural schematic diagram of the forming process of one embodiment of the invention semiconductor structure.
Specific embodiment
As described in the background art, the performance for the NMOS transistor that existing NMOS and PMOS integration making technology is formed still has It is to be hoisted.
The study found that in NMOS and PMOS integrated technique manufacture craft, mask layer generally uses Other substrate materials, but by The precision of photoetching process is improved in order to enable mask layer has flat surface in the presence of the first groove and the second groove, It needs before forming photoresist mask layer, forms filled layer on the semiconductor substrate, the formation process of filled layer is rotation Technique is applied, then photoresist mask layer is formed in filling layer surface, then uses the exposure development technique graphically photoresist Mask layer forms the opening for exposing the filled layer on first area in photoresist mask layer, then along opening etching filling Layer exposes the second metal layer on first area, then removes the second metal layer on first area, exposes the first metal Layer.Further study show that since the Density Distribution of several transistors in semiconductor substrate has differences, i.e., corresponding first The Density Distribution of several first grooves and the second groove has differences on region and second area, with the distribution of several first grooves For, area's (unit plane is dredged including the first groove Mi Qu (the first number of recesses in unit area is relatively more) and the first groove The first number of recesses in product is relatively fewer), when forming filled layer, the first number of recesses of the first groove Mi Qu is greater than first Groove dredges the quantity of first groove in area, and consumption of the filled layer when filling the first groove of the first groove Mi Qu is bigger, makes The thickness for obtaining the filled layer of the first groove Mi Qu can be relatively shorter than the thickness that the first groove dredges the filled layer in area, cover with photoresist When film layer etches the filled layer on first area, due to the filled layer thinner thickness in the close area of the first groove, can first it be etched Except to expose second metal layer in the first groove, and continue to etch with the filled layer dredged the first groove in area, Second metal layer in the close area of first groove can be by over etching, so that the thickness of the second metal layer in the first flute density can become It is thin, it is subsequent to dredge second metal layer in area and the close area of the first groove removing the first groove, in the corresponding close area of first groove Second metal layer can be removed first, be made, when continuing to remove the second metal layer in the thin area of the first groove, in the close area of the first groove The first metal layer can be by over etching, i.e., after removing second metal layer, the thickness of the first metal layer in the close area of the first groove The thickness that the first metal layer in area can be dredged less than the first groove, to influence the performance for the transistor being subsequently formed.
For this purpose, preventing from dredging in the forming process of transistor the present invention provides a kind of forming method of semiconductor structure The etching injury of the metal layer in the area He Mi, area.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention Specific embodiment be described in detail.When describing the embodiments of the present invention, for purposes of illustration only, schematic diagram can disobey general proportion Make partial enlargement, and the schematic diagram is example, should not limit the scope of the invention herein.In addition, in reality It should include the three-dimensional space of length, width and depth in production.
Fig. 1~Figure 11 is the structural schematic diagram of the forming process of one embodiment of the invention semiconductor structure.
With reference to Fig. 1, semiconductor substrate 200 is provided, the semiconductor substrate 200 includes first area 11 and second area 12, the first area 11 includes NMOS area 21 and the area PMOS 22, has several first in the semiconductor substrate 200 in the area PMOS 22 Pseudo- grid 203 have the several second pseudo- grid 204, the semiconductor substrate of second area 12 in the semiconductor substrate 200 of NMOS area 21 There are several third puppet grid 205, the density of the first pseudo- grid 203 and the second pseudo- grid 204 is greater than third puppet grid 205 on 200 Density.
The material of the semiconductor substrate 200 is silicon (Si), germanium (Ge) or SiGe (GeSi), silicon carbide (SiC)；It can also To be silicon-on-insulator (SOI), germanium on insulator (GOI)；It or can also be other materials, such as GaAs etc. III-V Compounds of group.The semiconductor substrate 200 can also inject certain Doped ions according to design requirement to change electrical parameter.
The semiconductor substrate 200 includes first area 11 and second area 12, and first area is that pseudo- grid density is biggish Region, second area are the pseudo- lesser region of grid density, and pseudo- grid density is the quantity of pseudo- grid in unit area, in the present embodiment, The density of first pseudo- grid and the second pseudo- grid is the quantity of the first pseudo- grid and the second pseudo- grid in unit area, and the density of third puppet grid is The quantity of third puppet grid in unit area.
The quantity of first area 11 and second area 12 can be one or more (>=2) in semiconductor substrate 200, this In embodiment, using a first area 11 and a second area 12 as example.
The second area 12 includes NMOS area 21 and the area PMOS 22, is subsequently formed NMOS transistor on NMOS area 21, PMOS transistor is subsequently formed in the area PMOS 22.The quantity in the NMOS area 21 and the area PMOS 22 can for one or more (>=2 It is a), in the present embodiment, using a NMOS area 21 and an area PMOS 22 as example.
Fleet plough groove isolation structure 201, the fleet plough groove isolation structure 201 are also formed in the semiconductor substrate 200 For adjacent active area to be isolated, prevent from being electrically connected between the transistor formed on different active areas, it is described in the present embodiment Fleet plough groove isolation structure can be formed between NMOS area 21 and the area PMOS 22, between the first area 11 and second area 12 Fleet plough groove isolation structure can be formed.
The fleet plough groove isolation structure 201 can be with single-layer or multi-layer (>=2 layers) stacked structure.In one embodiment, described When fleet plough groove isolation structure 201 is single layer structure, the material of the fleet plough groove isolation structure 201 can for silica, silicon nitride, Silicon oxynitride is one such or several.In one embodiment, the fleet plough groove isolation structure is double stacked structure, including lining Pad oxide and the filled layer in cushion oxide layer.
The first pseudo- grid 204 of pseudo- grid 203, second and third puppet grid 205 are as sacrificial when being subsequently formed metal gate electrode The material of domestic animal layer, the described first pseudo- grid 204 of pseudo- grid 203, second and third puppet grid 205 is polysilicon or amorphous carbon or other conjunctions Suitable material, the forming process of the first pseudo- grid 203, second pseudo- grid 204 and third puppet grid 205 are as follows: in the semiconductor substrate 200 The pseudo- gate material layer of upper formation；Patterned photoresist layer is formed in the pseudo- gate material layer；With the patterned photoresist Layer is puppet gate material layer described in mask etching, and the first 204 and of pseudo- the 203, second pseudo- grid of grid is formed in the semiconductor substrate 200 Third puppet grid 205.
In the present embodiment, the first pseudo- grid 204 of pseudo- grid 203, second and third puppet grid 205 and semiconductor substrate 200 it Between be also formed with high-K dielectric layer 209.
Dielectric constant K >=3.5 of the high-K dielectric layer 209, in one embodiment, the material of the high-K gate dielectric layer 209 Material can be HfO2、TiO2、HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3Or BaSrTiO or other Suitable high K dielectric material.
It in other embodiments of the invention, can also be in subsequent the first pseudo- grid 204 of pseudo- grid 203, second of removal and third When pseudo- grid 205 form the first groove, the second groove and third groove, in first groove, the second groove and third groove Side wall and bottom surface form high-K dielectric layer.
In the present embodiment, the described first pseudo- grid 204 of pseudo- grid 203, second are identical with the size of third puppet grid 205.At other In embodiment, the size of the described first pseudo- grid 204 of pseudo- grid 203, second and third puppet grid 205 can be different.
In one embodiment, between the first pseudo- grid 204 of pseudo- grid 203, second and third puppet grid 205 and semiconductor substrate 200 Silicon oxide layer can also be formed.
It is also formed with side wall on the two sides side wall of the described first pseudo- grid 204 of pseudo- grid 203, second and third puppet grid 205, it is described Side wall can be single-layer or multi-layer (>=2 layers) stacked structure.
In one embodiment, the side wall 203 is double stacked structure, including is located at the first pseudo- grid of pseudo- grid 203, second 204 and the offset side wall in 205 sidewall surfaces of third puppet grid and the main side wall that is disposed offset from side wall.
The material of the offset side wall is silica or other suitable materials, and the formation process of offset side wall is thermal oxide Or depositing operation, the material of the main side wall are silicon nitride, formation process is deposition and etching technics.
After forming offset side wall, further includes: using the pseudo- grid and offset side wall as exposure mask, to the semiconductor substrate into The first ion implanting of row, in partly leading for the described first pseudo- grid 204 of pseudo- grid 203, second and third puppet grid 205 and offset side wall two sides Shallow doped region is formed in body substrate.
After forming shallow doped region, main side wall, the formation of the main side wall are formed on the surface of the offset side wall Journey are as follows: form the pseudo- grid 204 of the described first pseudo- grid 203, second of covering, third puppet grid 205, offset side wall and semiconductor substrate 200 The spacer material layer on surface；Without spacer material layer described in mask etching, main side wall is formed on offset side wall surface.The main side wall It can be single-layer or multi-layer stacked structure.
After forming main side wall, further includes: with the main side wall and pseudo- grid 202 it is exposure mask, carries out the second ion implanting, Deep doped region is formed in the first pseudo- grid 204 of pseudo- grid 203, second, third puppet grid 205 and the semiconductor substrate 200 of main side wall two sides, The depth doped region and shallow doped region constitute source region or the drain region of transistor.
The type for the foreign ion that first ion implanting and the second ion implanting are injected is identical, the foreign ion packet N-type impurity ion and p type impurity ion are included, the N-type impurity ion is phosphonium ion, arsenic ion or antimony ion, the p type impurity Ion is boron ion, gallium ion or indium ion.The type of first ion implanting and the second ion implanting implanting impurity ion Selected according to the type of transistor to be formed, when transistor to be formed be N-type transistor when, the first ion implanting and The foreign ion of second ion implanting is the foreign ion of N-type, when transistor to be formed is P-type transistor, the first ion The foreign ion of injection and the second ion implanting is the foreign ion of p-type.
In the present embodiment, after forming the first pseudo- grid 203 and side wall, further includes: be with the described first pseudo- grid 203 and side wall Exposure mask etches the semiconductor substrate 200, and the is formed in the semiconductor substrate 200 of the described first pseudo- grid 203 and side wall two sides One groove；Then the first stressor layers are filled in first groove, form the first stress source/drain region, the material of first stressor layers Material is SiGe.
After forming the second pseudo- grid 204, third puppet grid 205 and side wall, further includes: pseudo- with the described second pseudo- grid 204, third Grid 205 and side wall are exposure mask, etch the semiconductor substrate 200, the semiconductor substrate 200 in the described second 204 two sides of pseudo- grid Interior formation second groove forms third groove in the semiconductor substrate 200 of 205 two sides of third puppet grid；Described second The second stressor layers are filled in groove and third groove, form the second stress source/drain region, the shape in third groove in second groove At tertiary stress source/drain region, the material of second stressor layers is silicon carbide.
200, the first pseudo- grid 204 of pseudo- grid 203, second of semiconductor substrate and third are covered with continued reference to FIG. 1, being formed The dielectric layer 202 of pseudo- grid 205, the surface of the dielectric layer 202 and the first pseudo- grid 204 of pseudo- grid 203, second and third puppet grid 205 Top surface flush.
The material of the dielectric layer 202 is silica, fluorine silica glass or other suitable materials.
The forming process of the dielectric layer 202 are as follows: formed and cover the pseudo- grid 203, second of the semiconductor substrate 200, first The layer of dielectric material of pseudo- grid 204 and third puppet grid 205；The layer of dielectric material is planarized, with the first pseudo- grid of pseudo- grid 203, second 204 and third puppet grid 205 surface as stop-layer, form dielectric layer 202.
With reference to Fig. 2, the described first pseudo- grid 203 (referring to Fig. 1), the second pseudo- grid 204 (referring to Fig. 1) and third puppet grid are removed 205 (referring to Fig. 1), form the first groove 206, the second groove 207 and third groove 208.
Remove the described first pseudo- grid 204 of pseudo- grid 203, second and third puppet grid 205 using wet etching, dry etching or The technique that person's wet etching and dry etching combine.In one embodiment, using the pseudo- grid of wet etching removal described first 203, the second pseudo- grid 204 and third puppet grid 205, the solution that wet etching uses for KOH or TMAH (tetramethylammonium hydroxide) or NH3.H2O。
After removing the described first pseudo- grid 204 of pseudo- grid 203, second and third puppet grid 205, what corresponding first area 11 was formed The density of first groove 206 and the second groove 207 is greater than 208 density of third groove that second area 12 is formed.First groove 206 Refer to the quantity of the first groove 206 and the second groove 207 in unit area, third groove with the density of the second groove 207 208 density refers to the quantity of the third groove 208 in unit area.
With reference to Fig. 3, in the high-K dielectric layer 209 and the first groove 206, the second groove 207 and third groove 208 Side wall and bottom surface formed the first metal layer 210；Second metal layer 211 is formed on the first metal layer 210.
The first metal layer 210 and second metal layer 211 are used to adjust the work function of transistor, the first metal layer 210 and second metal layer 211 material it is not identical.
The first metal layer 210 can be single-layer or multi-layer (>=2 layers) stacked structure, and the second metal layer 211 can Think single-layer or multi-layer (>=2 layers) stacked structure.
In one embodiment, the material of the first metal layer 210 be Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN, One or more of TiAlN.The material of the second metal layer 211 be Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN, One or more of TiAlN.
In the present embodiment, the material of the first metal layer 210 is TaN, and the material of the second metal layer 211 is TiN, The first metal layer 210 and second metal layer 211 with a thickness of 60~200 angstroms, the first metal layer 210 and second metal layer 211 Formation process is chemical vapor deposition process or sputtering.
With reference to Fig. 4, inorganic fill layer 212 is formed in second metal layer 211, the filling of inorganic fill layer 212 full first is recessed Slot 206 (referring to Fig. 3), the second groove 207 (referring to Fig. 3) and third groove 208 (referring to Fig. 3), and second area 12 is inorganic The thickness of filled layer 212 is greater than the thickness of the inorganic fill layer 212 of first area 11.
It include element silicon in the inorganic fill layer 212, the formation process of the inorganic fill layer 212 is spin coating.
When forming inorganic fill layer 212 using spin coating proceeding, due to the first groove 206 and second of the formation of first area 11 The density of groove 207 is greater than 208 density of third groove that second area 12 is formed, and when spin coating, fills the first groove 206 and second The organic filler material that groove 207 consumes can be greater than the organic filler material that filling third groove 208 consumes, so that formed the The thickness of the inorganic fill layer 212 in two regions 12 is greater than the thickness of the inorganic fill layer 212 of first area 11.In an embodiment In, the difference in thickness of 12 inorganic fill layer 212 of the first area 11 and second area is 400~600 angstroms.
With reference to Fig. 5, reflowable organic coating 213 is formed on the inorganic fill layer 212, second area 12 returns The thickness of the organic coating 213 of stream is less than the thickness of the reflowable organic coating 213 of first area 11.
Reflowable 213 one side of organic coating as it is subsequent be exposed technique to photoresist layer when antireflection Coating；On the other hand, the reflowable organic coating 213 is used to eliminate the first area 11 and second of inorganic fill layer 212 Difference in thickness on region 12 is put down so that the overall structure that inorganic fill layer 212 and reflowable organic coating 213 are constituted has Smooth surface, i.e., so that on 212 surface of second metal layer on first area 11 and second area 12 by inorganic fill layer 212 The equal or difference in thickness very little with the integrally-built thickness that reflowable organic coating 213 is constituted, it is subsequent to perform etching step When rapid, so that or thickness equal with the thickness of inorganic fill layer remaining on second area 12 on NMOS area 21 in first area Difference very little.
The forming process of the reflowable organic coating 213 are as follows: formed on inorganic fill layer 212 using spin coating proceeding Reflowable antireflection material layer 213；The first heat treatment is carried out to the reflowable antireflection material layer at the first temperature； After first heat treatment, the second heat treatment is carried out to the reflowable antireflection material layer at the second temperature, is formed reflowable Organic coating 213, second temperature be greater than the first temperature.
First temperature is higher than the glass transition temperature of organic-containing materials and is lower than Cross-linked temperature, in the first temperature Under, organic-containing materials can move freely, under gravity, organic-containing materials can from highly higher side (second 212 surface of inorganic fill layer in region 12) it is moved to the place of height lower (212 surface of inorganic fill layer of first area 11) It is dynamic, until the top surface of first area 11 and the organic coating on second area 12 height flushes or difference in height very little, institute The crosslinking temperature that second temperature is higher than reflowable organic-containing materials is stated, the reflowable organic-containing materials can be handed over Connection reaction, forms stable immovable organic coating.
In one embodiment, first temperature is 50~160 degrees Celsius, and the time of the first heat treatment is 1min- 30min, the second temperature are 180~350 degrees Celsius, and the time of the second heat treatment is 1min-30min, so that is formed can The organic coating of reflux eliminate inorganic fill layer 212 first area 11 and the difference in thickness on second area 12 effect compared with It is good, and will not influence the performance of antireflection.
In one embodiment, the overall thickness of the inorganic fill layer 212 and reflowable organic coating 213 be 500~ 3000 angstroms, the overall thickness of the inorganic fill layer 212 and reflowable organic coating 213 of the first area 11 and second area 12 Difference value is less than 100 angstroms.
With reference to Fig. 6 and Fig. 7, patterned photoresist layer 214 is formed on the reflowable organic coating 213, it is described Patterned photoresist layer 214 exposes the reflowable organic coating of the NMOS area 12 in second area 12 and first area 213 surfaces.
The forming process of patterned photoresist layer 214 are as follows: using spin coating proceeding in the reflowable organic coating 213 Upper formation photoresist material layer 225；Using exposure and imaging technique, graphically the photoresist material layer 225, formation are graphical Photoresist layer 214.
It is exposure mask with the patterned photoresist layer 214 in conjunction with reference Fig. 8~Figure 10, etching removal second area 12 Reflowable organic coating 213, inorganic fill layer 212 and second metal layer 211 on NMOS area 21, expose the first metal The surface of layer 210.
Etching removal second area 12 and reflowable organic coating 213 on NMOS area 21, inorganic fill layer 212 and the The step of two metal layer 211 includes the first etch step, the second etch step and third etch step: referring to FIG. 8, carrying out the One etch step, etching remove the reflowable organic coating 213 and part inorganic fill on second area 12 and NMOS area 21 Layer 212；Referring to FIG. 9, carrying out the second etch step, remaining inorganic fill layer on second area 12 and NMOS area 21 is removed 212 (referring to Fig. 8), expose the surface of the second metal layer 211 on second area 12 and NMOS area 21；With reference to Figure 10, carry out Third etch step, etching remove the second metal layer 211 on second area 12 and NMOS area 21, expose 12 He of second area The surface of the first metal layer 210 on NMOS area 21.
First etch step is plasma etching industrial, and the gas that the plasma etching industrial uses is carbon fluorination Close object gas and oxygen (O2), the fluorocarbon gas is CF4、C2F6、C3F8、C4F8One or more of, carbon fluorination is closed The flow of object gas is 20~200sccm, O2Flow be 5~20sccm, chamber pressure be 5~30mTorr, the function of radio frequency source Rate is 100 watts~1000 watts, and the power of bias source is 50 watts~300 watts.
After carrying out the first etch step, the inorganic fill layer 212 of remainder thickness on second area 12 and NMOS area 21 Purpose be the over etching or damage for preventing the first etch step to second metal layer 210, cause second area 12 and NMOS area 21 thickness is inconsistent, is unfavorable for the control of thickness etching process.In one embodiment, second area 12 and NMOS area 21 Thickness≤50 angstrom of upper remaining inorganic fill layer 212, preventing the first etch step to the over etching of second metal layer 210 or While damage, reduce the technology difficulty of the second etch step.
Second etch step is plasma etching industrial, and the gas that the plasma etching industrial uses is fluorocarbon Gas, the fluorocarbon gas are CF4、C2F6、C3F8、C4F8One or more of, the flow of fluorocarbon gas For 10~100sccm, chamber pressure is 5~30mTorr, and the power of radio frequency source is 100 watts~800 watts, and the power of bias source is 20 watts~150 watts, so that the process for removing remaining inorganic fill layer 212 more mitigates, reduce the second metal layer to bottom 211 damage so that second area 12 is identical with the thickness of the second metal layer 211 of the exposure on NMOS area 21 or difference very It is small.
The third etch step be wet etching, the etching solution that the wet etching uses for hydrochloric acid, hydrogen peroxide and The mixed solution of water, in one embodiment, the volume ratio of hydrochloric acid, hydrogen peroxide and water is 1:1:5~2:5 in the mixed solution: 30, while clean removal second metal layer, prevent etching process to the of exposure on second area 12 and NMOS area 21 One metal layer 210 causes to damage.
In the present embodiment, before etching, due to 212 surface of second metal layer on first area 11 and second area 12 On the integrally-built thickness being made of inorganic fill layer 212 with reflowable organic coating 213 is equal or difference in thickness very Small, after carrying out the first etch step, second area 12 and 212 thickness of inorganic fill layer remaining on NMOS area 21 are equal or thick Difference very little is spent, thus when carrying out the second etch step, remaining inorganic fill layer 212 on second area 12 and NMOS area 21 The time of removal is identical or time difference very little, i.e. remaining inorganic fill layer on removal second area 12 and NMOS area 21 212 time differences successive there is no removal, thus when carrying out third etch step, remove second area 12 and NMOS area 21 On time of second metal layer 211 be identical or time difference very little, i.e., the on removal second area 12 and NMOS area 21 Two metal layers 211 are there is no successive time difference is removed, so that third etch step will not be to second area 12 or NMOS area The first metal layer 210 on 21 generates etching injury, so that the second area 12 of exposure or NMOS area 21 after third etch step On the thickness of the first metal layer 211 be consistent, the gold of the transistor finally formed on second area 12 and NMOS area 21 Belong to layer to be consistent the regulation performance of work function.
With reference to Figure 10, remaining patterned photoresist layer 214 (referring to Fig. 9), reflowable organic coating 213 are removed (referring to Fig. 9), inorganic fill layer 212 (referring to Fig. 9), exposes 211 surface of second metal layer in the area PMOS 22.
Removing remaining patterned photoresist layer 214, reflowable organic coating 213, inorganic fill layer 212 can adopt With wet etching or dry etch process.
With reference to Figure 11, the first metal gate electrode 215, the first metal are formed in the second metal layer 210 in the area PMOS 22 First groove of the filling of gate electrode 215 206 (referring to Figure 10), forms the second metal on the first metal layer 210 on NMOS area 21 Gate electrode 217, the second groove of the second metal gate electrode 217 filling 207 (referring to Figure 10), the first metal on second area 12 Third metal gate electrode 220 is formed on layer 210, third metal gate electrode 220 fills full third groove 208 (referring to Figure 10).
The forming process of first metal gate electrode 215, the second metal gate electrode 217 and third metal gate electrode 219 Are as follows: form second metal on 210 surface of the first metal layer and the area PMOS 22 that cover the second area 12 and NMOS area 21 The metal layer on 211 surface of layer, the metal layer fill full first groove 206, the second groove 207, third groove 208；Using change It learns mechanical milling tech and removes metal layer, second metal layer 211 and the first metal layer 210 on 202 surface of dielectric layer, the The first metal gate electrode 215 is formed in one groove 206, the second metal gate electrode 217 is formed in the second groove 207, in third Third metal gate electrode 220 is formed in groove 208.
In one embodiment, the material of the metal layer is W, Al, Cu or other suitable metals.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the range of restriction.

Claims (20)

1. a kind of forming method of semiconductor structure characterized by comprising
Semiconductor substrate is provided, the semiconductor substrate includes first area and second area, and the first area includes NMOS Area and the area PMOS have the several first pseudo- grid in the semiconductor substrate in the area PMOS, have in the semiconductor substrate of NMOS area several Second pseudo- grid have several third puppet grid, the density of the described first pseudo- grid and the second pseudo- grid in the semiconductor substrate of second area Greater than the density of third puppet grid, between the described first pseudo- grid, the second pseudo- grid and third puppet grid and semiconductor substrate there is high K to be situated between The density of matter layer, the first pseudo- grid and the second pseudo- grid is the quantity of the first pseudo- grid and the second pseudo- grid in unit area, described the The density of three pseudo- grid is the quantity of third puppet grid in unit area；
Formed cover the semiconductor substrate, the first pseudo- grid, the second pseudo- grid and third puppet grid dielectric layer, the table of the dielectric layer Face is flushed with the top surface of the first pseudo- grid, the second pseudo- grid and third puppet grid；
The described first pseudo- grid, the second pseudo- grid and third puppet grid are removed, the first groove, the second groove and third groove are formed；
The first metal is formed in the high-K dielectric layer and in the sidewall surfaces of the first groove, the second groove and third groove Layer；
Second metal layer is formed on the first metal layer；
Inorganic fill layer is formed in second metal layer, inorganic fill layer fills full first groove, the second groove and third groove, And the thickness of the inorganic fill layer of second area is greater than the thickness of the inorganic fill layer of first area；
Reflowable organic coating is formed on the inorganic fill layer, the thickness of the reflowable organic coating of second area is small In the thickness of the reflowable organic coating of first area, the reflowable organic coating is used to eliminate the of inorganic fill layer Difference in thickness on one region and second area, so that the overall structure tool that inorganic fill layer and reflowable organic coating are constituted There is flat surface；
Patterned photoresist layer is formed on the reflowable organic coating, the patterned photoresist layer exposes The reflowable organic coating layer surface of NMOS area in two regions and first area；
The reflowable organic coating on NMOS area, inorganic fill layer and second in etching removal second area and first area Metal layer exposes the surface of the first metal layer.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that include silicon in the inorganic fill layer Element.
3. the forming method of semiconductor structure as claimed in claim 2, which is characterized in that the formation work of the inorganic fill layer Skill is spin coating.
4. the forming method of semiconductor structure as described in claim 1, which is characterized in that the first area and second area The difference in thickness of inorganic fill layer is 400~600 angstroms.
5. the forming method of semiconductor structure as described in claim 1, which is characterized in that the reflowable organic coating Forming process are as follows: form reflowable antireflection material layer on inorganic fill layer using spin coating proceeding；It is right at the first temperature The reflowable antireflection material layer carries out the first heat treatment；After first heat treatment, at the second temperature to described reflowable Antireflection material layer carry out the second heat treatment, form reflowable organic coating, second temperature is greater than the first temperature.
6. the forming method of semiconductor structure as claimed in claim 5, which is characterized in that first temperature is higher than organic painting The glass transition temperature of layer material and be lower than Cross-linked temperature, the second temperature be higher than reflowable organic-containing materials crosslinking Temperature.
7. the forming method of semiconductor structure as claimed in claim 6, which is characterized in that first temperature is 50~160 Degree Celsius, the time of the first heat treatment is 1min-30min.
8. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that the second temperature is 180~350 Degree Celsius, the time of the second heat treatment is 1min-30min.
9. the forming method of semiconductor structure as described in claim 1, which is characterized in that the inorganic fill layer and reflowable Organic coating overall thickness be 500~3000 angstroms.
10. the forming method of the semiconductor structure as described in claim 1 or 9, which is characterized in that the first area and second The inorganic fill layer in region and the overall thickness difference value of reflowable organic coating are less than 100 angstroms.
11. the forming method of semiconductor structure as described in claim 1, which is characterized in that the first metal layer and second The material of metal layer is not identical.
12. the forming method of semiconductor structure as claimed in claim 11, which is characterized in that the material of the first metal layer For one or more of Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN, TiAlN.
13. the forming method of semiconductor structure as claimed in claim 11, which is characterized in that the material of the second metal layer For one or more of Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN, TiAlN.
14. the forming method of semiconductor structure as described in claim 1, which is characterized in that it is remaining to further comprise the steps of: removal Reflowable organic coating, inorganic fill layer, expose the second metal layer surface in the area PMOS；The second gold medal in the area PMOS Belong to and form the first metal gate electrode on layer, the first metal gate electrode fills the first groove, on the first metal layer on NMOS area The second metal gate electrode is formed, the second metal gate electrode is filled the second groove, formed on the first metal layer on the second region Third metal gate electrode, third metal gate electrode fill full third groove.
15. the forming method of semiconductor structure as described in claim 1, which is characterized in that etching removal second area and The step of reflowable organic coating, inorganic fill layer and second metal layer on NMOS area includes the first etch step, second Etch step and third etch step carry out the first etch step, reflowable on etching removal second area and NMOS area Organic coating and part inorganic fill layer；It carries out the second etch step, removes remaining on second area and NMOS area inorganic fill out Layer is filled, the second metal layer surface on second area and NMOS area is exposed；Carry out third etch step, the secondth area of etching removal Second metal layer on domain and NMOS area exposes the first metal layer surface on second area and NMOS area.
16. the forming method of semiconductor structure as claimed in claim 15, which is characterized in that after carrying out the first etch step, Thickness≤50 angstrom of remaining inorganic fill layer on second area and NMOS area.
17. the forming method of semiconductor structure as claimed in claim 15, which is characterized in that the first etch step is plasma Etching technics, the gas that the plasma etching industrial uses is fluorocarbon gas and oxygen.
18. the forming method of semiconductor structure as claimed in claim 15, which is characterized in that the second etch step is plasma Etching technics, the gas that the plasma etching industrial uses is fluorocarbon gas and oxygen.
19. the forming method of semiconductor structure as claimed in claim 15, which is characterized in that the third etch step is wet Method etching.
20. the forming method of semiconductor structure as claimed in claim 19, which is characterized in that the quarter that the wet etching uses Erosion solution is the mixed solution of hydrochloric acid, hydrogen peroxide and water.
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