CN106294257A - A kind of experimental provision and experimental system - Google Patents
A kind of experimental provision and experimental system Download PDFInfo
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- CN106294257A CN106294257A CN201610656813.5A CN201610656813A CN106294257A CN 106294257 A CN106294257 A CN 106294257A CN 201610656813 A CN201610656813 A CN 201610656813A CN 106294257 A CN106294257 A CN 106294257A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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Abstract
The invention discloses a kind of experimental provision and experimental system, belong to field of computer technology, solve the technical problem that between existing experimental facilities and experiment server, transfer rate is low.This experimental provision includes: experimental considerations unit, and it is used for writing experimental code and tests, and carries out the communication of the network data produced in experimentation with server；Communication unit, it gives described experimental considerations unit for the experiment control Data Concurrent issued receiving server, it is achieved server is for the control of experimental considerations unit, and carries out the transmission of experimental data between server and described test unit.
Description
Technical field
The present invention relates to field of computer technology, specifically, relate to a kind of experimental provision and experimental system.
Background technology
The development trend of the most domestic computer hardware curriculum experiment equipment is centralized management, i.e. uses server set
Middle management misconduct equipment, has the solution of oneself, a part to use serial ports as logical in this development trend Xia Ge colleges and universities
Letter interface, but the mode transmission speed of this use serial ports becomes bottleneck；Another part use USB interface, but due to
Big and transmission range restriction one station server of USB interface power consumption can only manage little experimental facilities；Itself and part
Being to use other kinds of slow interface, existing equipment of tracing it to its cause does not has processor to process high-speed data, Zhi Nengtong yet
Cross programming device simulation low-speed device.
Therefore, a kind of experiment dress that can solve the problem that between existing experimental facilities and experiment server, transfer rate is low is needed badly
Put.
Summary of the invention
It is an object of the invention to provide a kind of experimental provision and experimental system, to solve existing experimental facilities and experiment
The technical problem that between server, transfer rate is low.
The present invention provides a kind of experimental provision, and this device includes:
Experimental considerations unit, it is used for writing experimental code and tests, and carries out the net of generation in experimentation with server
The communication of network data；
Communication unit, it gives described experimental considerations unit for the experiment control Data Concurrent issued receiving server, real
Existing server is for the control of experimental considerations unit, and carries out the transmission of experimental data between server and described test unit.
Being provided with high speed network interface in described communication unit, described communication unit is carried out with server by described high speed network interface
Described experiment control data and the transmission of experimental data.
Being provided with experiment network interface in described experimental considerations unit, described experimental considerations unit is by described experiment network interface and described server
Carry out the communication of the network data produced in experimentation.
Described experimental considerations unit and described communication unit carry out described experiment control data and experimental data by high-speed bus
Transmission.
Described communication unit and described experimental considerations unit are connected with server by cable interface or back panel connector.
The present invention also provides for a kind of experimental system, and this system includes:
Multiple described experimental provisions；
Server；
Described communication unit and server carry out the communication of experiment control data and experimental data, constitute and control network, institute
State experimental considerations unit and carry out the communication of the network data of generation in experimentation with server, constitute Experimental Network.
Described control network is by Experimental Network described in described server monitoring, and sends data in described Experimental Network
And/or from described Experimental Network, gather data.
The high-speed data that the experimental provision of present invention offer and experimental system are capable of between server and experimental facilities
Exchange and management, employ high speed system bus and downstream experimental facilities communication, coordinates 100M network interface to make data transmission bauds
It is greatly improved.Experimental provision hardware configuration include embedded solution (arm9 processor, internal memory, nandflash,
Serial ports, USB, wifi, network interface, touch screen), control FPGA, experiment FPGA, experiment network interface and be used for supporting all kinds of realities of experiment
Test interface.Present invention also offers server experimental data based on the exploitation of hardware above basic engineering exchange at a high speed and control association
View, high speed system bus drive, control FPGA bridging logic and dual network structure.
Other features and advantages of the present invention will illustrate in the following description, and, becoming from description of part
Obtain it is clear that or understand by implementing the present invention.The purpose of the present invention and other advantages can be by description, rights
Structure specifically noted in claim and accompanying drawing realizes and obtains.
Accompanying drawing explanation
For the technical scheme in the clearer explanation embodiment of the present invention, required in embodiment being described below
Accompanying drawing does simply to be introduced:
Fig. 1 is the experimental provision schematic diagram that the embodiment of the present invention provides；
Fig. 2 is the experimental considerations unit schematic diagram that the embodiment of the present invention provides；
Fig. 3 is that the experimental provision that the embodiment of the present invention provides uses schematic diagram；
Fig. 4 is the experimental system schematic diagram that the embodiment of the present invention provides；
Fig. 5 is that the ahb bus of embodiment of the present invention offer is from equipment state machine schematic diagram.
Detailed description of the invention
Describe embodiments of the present invention in detail below with reference to drawings and Examples, whereby how the present invention is applied
Technological means solves technical problem, and the process that realizes reaching technique effect can fully understand and implement according to this.Need explanation
As long as not constituting conflict, each embodiment in the present invention and each feature in each embodiment can be combined with each other,
The technical scheme formed is all within protection scope of the present invention.
The embodiment of the present invention provides a kind of experimental provision, and as shown in figures 1 and 3, this device includes: communication unit 1, experiment
Unit 2.Experimental considerations unit 2 is used for writing experimental code and tests, and carries out the network number of generation in experimentation with server
According to communication.Communication unit 1 gives experimental considerations unit for the experiment control Data Concurrent issued receiving server, it is achieved service
Device is for the control of experimental considerations unit, and carries out the transmission of experimental data between server and test unit.
In one embodiment of the invention, the function of communication unit 1 is integrated on ARM-CPU, sets in communication unit 1
Being equipped with high speed network interface, communication unit 1 carries out experiment control data and experimental data by high speed network interface and upstream equipment server
Communication, optionally, high speed network interface select 100-M network Ethernet.That ARM-CPU selects is the S3C2440 of the ARM9 series of Samsung
Chip, its dominant frequency is 400Mhz, and such performance can meet the demand that high-speed data processes completely.By ARM-CPU and clothes
Business device communication, its transmission speed will not become the bottleneck of experimental system, for by Server remote cross-platform Control release device
Provide the foundation hardware condition.
Further, experimental considerations unit 2 includes as shown in Figures 2 and 3: bus control module 7, experiment module 3, memory module
4, experiment control module 5 and parsing module 6.
Wherein, experiment module 3 writes experimental code for student and tests, and experiment module 3 is fpga chip, at this
In bright concrete application, it is referred to as testing FPGA by this fpga chip.Experiment FPGA opens to student by the burned experimental code of student
Complete experiment, experiment FPGA additionally provides conventional experimental interface LED, charactron, serial ports etc..Experiment module 3 is provided with
Testing network interface, experiment module 3, by experiment network interface and server communication, builds Experimental Network, and this experiment network interface is Experimental Network
Access port.
Wherein, serial ports provides the another kind of access way of experiment FPGA.Display lamp is for showing the number on experiment FPGA
According to, allow experimenter understand the content of current data.Charactron for need use numeral method experiment in, carry out data
Display.Hand switch is needing hand switch manually to dial in the experiment of data, manually dials in number to experiment FPGA for experimenter
According to.
In the experimental provision that the embodiment of the present invention provides, also include wifi interface, USB interface, serial ports and LCD screen.
Wifi interface, USB interface, serial ports and lcd controller are integrated in ARM-CPU, collectively form embedded solution so that
Experimental provision can access in several ways, and the TFT of STN and the 16M color of lcd controller the highest support 4K color, including
One LCD DMA, can give student one visual interface clearly, and student can test more easily.
Bus control module 7 is connected by high-speed bus with communication unit 1, and bus control module 7 is for by the most total
Line and communication unit 1 carry out the communication of experiment control data and experimental data.In embodiments of the present invention, high-speed bus selects height
Level high performance bus (Advanced High Performance Bus, AHB) bus, the most senior high property
Ahb bus can be collectively referred to as below bus, its operating frequency be 100MHZ data bit width be 32.Bus control module 7 passes through
Ahb bus and communication unit 1 carry out data communication.
Further, bus control module 7 be additionally operable to distribute to the address of high-speed bus experiment module, memory module and
Experiment control module so that experiment module, memory module and experiment control module can be entered by high-speed bus with communication unit
Row communication.
Experiment control module 5 completes experiment for Control release module.Code in experiment control module 5 is for experiment
Design in advance, it will by the bus state required for particular experiment around experimental considerations unit fpga chip and monitor logic and join
Put complete.Experiment module fpga chip will need the signal observed obtained by register access bus in whole experimentation
Acquirement is arrived, and sends up.
Parsing module 6 resolves for experiment control data and the experimental data receiving bus control module, and
Data content after resolving is sent to experiment module, memory module and experiment control module.
Bus control module 7, experiment control module 5 and parsing module 6 are integrated on one piece of fpga chip, real in the present invention
Execute in example and be referred to as controlling FPGA by this fpga chip.
Memory module 4 is used for storing experimental data, and memory module is memorizer SRAM.At needs storage code and some literary compositions
In the experiment of part, code is write in memory module 4 by we.Memory module 4 read-write is to be sent by experiment control module 5
's.When needs memory write when, memory module is sent to the relevant write signal of memorizer and address, when reading memorizer
Time, memory module is sent to the relevant read signal of memorizer and address.
In embodiments of the present invention, the function of communication unit 1 is integrated on ARM-CPU, bus control module 7 experiment control
Module 5 and parsing module 6 are integrated on one piece of fpga chip.This pattern controlled as justifying core using ARM why can
Accessing employing, depend on the high speed development of FPGA and ARM, function is the most powerful, number of pin is abundant, cost is constantly pressed
Contracting.And use the benefit of this control model to be also apparent from, use ARM can be significantly reduced down as controlling CPU
Trip controls the complexity of fpga logic so that whole system can more rapid more stable operation.
Optionally, communication unit and experimental considerations unit are connected with server by cable interface or back panel connector.Most real
Testing platform and all can have two kinds of use patterns, one is experimental box pattern, and this pattern directly uses netting twine to access with server even
Connect；Another kind is rack pattern, is connected with the backboard of cabinet by backplane connector；In embodiments of the present invention, it is considered to these are two years old
Plant use pattern, devise one group of wire jumper and can select to use cable interface RJ45 access server still to use back panel connector
Access server.
The embodiment of the present invention provides a kind of experimental system, and as shown in Figure 4, this experimental system includes: multiple experimental provisions and
Server.
Communication unit in experimental provision and server carry out the communication of experiment control data and experimental data, constitute and control
Network.Network interface in the most embedded solution is linked into control network with server communication；Controlling network is master network, wherein
Control network process be mainly responsible for experimental provision communication, it is achieved transmission control command, the function such as experimental data.
Experimental considerations unit in experimental provision and server carry out the communication of Experimental Network data, constitute Experimental Network.Experiment
The experiment network interface of FPGA configuration is linked in Experimental Network.Experimental Network process in Experimental Network is responsible for safeguarding that student passes through reality
Test the Experimental Network that network interface is built.Controlling network and Experimental Network is two relatively independent networks, Experimental Network will not be to control
Network processed has any impact.
Further, control network by server monitoring Experimental Network, and send in Experimental Network data and/or from
Experimental Network gathers data.Can be by controlling in network process monitoring and sampling experimental network server end student
The correctness of data verification experiment, student can also send test data by controlling network process to Experimental Network, conveniently learn
Give birth to network experiment.
The embodiment of the present invention provides a kind of bus driver method of ARM-CPU and experiment FPGA high-speed bus, this driving side
Method includes:
In internal memory, discharge the working place of high-speed bus according to cdev and realize the unloading in internal memory of high-speed bus.
The secondary device number device number as high-speed bus is applied in LINUX miscellaneus unit drives.ARM chip S2C2440
Internal memory map provide two kinds of start-up mode one be norflash start-up mode another kind be nandflash start-up mode.This
It is designed with nandflash start-up mode.Ahb bus is that S3C2440 Memory Controller provides 8 available BANK skies
Between, each BANK space provides the space of 128MB, and taken has bank0 (NC), bank4 (DM9000), bank5
(SDRAM), bank6 (SDRAM), remaining be the free time.The bank5 addressing space as bus is employed in the design,
Its initial address is 0x28000000.The space having considered bus in embodiments of the present invention uses size and design
Difficulty has only applied for the address space addressing space as bus of 2M in internal memory.
In the design, ahb bus drives is Shen in flush type LINUX miscellaneus unit (i.e. major device number is 10) drives
Please secondary device number 54 as oneself device number (i.e. major device number be secondary devices No. 10 be 54), use miscellaneus unit to drive application
The benefit driving device number is that exploitation is relatively easy and miscellaneus unit can automatically create device node without mknod manual creation
Device node.
The cdev of high-speed bus, the operation of high-speed bus is generated according to described device number, device name and action type
Type includes: opens operation, close operation, read operation and write operation；
The cdev structure of ahb bus is slightly different with the cdev structure of common char device driver, and reason is ahb bus
Being a subset of miscellaneus unit, cdev structure has been done and has been encapsulated the device number of actually ahb bus application and be by miscellaneus unit
The secondary device number that miscellaneus unit is equipped with, the following is the cdev structure after encapsulation:
Wherein macrodefinition MISC_DYNAMIC_MINOR function is to apply for secondary device number at random, and in the design, application is to equipment
Number it is 54.
DEVICE_NAME: this is macrodefined is device name, at the entitled fpga_ahb of the equipment defined in the design.
Dev_fops: this member definition's is that file_operations structure is defined as follows:
Can be seen that in the design, ahb bus drives the operation supported to have open, close, read, write to operate.
In internal memory, the corresponding memory headroom working place as high-speed bus is applied for, it is achieved high-speed bus according to cdev
The loading in internal memory.Device number and file_operations structure can be carried out initialized work after having designed
Making, ahb bus initializes work to be completed to be had bank5 is mapped to memory headroom, applies for equipment according to cdev.Corresponding generation
Code:
In the design, employ Dram mapping function ioremap, applied for that the memory headroom of 2M is as ahb bus
Working place；Misc_register function is facility registration function.
According to cdev discharge in internal memory the working place of described high-speed bus realize described high-speed bus in internal memory
Unloading.The bus operation that needed of unloading is corresponding with initialization, in initialization, have mapped memory headroom so
It is to be accomplished by releasing memory in bus unloading；Have registered equipment when initializing, be this equipment of just should nullifying in unloading.Accordingly
Code:
Ahb bus read operation is relatively simple, and there are 2 points in noticeable place: first is called readw function
Fpga_bas is to obtain in bus initialization process to bus operation base address, is a global variable, and offset is to read behaviour
Make incoming offset address kbuf=readw ((void*) (fpga_base+offset))；Another point is exactly copy_to_user
(buf, &kbuf, len) will go up data kfuf that an operation reads back and copy user's space to from kernel spacing.
The process of ahb bus write operation from read substantially similar the most different be a little to need to copy data from user's space
Shellfish is to kernel spacing.Respective code:
The function controlling FPGA realization is that the integrated parsing module in equipment, control FPGA as ahb bus completes
Resolving AHB line data content, experiment control module integrated in controlling FPGA completes experiment for Control release FPGA.
Ahb bus signal list as shown in table 1,
ADDR [26:0] is 27 AHB address bus；
DATA [31:0] is 32 AHB data/address bus；
NGCS [7:0] is that ahb bus enables signal, and 0 effectively, and this chip of S3C2440 supports the access of 8 BANK,
BANK5 is distributed to control FPGA in driving and uses by ahb bus；
NW is ahb bus write signal, and 0 is effective；
NOE is ahb bus read signal, and 0 is effective；
Table 1
The simple mode using ahb bus in embodiments of the present invention the most only used ADDR, DATA, nGCS,
This group signal of nWE, nOE, remaining nXBREQ, nXBACK, nWAIT signal also useless uses, but at FPGA internal logic
In need to be entered as these 3 signals high-impedance state (i.e. ' Z'), ARM otherwise can be caused to crash.
About ahb bus accessing time sequence, when FPGA logical code designs can according to timing diagram complete nGCS, nWe,
NOE is Low level effective.In this sequential chart, the parameter such as tacs, tcos, tacc can change AHB by configuring corresponding registers
The access time of bus.
Control FPGA and need to realize AHB from apparatus logic, use the mode of state machine to realize in the design.Such as Fig. 5
Shown ahb bus, from equipment state machine, has three state idle states, write state, read state.
Idle state: default conditions, if triggering signal nGCS5, nWe or nOE in this state to meet (nGCS5and
(nWe or nOE)) jump to NextState equal to zero, otherwise stay this state to continue waiting for triggering signal, the behaviour of this state
Make tetra-signal demands of nXBREQ, nXBACK, nWAIT, DATA and set high resistance state.
Writ state: nGCS5 jumps to this state equal to 0 and nWe equal to 0, and this state is ahb bus write operation, on
Position machine writes data into from equipment, and tri-signals of operation nXBREQ, nXBACK, nWAIT at this equipment set high resistance state, will
Data write FPGA internal register on data/address bus.
Read state: nGCS5 jumps to this state equal to 0 and nOE equal to 0, and this state is ahb bus read operation, should
Operate and initiated to place data into data/address bus from equipment response by host computer.
As shown in table 2 upstream device address is distributed, ahb bus drives has applied for that the address space of 2M is as downstream chip
Working place, ahb bus is connected with controlling FPGA, then by ground by the way of controlling FPGA internal logic and using direct addressing
Location be distributed into 3 sections be respectively supplied to control FPGA itself, experiment FPGA, SRAM use, wherein address realm: 0x000000～
0x03ffff, size be 256K bit wide be 32bits distribute to control FPGA, use as internal register space；Address realm
For 0x080000～0x0800ff, size be 256 bit wides be that 32bits distributes to test FPGA, as the communication of experiment FPGA
Interface；Address realm is: 0x100000～0x1fffff, size be 1M bit wide be 32 distribute to SRAM use, as CPU visit
Ask the interface of SRAM.
Table 2
The embodiment of the present invention also provides for the exchange at a high speed of the experimental technique of a kind of experimental system, i.e. experimental data and controls association
View, the method includes:
In a step 101, experimental provision sends, to server, the reality that new equipment application request, i.e. server find to be newly added
After experiment device, the experimental provision being newly added can send new equipment application request to server, and server reads after receiving this request
Experimental provision is also joined in heart beating list by the information of experimental provision, starts heartbeat timer simultaneously.
In a step 102, after new experimental provision adds server, server sends initialization information to experimental provision, should
Information includes system firmware and configuration information.
In step 103, after experimental provision adds server, timing sends heartbeat packet to server, and server receives heart beating
Heartbeat timer is reset and starts new timing, if the heartbeat packet timer of server is the most overtime, server meeting by Bao Houhui
Assert this experimental provision off-line, delete this experimental provision information.
At step 104, server sends experiment order and experimental data to experimental provision, and student sends at server end
Corresponding experiment order is to experimental provision, and the experimental data that student finishes writing in advance gives experimental provision for students ' analysis.
In step 105, the experimental data of server timing acquiring experimental provision, by server analysis and on experiment circle
Show on face.
In step 106, notifying server during experimental provision off-line, server can preserve experiment information and then delete this reality
Experiment device information.
The high-speed data that the experimental provision of present invention offer and experimental system are capable of between server and experimental facilities
Exchange and management, employ high speed system bus and downstream experimental facilities communication, coordinates 100M network interface to make data transmission bauds
It is greatly improved.Experimental provision hardware configuration include embedded solution (arm9 processor, internal memory, nandflash,
Serial ports, USB, wifi, network interface, touch screen), control FPGA, experiment FPGA, experiment network interface and be used for supporting all kinds of realities of experiment
Test interface.Present invention also offers server experimental data based on the exploitation of hardware above basic engineering exchange at a high speed and control association
View, high speed system bus drive, control FPGA bridging logic and dual network structure.
While it is disclosed that embodiment as above, but described content is only to facilitate understand the present invention and adopt
Embodiment, be not limited to the present invention.Technical staff in any the technical field of the invention, without departing from this
On the premise of spirit and scope disclosed in invention, in form and any amendment and change can be made in details implement,
But the scope of patent protection of the present invention, still must be defined in the range of standard with appending claims.
Claims (7)
1. an experimental provision, it is characterised in that including:
Experimental considerations unit, it is used for writing experimental code and tests, and carries out the network number of generation in experimentation with server
According to communication；
Communication unit, it gives described experimental considerations unit for the experiment control Data Concurrent issued receiving server, it is achieved clothes
Business device is for the control of experimental considerations unit, and carries out the transmission of experimental data between server and described test unit.
2. experimental provision as claimed in claim 1, it is characterised in that be provided with high speed network interface in described communication unit, described
Communication unit carries out described experiment control data and the transmission of experimental data by described high speed network interface and server.
3. experimental provision as claimed in claim 1, it is characterised in that be provided with experiment network interface in described experimental considerations unit, described
Experimental considerations unit carries out the communication of the network data produced in experimentation by described experiment network interface and described server.
4. experimental provision as claimed in claim 1, it is characterised in that described experimental considerations unit and described communication unit are by a high speed
Bus carries out described experiment control data and the transmission of experimental data.
5. experimental system as claimed in claim 1, it is characterised in that described communication unit and described experimental considerations unit pass through netting twine
Interface or back panel connector are connected with server.
6. an experimental system, it is characterised in that including:
Multiple experimental provisions as described in any one of claim 1 to 5；
Server；
Described communication unit and server carry out the communication of experiment control data and experimental data, constitute and control network, described reality
Verification certificate unit and server carry out the communication of the network data produced in experimentation, constitute Experimental Network.
7. experimental system as claimed in claim 5, it is characterised in that described control network is by described in described server monitoring
Experimental Network, and in described Experimental Network, send data and/or from described Experimental Network, gather data.
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Application publication date: 20170104 |