CN106252400A - A kind of thick film SOI LIGBT device and the raising method of latch-up immunity thereof - Google Patents
A kind of thick film SOI LIGBT device and the raising method of latch-up immunity thereof Download PDFInfo
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- CN106252400A CN106252400A CN201610835934.6A CN201610835934A CN106252400A CN 106252400 A CN106252400 A CN 106252400A CN 201610835934 A CN201610835934 A CN 201610835934A CN 106252400 A CN106252400 A CN 106252400A
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 230000036039 immunity Effects 0.000 title claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 55
- 238000002955 isolation Methods 0.000 claims abstract description 48
- 229920005591 polysilicon Polymers 0.000 claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000002161 passivation Methods 0.000 claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 230000005611 electricity Effects 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- -1 phosphonium ion Chemical class 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
nullA kind of thick film SOI LIGBT device and the raising method of latch-up immunity thereof，Including P type substrate，P type substrate is provided with one layer and buries oxide layer，N-type drift region is had burying oxide layer，The inside of N-type drift region is provided with PXing Ti district and N-type relief area，It is provided with p-type negative contact zone and N-shaped negative contact zone at p-type body surface，Contact area is connected with cathode contacts metal level，It is provided with p type anode contact area on the surface of N-type relief area，Contact area is connected with positive contact metal level，There are field oxide and conductive polysilicon gate in the surface of N-type drift region，In negative contact zone、Positive contact district、The surface of field oxide and conductive polysilicon gate is provided with passivation layer，It is characterized in that，Isolation channel it is provided with outside device cathodes，Conductive polycrystalline silicon and negative contact zone and cathode metal layer short circuit in isolation channel，Electric potential difference between conductive polycrystalline silicon and N-type drift region in the method increase isolation channel，Reduce and flow through the hole current of lateral channel in PXing Ti district，Achieve the raising of latch-up immunity.
Description
Technical field
The present invention relates to the reliability field of integrated circuit, be about a kind of thick film SOI-LIGBT device and anti-breech lock thereof
The method that ability improves.
Background technology
High power semiconductor device and integrated circuit have occupied about the 75% of international power semiconductor industry total value.I
State's independent research high-power component technology the most progressively internationalizes, simultaneously overheated, the overvoltage of device, electrostatic defending (Electronic
Static Discharge protection, ESD), the integrity problem such as anti-breech lock the most especially prominent.Wherein imitate due to breech lock
Should cause cross flow problem make insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT),
Silicon-on-insulator lateral insulated gate bipolar transistor (Silicon-On-Insulated-Lateral Insulated Gate
Bipolar Transistor, SOI-LIGBT), silicon controlled rectifier (SCR) (Semiconductor Control Rectifier,
Etc. SCR) device reliability when circuit works is greatly reduced.For SOI-LIGBT device in actual push-pull circuit, power
Device once enters latch mode, will directly form low impedance path between power supply and the ground of push-pull circuit, will between power supply and ground
Flow through big electric current and make power device or even whole circuit burnout.Therefore the breech lock that must study SOI-LIGBT device in detail is special
Property to improve device and the reliability of circuit thereof.
At present for SOI-LIGBT device, latch-up is mainly derived from device architecture the NPN crystal of parasitism
Pipe.According to the working mechanism of SOI-LIGBT, device architecture exists by negative electrode N-type contact area, PXing Ti district and N-type drift region group
The parasitic NPN transistor become.When device works, there are two strands of electric currents in structure, one derives from the cathode system electricity to anode
Electron current, another strand derives from the hole current launched by anode.Wherein hole current is sent by anode and flows through N-type relief area, N
Type drift region and PXing Ti district, finally collected by negative electrode p-type contact area；Horizontal stroke in PXing Ti district can be flowed through when hole current is excessive
Reaching 0.7V to the pressure drop of channel region, at this moment parasitic NPN transistor is opened, now parasitic NPN transistor meeting and colelctor electrode
The PNP transistor at place mutually provides base current, so that device cannot turn off, ultimately forms latch phenomenon.The present invention is directed to
This situation, it is proposed that a kind of device latch-up immunity promotes new method.
Summary of the invention
The present invention is on the basis of original device architecture, it is provided that a kind of thick film SOI-LIGBT device and anti-door bolt thereof
The raising method of lock ability, and latch-up immunity has and significantly improves.
The present invention adopts the following technical scheme that
A kind of thick film SOI-LIGBT device, including P type substrate, is provided with one layer in P type substrate and buries oxide layer, burying oxygen
Changing and have N-type drift region above layer, the inside of N-type drift region is provided with PXing Ti district and N-type relief area, is provided with P at p-type body surface
Type negative contact zone and N-shaped negative contact zone, p-type negative contact zone is connected with cathode contacts metal level with N-shaped negative contact zone,
Be provided with p type anode contact area on the surface of N-type relief area, p type anode contact area is connected with positive contact metal level, and N-type is drifted about
There are field oxide and conductive polysilicon gate in the surface in district, field oxide between N-shaped negative contact zone and p-type contact area,
Conductive polysilicon gate extends to field oxide upper surface by border, N-shaped negative contact zone, at p-type negative contact zone, N-shaped
The surface of negative contact zone, p type anode contact area, field oxide and conductive polysilicon gate is provided with passivation layer, outside device cathodes
Side is provided with isolation channel, and described isolation channel is made up of isolating oxide layer and the conductive polycrystalline silicon wrapped up by described isolating oxide layer, its
It is characterised by, the conductive polycrystalline silicon wrapped up by described isolating oxide layer and p-type negative contact zone, N-shaped negative contact zone and the moon
Pole metal level short circuit.
The raising method of the latch-up immunity of a kind of described thick film SOI-LIGBT device, described SOI-LIGBT device includes
P type substrate, is provided with one layer in P type substrate and buries oxide layer, has N-type drift region burying oxide layer, the inside of N-type drift region
It is provided with PXing Ti district and N-type relief area, is provided with p-type negative contact zone and N-shaped negative contact zone, p-type negative electrode at p-type body surface
Contact area is connected with cathode contacts metal level with N-shaped negative contact zone, is provided with p type anode contact area on the surface of N-type relief area,
P type anode contact area is connected with positive contact metal level, and there are field oxide and conductive polysilicon gate in the surface of N-type drift region,
Field oxide is between N-shaped negative contact zone and p-type contact area, and conductive polysilicon gate is opened by border, N-shaped negative contact zone
Begin extend to field oxide upper surface, in p-type negative contact zone, N-shaped negative contact zone, p type anode contact area, field oxide and
The surface of conductive polysilicon gate is provided with passivation layer, is provided with isolation channel outside device cathodes, and described isolation channel is by isolating oxide layer
Form with the conductive polycrystalline silicon wrapped up by described isolating oxide layer, it is characterised in that by leading of being wrapped up by described isolating oxide layer
Electricity polysilicon and p-type negative contact zone, N-shaped negative contact zone and cathode metal layer short circuit so that whole isolation channel have with
The current potential that negative electrode is identical, reduces the current potential within isolation channel, electromotive force between conductive polycrystalline silicon and N-type drift region in increase isolation channel
Difference, and utilize electric potential difference, reduce and flow through the hole current of lateral channel in PXing Ti district.
Compared with prior art, the invention of this time has the advantage that
(1) structure in the inventive method can effectively improve device latch-up immunity.The present invention uses isolation channel
In the form of conductive polycrystalline silicon 15 ground connection, the current potential that can avoid conductive polycrystalline silicon 15 in device isolation groove is dry by the external world
Disturb, keep a constant electronegative potential, thus conductive polysilicon electrode 15 and N-type drift region 3 in effectively increasing device
Voltage difference, as shown in Figure 6, Fig. 6 comparison diagram 5, conductive polysilicon electrode 15 and N-type drift region 3 electric potential difference increase close to twice,
-44V is increased to, due to the effect of this bigger electric potential difference in new construction so that in device, must have more sky by-24.2V
Cave electric current flows along ditch non-intercommunicating cells lateral wall.Highlight regions as shown in Fig. 6 16, on the premise of hole current total amount is constant, subtracts
Little flowed through the hole current of position 17 in PXing Ti district 4 by N-type drift region 3, thus reduce dead resistance at position 17
On pressure drop, reduce device produce breech lock probability, finally make the breech lock voltage of device bring up to 263V from 210V.
(2) in the present invention, in isolation channel, conductive polysilicon electrode 15 and negative electrode short circuit method do not change the breakdown voltage of device
With current capacity.Owing to the breakdown point of device architecture is positioned at below p-type contact area 6, but isolation channel will not change p-type contact area
Electric Field Distribution below 6, so conductive polysilicon electrode 15 ground connection can't produce shadow to the breakdown voltage of device in isolation channel
Ring.Additionally, the existence of the isolation moat structure in the inventive method passes through the partial holes electric current of position 17 in PXing Ti district 4
Flow into negative electrode along ditch non-intercommunicating cells lateral wall after changing original path, increase the hole current flowing through ditch non-intercommunicating cells lateral wall, reduce
Flow through the hole current of position 17 in PXing Ti district 4, highlight regions as shown in Fig. 6 16, but size of current total in device
Do not change.
(3) in the isolation channel in the present invention conductive polysilicon electrode 15 and negative electrode 9 short circuit method owing to need not new light
Cut blocks for printing, be also not related to new domain technique, so the process costs of manufacture can't be increased in the manufacture of device.
(4) its latch-up immunity when realizing in parallel of the structure in the inventive method is unaffected, adds parallel-connection structure
The stability of middle device.In high power device application, conventional parallel-connection structure forms racetrack many fingers device, passes as system device described in Fig. 2
Racetrack many fingers element layout that part structure composes in parallel, the racetrack composed in parallel for novel device architecture described in Fig. 4 is many
Refer to element layout.The parallel-connection structure of conventional device structure composition can be done by other devices outside and surrounding in the application
Disturb, Fig. 2 China and foreign countries on the one hand can be caused to enclose the potential fluctuation problem of the conductive polycrystalline silicon 15 in isolation channel 19；On the other hand can affect
Fig. 2 China and foreign countries enclose the current potential of conductive polycrystalline silicon 15 in isolation channel 19 and the conductive polycrystalline silicon 15 in the isolation channel 18 of inside configuration
Being uniformly distributed of current potential.But, the parallel-connection structure in Fig. 4 is due to the conductive polycrystalline silicon 15 in isolation channel and negative electrode short circuit, permissible
Make conductive polycrystalline silicon in all devices in parallel 15 keep stable with the electric potential difference of device inside N-type drift region 3, finally avoid by
The problem that device property floats in the parallel-connection structure that external interference causes, enhances the stability of device in parallel-connection structure.
Accompanying drawing explanation
Fig. 1 is the two dimensional cross-section structure of traditional thick film SOI-LIGBT device.
The domain of racetrack many fingers device that the thick film SOI-LIGBT device architecture that Fig. 2 is traditional composes in parallel, in domain
In isolation channel near negative electrode conductive polycrystalline silicon not with negative electrode short circuit.
Fig. 3 is the two dimensional cross-section knot of the novel thick film SOI-LIGBT device of conductive polycrystalline silicon and negative electrode short circuit in isolation channel
Structure.
The domain of racetrack many fingers device that the thick film SOI-LIGBT device architecture that Fig. 4 is novel composes in parallel, at domain
The conductive polycrystalline silicon in isolation channel near interior device cathodes and negative electrode short circuit.
When Fig. 5 is that in isolation channel, conductive polycrystalline silicon is not with negative electrode short circuit, being 10V in grid voltage, anode voltage is 200V situation
Under the hole current distributed simulation figure of thick film SOI-LIGBT device.
Fig. 6 be in isolation channel conductive polycrystalline silicon be connected with negative electrode ground connection time, be 10V in grid voltage, anode voltage is 200V feelings
The hole current distributed simulation figure of the thick film SOI-LIGBT device under condition.
Fig. 7 is traditional thick film SOI-LIGBT device and novel thick film SOI-LIGBT device breech lock voltage tester result pair
Ratio.
Detailed description of the invention
Embodiment 1
A kind of thick film SOI-LIGBT device, including P type substrate 1, is provided with one layer in P type substrate 1 and buries oxide layer 2, burying
N-type drift region 3, the inside of N-type drift region 3 is had to be provided with PXing Ti district 4 and N-type relief area 14, in PXing Ti district 4 above oxide layer 2
Surface is provided with p-type negative contact zone 6 and N-shaped negative contact zone 7, p-type negative contact zone 6 and N-shaped negative contact zone 7 and connects with negative electrode
Touching metal level 9 to be connected, be provided with p type anode contact area 13 on the surface of N-type relief area 14, p type anode contact area 13 connects with anode
Touching metal level 12 to be connected, there are field oxide 11 and conductive polysilicon gate 10 in the surface of N-type drift region 3, and field oxide 11 is between n
Between type negative contact zone 7 and p-type contact area 13, conductive polysilicon gate 10 extends to by border, N-shaped negative contact zone 7
Field oxide 11 upper surface, in p-type negative contact zone 6, N-shaped negative contact zone 7, p type anode contact area 13, field oxide 11 and
The surface of conductive polysilicon gate 10 is provided with passivation layer 8, is provided with isolation channel outside device cathodes, and described isolation channel is by isolation oxidation
Layer 5 and the conductive polycrystalline silicon 15 wrapped up by described isolating oxide layer 5 form, it is characterised in that wrapped up by described isolating oxide layer 5
Conductive polycrystalline silicon 15 and p-type negative contact zone 6, N-shaped negative contact zone 7 and cathode metal layer 9 short circuit.
Embodiment 2
The raising method of the latch-up immunity of a kind of described thick film SOI-LIGBT device, described SOI-LIGBT device includes
P type substrate 1, is provided with one layer in P type substrate 1 and buries oxide layer 2, has N-type drift region 3 burying, N-type drift region 3 above oxide layer 2
Inside be provided with PXing Ti district 4 and N-type relief area 14, be provided with p-type negative contact zone 6 and N-shaped cathode contacts on surface, PXing Ti district 4
District 7, p-type negative contact zone 6 is connected with cathode contacts metal level 9 with N-shaped negative contact zone 7, sets on the surface of N-type relief area 14
Having p type anode contact area 13, p type anode contact area 13 to be connected with positive contact metal level 12, there is field on the surface of N-type drift region 3
Oxide layer 11 and conductive polysilicon gate 10, field oxide 11, between N-shaped negative contact zone 7 and p-type contact area 13, conducts electricity
Polysilicon gate 10 extends to field oxide 11 upper surface by border, N-shaped negative contact zone 7, at p-type negative contact zone 6, n
The surface of type negative contact zone 7, p type anode contact area 13, field oxide 11 and conductive polysilicon gate 10 is provided with passivation layer 8,
Being provided with isolation channel outside device cathodes, described isolation channel is many by isolating oxide layer 5 and the conduction wrapped up by described isolating oxide layer 5
Crystal silicon 15 forms, it is characterised in that conductive polycrystalline silicon 15 and p-type negative contact zone 6, the n that will be wrapped up by described isolating oxide layer 5
Type negative contact zone 7 and cathode metal layer 9 short circuit so that whole isolation channel has the current potential identical with negative electrode, reduce isolation
Current potential within groove, electric potential difference between conductive polycrystalline silicon 15 and N-type drift region 3 in increase isolation channel, and utilize electric potential difference, reduce
Flow through the hole current of lateral channel in PXing Ti district 4.
For our thick film SOI technique, soi layer thickness is 18 μm, in order to realize the isolation between device, and the three of device
The isolation channel thickness of Mingzhi also should reach 18 μm, and the width of isolation channel should have about 2 μm.
The present invention adopts and prepares with the following method:
First being that soi layer makes, wherein drift region 3 uses to inject phosphonium ion and carry out high annealing and forms N-type drift region
3.For SiO2The isolation channel of the high-aspect-ratio that oxide layer 5 is formed with conductive polycrystalline silicon 15, first carries out sidewall oxidation again with leading
Electricity polysilicon is filled.Ensuing is the making of lateral isolation bipolar transistor, is included in N-type drift region 3 by injecting
Phosphonium ion forms N-type cushion 14, injects boron ion and forms PXing Ti district 4, followed by field oxide 11, and deposit conduction afterwards is many
Crystal silicon 10, etching forms grid, then makes p type anode contact area 13, N-shaped negative contact zone 7, p-type negative contact zone 6.And then
Depositing silicon dioxide passivation layer 8 at overall structure upper surface, etching deposits metal behind electrode contact district, then etches metal and draw
Electrode, is finally passivated processing.
Claims (4)
1. a thick film SOI-LIGBT device, including P type substrate (1), is provided with one layer in P type substrate (1) and buries oxide layer (2),
N-type drift region (3), the inside of N-type drift region (3) is had to be provided with PXing Ti district (4) and N-type relief area burying oxide layer (2) top
(14), p-type negative contact zone (6) and N-shaped negative contact zone (7), p-type negative contact zone (6) it are provided with on PXing Ti district (4) surface
It is connected with cathode contacts metal level (9) with N-shaped negative contact zone (7), is provided with p type anode on the surface of N-type relief area (14) and connects
Touching district (13), p type anode contact area (13) are connected with positive contact metal level (12), and the surface of N-type drift region (3) has field to aoxidize
Layer (11) and conductive polysilicon gate (10), field oxide (11) between N-shaped negative contact zone (7) and p-type contact area (13) it
Between, conductive polysilicon gate (10) extends to field oxide (11) upper surface by N-shaped negative contact zone (7) border, in p-type
Negative contact zone (6), N-shaped negative contact zone (7), p type anode contact area (13), field oxide (11) and conductive polysilicon gate
(10) surface is provided with passivation layer (8), is provided with isolation channel outside device cathodes, and described isolation channel is by isolating oxide layer (5) and quilt
Conductive polycrystalline silicon (15) composition that described isolating oxide layer (5) wraps up, it is characterised in that wrapped up by described isolating oxide layer (5)
Conductive polycrystalline silicon (15) and p-type negative contact zone (6), N-shaped negative contact zone (7) and cathode metal layer (9) short circuit.
Thick film SOI-LIGBT device the most according to claim 1, it is characterised in that the described conduction in isolation channel is many
Crystal silicon (15) and p-type contact area (6) optimum distance between the two are 5 μm-10 μm.
Thick film SOI-LIGBT device the most according to claim 1, it is characterised in that the described conduction in isolation channel is many
The doping content of crystal silicon (15) is at 1E19cm-3～1E22cm-3In the range of.
4. a raising method for the latch-up immunity of thick film SOI-LIGBT device, described SOI-LIGBT described in claim 1
Device includes P type substrate (1), is provided with one layer and buries oxide layer (2) in P type substrate (1), has N-type to float burying oxide layer (2) top
Moving district (3), the inside of N-type drift region (3) is provided with PXing Ti district (4) and N-type relief area (14), is provided with P on PXing Ti district (4) surface
Type negative contact zone (6) and N-shaped negative contact zone (7), p-type negative contact zone (6) and N-shaped negative contact zone (7) connect with negative electrode
Touch metal level (9) to be connected, be provided with p type anode contact area (13), p type anode contact area (13) on the surface of N-type relief area (14)
Being connected with positive contact metal level (12), there are field oxide (11) and conductive polysilicon gate in the surface of N-type drift region (3)
(10), field oxide (11) between N-shaped negative contact zone (7) and p-type contact area (13), conductive polysilicon gate (10) by
N-shaped negative contact zone (7) border starts to extend to field oxide (11) upper surface, connects at p-type negative contact zone (6), N-shaped negative electrode
The surface touching district (7), p type anode contact area (13), field oxide (11) and conductive polysilicon gate (10) is provided with passivation layer
(8), being provided with isolation channel outside device cathodes, described isolation channel wraps up by isolating oxide layer (5) with by described isolating oxide layer (5)
Conductive polycrystalline silicon (15) composition, it is characterised in that the conductive polycrystalline silicon (15) that will be wrapped up by described isolating oxide layer (5) and P
Type negative contact zone (6), N-shaped negative contact zone (7) and cathode metal layer (9) short circuit so that whole isolation channel has with cloudy
The most identical current potential, reduces current potential isolation channel within, increase in isolation channel conductive polycrystalline silicon (15) and N-type drift region (3) it
Between electric potential difference, and utilize electric potential difference, reduce and flow through the hole current of lateral channel in PXing Ti district (4).
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107256885A (en) * | 2017-06-30 | 2017-10-17 | 北京工业大学 | A kind of high stability insulation grid bipolar transistor and preparation method thereof |
| CN111223855A (en) * | 2019-11-19 | 2020-06-02 | 江南大学 | Method for improving ESD protection performance of circuit system by using gate isolation technology |
| CN111261722A (en) * | 2020-01-21 | 2020-06-09 | 东南大学 | Low reverse recovery charge lateral diode of integrated capacitor |
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| CN103762230A (en) * | 2014-01-24 | 2014-04-30 | 东南大学 | N-channel injection efficiency reinforced insulated gate bipolar transistor |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107256885A (en) * | 2017-06-30 | 2017-10-17 | 北京工业大学 | A kind of high stability insulation grid bipolar transistor and preparation method thereof |
| CN107256885B (en) * | 2017-06-30 | 2022-08-26 | 北京工业大学 | High-reliability insulated gate bipolar transistor and manufacturing method thereof |
| CN111223855A (en) * | 2019-11-19 | 2020-06-02 | 江南大学 | Method for improving ESD protection performance of circuit system by using gate isolation technology |
| CN111261722A (en) * | 2020-01-21 | 2020-06-09 | 东南大学 | Low reverse recovery charge lateral diode of integrated capacitor |
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| CN106252400B (en) | 2019-06-18 |
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