CN105633140B - A kind of dual layer section SOI LIGBT devices and its manufacturing method - Google Patents
A kind of dual layer section SOI LIGBT devices and its manufacturing method Download PDFInfo
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Abstract
The invention discloses a kind of dual layer section SOI LIGBT devices, including silicon substrate, the first oxygen buried layer and N buried layers are from left to right equipped on silicon substrate successively, the upper surface of N buried layers is higher than the upper surface of the first oxygen buried layer, first oxygen buried layer is equipped with P buried layers, N buried layers are equipped with the second oxygen buried layer, and the upper surface of the upper surface of P buried layers and the second oxygen buried layer is equipped with N-type drift region in sustained height, P buried layers and the second oxygen buried layer；The invention also discloses a kind of manufacturing methods of dual layer section SOI LIGBT devices, and the oxide layer of conventional SOI LIGBT is divided into two layers, and is isolated between interlayer using reversed PN junction.On the one hand the structure of this novel staged isolation in the case where ensureing the good isolation substrate leakage current of device, improves heat-sinking capability, reduces operating temperature, while also improve breakdown voltage.
Description
Technical field
The present invention relates to electronic technology field, particularly a kind of dual layer section SOI LIGBT devices and its manufacturing method.
Background technology
Lateral insulated gate bipolar transistor LIGBT (Lateral Insulator Gate Bipolar Transistor)
It is the compound power device that mos gate device architecture is combined with bipolar transistor structure, there is high input impedance and low
The characteristics of conduction voltage drop.With LDMOS unlike LIGBT be a kind of bipolar device, not only there are electronic current, anode in when conducting
P+ can inject hole to drift region and generate electronic current, and partial holes will continue to note to substrate in the case of no separation layer
Enter, cause considerable leakage current.Therefore there are two kinds of substrate isolation methods, one kind is that reversed PN junction adds water conservancy diversion knot
The shortcomings that structure, this structure is that heavy doping is needed therefore to greatly reduce breakdown voltage.One kind is SOI isolation, and this mode is
With the direct isolation liner bottom of oxide layer and drift region, can very effective reduction leakage current, but because only that drift region pressure-bearing
Breakdown voltage is equally also reduced, simultaneously as the capacity of heat transmission of oxide layer is very poor, self-heating effect can be caused.
Invention content
The technical problems to be solved by the invention are overcome the deficiencies in the prior art and provide a kind of dual layer section SOI
Oxygen buried layer is divided into two sections in the present invention by LIGBT devices and its manufacturing method, and heat is conducting to lining when being conducive to work
Bottom, so as to reduce self-heating effect, silicon substrate participates in pressure-bearing, therefore breakdown voltage can greatly promote.
The present invention uses following technical scheme to solve above-mentioned technical problem：
According to a kind of dual layer section SOI LIGBT devices proposed by the present invention, including silicon substrate, on silicon substrate from left to right
It is equipped with the first oxygen buried layer and N buried layers successively, the upper surface of N buried layers is higher than the upper surface of the first oxygen buried layer, is set on the first oxygen buried layer
There are a P buried layers, N buried layers are equipped with the second oxygen buried layer, and in sustained height, P is buried for the upper surface of the upper surface of P buried layers and the second oxygen buried layer
Layer and the second oxygen buried layer are equipped with N-type drift region；
Left side in N-type drift region is equipped with P bodies area, and cathode heavy doping P+ areas, cathode are from left to right equipped with successively in P bodies area
Heavy doping N+ areas, the right side in N-type drift region are equipped with anode P+ areas, N buffering areas and anode heavy doping N+ areas are lightly doped, be lightly doped
N buffering areas are located at the lower section in anode P+ areas, anode heavy doping N+ areas be located at anode P+ areas and the right side that N buffering areas are lightly doped and with
The right contact of second oxygen buried layer；
The upper surface in cathode heavy doping P+ areas and the portion of upper surface in cathode heavy doping N+ areas are equipped with cathode, cathode heavy doping
Portion of upper surface, the upper surface in P bodies area and the upper surface part subregion of N-type drift region in N+ areas are across equipped with grid, anode P+
The upper surface part subregion in area is equipped with anode, and oxide layer is equipped between grid and cathode, and the lower surface of grid also is provided with oxide layer,
Oxide layer is equipped between grid and anode.
Scheme, the N-type drift are advanced optimized as a kind of dual layer section SOI LIGBT devices of the present invention
Area, cathode heavy doping N+ areas, N buffering areas, N buried layers and anode heavy doping N+ areas is lightly doped is N-type；Silicon substrate, P bodies area, the moon
Pole heavy doping P+ areas, anode P+ areas and P buried layers are p-type.
Scheme is advanced optimized as a kind of dual layer section SOI LIGBT devices of the present invention, the silicon substrate is
SOI silicon substrates.
Based on a kind of manufacturing method of dual layer section SOI LIGBT devices, include the following steps：
Step 1: provide silicon substrate；
Step 2: being from left to right equipped with the first oxygen buried layer and N buried layers successively on a silicon substrate, the upper surface of N buried layers is higher than
The upper surface of first oxygen buried layer, the first oxygen buried layer are equipped with P buried layers, and N buried layers are equipped with the second oxygen buried layer, the upper surface of P buried layers
With the upper surface of the second oxygen buried layer in sustained height, P doping is carried out in P buried layers area, N doping is carried out in N buried layers area；
Step 3: N-type drift region is equipped on P buried layers and the second oxygen buried layer；
Step 4: the left side in N-type drift region is equipped with P bodies area, it is from left to right equipped with cathode heavy doping successively in P bodies area
P+ areas, cathode heavy doping N+ areas, the right side in N-type drift region are equipped with anode P+ areas, N buffering areas and anode heavy doping N+ are lightly doped
Area, is lightly doped the lower section that N buffering areas are located at anode P+ areas, and anode heavy doping N+ areas 15 are located at anode P+ areas and N bufferings are lightly doped
The right side in area and with the right contact of the second oxygen buried layer；
Step 5: the upper surface in cathode heavy doping P+ areas and the portion of upper surface in cathode heavy doping N+ areas are equipped with cathode, it is cloudy
The upper surface part subregion of the portion of upper surface in pole heavy doping N+ areas, the upper surface in P bodies area and N-type drift region is across equipped with grid
Pole, the upper surface part subregion in anode P+ areas are equipped with anode, oxide layer are equipped between grid and cathode, the lower surface of grid is also set
There is oxide layer, oxide layer is equipped between grid and anode.
Scheme is advanced optimized as a kind of manufacturing method of dual layer section SOI LIGBT devices of the present invention, institute
State a concentration of the 1 × 10 of N buried layers area and P buried layers area15cm-3, a concentration of the 1 × 10 of N-type drift region15cm-3, N buffering areas are lightly doped
A concentration of 3 × 1017cm-3, a concentration of the 1 × 10 of P bodies area17cm-3, cathode heavy doping N+ areas, cathode heavy doping P+ areas, anode
A concentration of the 1 × 10 of P+ areas21cm-3, a concentration of the 5 × 10 of anode heavy doping N+ areas20cm-3。
The present invention compared with prior art, has following technique effect using above technical scheme：
（1）Oxygen buried layer is divided into two sections in the present invention, heat is conducting to substrate when being conducive to work, so as to reduce from
Fuel factor；
（2）Silicon substrate participates in pressure-bearing, therefore breakdown voltage can greatly promote.
Description of the drawings
Fig. 1 is common LIGBT diagrammatic cross-sections.
Fig. 2 is the diagrammatic cross-section of common SOILIGBT devices.
Fig. 3 is the diagrammatic cross-section of dual layer section SOI LIGBT devices.
Reference numeral in figure is construed to：1- silicon substrates, the first oxygen buried layers of 2-, 17-N buried layers, 3-P buried layers, 17-N buried layers,
The second oxygen buried layers of 16-, 4-N types drift region, 5-P bodies area, 6- cathode heavy doping P+ areas, 7- cathode heavy doping N+ areas, 13- anodes P+
N buffering areas, 15- anode heavy doping N+ areas, 8- cathodes, 9- grids, 12- anodes, 11- oxide layers, 10- ditches is lightly doped in area, 14-
Road.
Specific embodiment
Technical scheme of the present invention is described in further detail below in conjunction with the accompanying drawings：
As shown in Figure 1, common LIGBT device architectures, there is no reply substrate leakage currents between working region and substrate
Isolation structure, therefore a large amount of holes are directly injected into substrate in working condition, and device performance is caused to seriously affect.
As shown in figure 3, a kind of dual layer section SOI LIGBT devices, including silicon substrate 1, on silicon substrate from left to right successively
Equipped with the first oxygen buried layer 2 and N buried layers 17, the upper surface of N buried layers 17 is higher than the upper surface of the first oxygen buried layer 2, on the first oxygen buried layer
Equipped with P buried layers 3, N buried layers 17 are equipped with the second oxygen buried layer 16, and the upper surface of the upper surface of P buried layers 3 and the second oxygen buried layer 16 is same
One height, 3 and second oxygen buried layer 16 of P buried layers are equipped with N-type drift region 4；
Left side in N-type drift region 4 is equipped with P bodies area 5, be from left to right equipped with successively in P bodies area 5 cathode heavy doping P+ areas 6,
Cathode heavy doping N+ areas 7, the right side in N-type drift region are equipped with anode P+ areas 13, N buffering areas 14 and anode heavy doping N+ are lightly doped
Area 15, is lightly doped the lower section that N buffering areas 14 are located at anode P+ areas 13, and anode heavy doping N+ areas 15 are located at anode P+ areas 13 and gently mix
The right side of miscellaneous N buffering areas 14 and with the right contact of the second oxygen buried layer 16；The upper end in P bodies area 5 is raceway groove 10；
The upper surface in cathode heavy doping P+ areas 6 and the portion of upper surface in cathode heavy doping N+ areas 7 are equipped with cathode, and cathode is heavily doped
Portion of upper surface, the upper surface in P bodies area and the upper surface part subregion of N-type drift region 4 in miscellaneous N+ areas 7 are across equipped with grid, sun
The upper surface part subregion in pole P+ areas 13 is equipped with anode, oxide layer is equipped between grid and cathode, the lower surface of grid also is provided with
Oxide layer is equipped with oxide layer between grid and anode.
The N-type drift region, cathode heavy doping N+ areas, N buffering areas, N buried layers and anode heavy doping N+ areas is lightly doped is N
Type；Silicon substrate, P bodies area, cathode heavy doping P+ areas, anode P+ areas and P buried layers are p-type.The silicon substrate is SOI silicon substrates.
Compared with common SOI LIGBT, innovation of the present invention is the change of oxygen buried layer, in common soi structure,
As shown in Fig. 2, only one layer of oxygen buried layer being completely covered.Oxygen buried layer is divided into two sections and uses weight in anode by structure of the present invention
N areas are adulterated hole to be prevented to inject substrate, hole are prevented to inject substrate using reversed PN junction interrupting.
The advantage of the inventive structure is embodied in when LIGBT works, and due to the device oxygen buried layer, there is no completely isolated drifts
Area and substrate are moved, therefore the heat generated that works can be distributed by body silicon, reduce self-heating effect, another aspect substrate is held
Pressure, improves breakdown voltage.
Based on dual layer section SOILIGBT devices, manufacturing method includes the following steps：
1st step, one oxygen buried layer 2 of growth regulation on silicon substrate 1；
2nd step, on a silicon substrate extension P buried layers and N buried layers；
3rd step carries out P doping in P buried layers；
4th step carries out N doping in N buried layers；
5th step, the second oxygen buried layer of regrowth on buried layer；
6th step, the extension N drift regions on silicon chip；
7th step, in N drift regions, N buffering areas are lightly doped in injection；
8th step is injected in N drift regions and P bodies area is lightly doped；
9th step injects cathode heavy doping N+ areas in P bodies area, in anode tap injection anode heavy doping N+ areas；
10th step injects cathode heavy doping P+ areas in P bodies area, and anode heavy doping P+ areas are injected in N buffering areas；
11st step grows oxide layer on surface；
12nd step manufactures electrode cathode, grid, anode on surface.
Described 3rd, in 4 steps, N buried layers and P buried layers a concentration of 1 × 1015cm-3, in the 6th step, N drift regions a concentration of 1
×1015cm-3, the described 7th, in 8 steps, N buffering areas a concentration of 3 × 1017cm-3, P bodies area a concentration of 1 × 1017cm-3, described
9th, in 10 steps, cathode heavy doping N+ areas, cathode heavy doping P+ areas, anode heavy doping P+ areas a concentration of 1 × 1021cm-3, anode weight
Adulterate N+ areas a concentration of 5 × 1020cm-3。
This structure reduces self-heating effect compared with conventional SOI LIGBT, improves breakdown voltage.
Structure, step, numerical value in above-described embodiment etc. are signal, under the premise of inventive concept is not violated, this
The those skilled in the art in field can be replaced on an equal basis, can also make several modifications and improvements, these belong to the present invention
Protection domain.
Claims (4)
1. a kind of dual layer section SOI LIGBT devices, which is characterized in that including silicon substrate, from left to right set successively on silicon substrate
There are the first oxygen buried layer and N buried layers, the upper surface of N buried layers is higher than the upper surface of the first oxygen buried layer, and the first oxygen buried layer is buried equipped with P
Layer, N buried layers are equipped with the second oxygen buried layer, the upper surface of the upper surface of P buried layers and the second oxygen buried layer in sustained height, P buried layers and
Second oxygen buried layer is equipped with N-type drift region；
Left side in N-type drift region is equipped with P bodies area, and it is heavily doped to be from left to right equipped with cathode heavy doping P+ areas, cathode in P bodies area successively
Miscellaneous N+ areas, the right side in N-type drift region are equipped with anode P+ areas, N buffering areas and anode heavy doping N+ areas are lightly doped, N is lightly doped and delays
Rush the lower section that area is located at anode P+ areas, anode heavy doping N+ areas are located at anode P+ areas and the right side that N buffering areas are lightly doped and with
The right contact of two oxygen buried layers；
The upper surface in cathode heavy doping P+ areas and the portion of upper surface in cathode heavy doping N+ areas are equipped with cathode, cathode heavy doping N+ areas
Portion of upper surface, the upper surface in P bodies area and the upper surface part subregion of N-type drift region across equipped with grid, anode P+ areas
Upper surface part subregion is equipped with anode, oxide layer is equipped between grid and cathode, the lower surface of grid also is provided with oxide layer, grid
Oxide layer is equipped between anode；
The N buried layers are the buried layer of N-type conduction type, and P buried layers are the buried layer of P-type conduction type, and P bodies area is P-type conduction type
Body area, be lightly doped N buffering areas be N-type conduction type the buffering area being lightly doped.
2. a kind of dual layer section SOI LIGBT devices according to claim 1, which is characterized in that the silicon substrate is portion
Divide SOI silicon substrates.
3. based on a kind of manufacturing method of dual layer section SOI LIGBT devices described in claim 1, include the following steps：
Step 1: provide silicon substrate；
Step 2: being from left to right equipped with the first oxygen buried layer and N buried layers successively on a silicon substrate, the upper surface of N buried layers is higher than first
The upper surface of oxygen buried layer, the first oxygen buried layer are equipped with P buried layers, and N buried layers are equipped with the second oxygen buried layer, the upper surface of P buried layers and the
The upper surface of two oxygen buried layers carries out P doping in sustained height, in P buried layers area, and N doping is carried out in N buried layers area；
Step 3: N-type drift region is equipped on P buried layers and the second oxygen buried layer；
Step 4: the left side in N-type drift region is equipped with P bodies area, it is from left to right equipped with cathode heavy doping P+ successively in P bodies area
Area, cathode heavy doping N+ areas, the right side in N-type drift region are equipped with anode P+ areas, N buffering areas and anode heavy doping N+ are lightly doped
Area, is lightly doped the lower section that N buffering areas are located at anode P+ areas, and anode heavy doping N+ areas 15 are located at anode P+ areas and N bufferings are lightly doped
The right side in area and with the right contact of the second oxygen buried layer；
Step 5: the upper surface in cathode heavy doping P+ areas and the portion of upper surface in cathode heavy doping N+ areas are equipped with cathode, cathode weight
Portion of upper surface, the upper surface in P bodies area and the upper surface part subregion of N-type drift region in N+ areas are adulterated across equipped with grid, sun
The upper surface part subregion in pole P+ areas is equipped with anode, oxide layer is equipped between grid and cathode, the lower surface of grid also is provided with oxygen
Change layer, oxide layer is equipped between grid and anode.
A kind of 4. manufacturing method of dual layer section SOI LIGBT devices according to claim 3, which is characterized in that the N
Buried layer area and a concentration of the 1 × 10 of P buried layers area15cm-3, a concentration of the 1 × 10 of N-type drift region15cm-3, N buffering areas are lightly doped
A concentration of 3 × 1017cm-3, a concentration of the 1 × 10 of P bodies area17cm-3, cathode heavy doping N+ areas, cathode heavy doping P+ areas, anode P+
A concentration of the 1 × 10 of area21cm-3, a concentration of the 5 × 10 of anode heavy doping N+ areas20cm-3。
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| CN106684135B (en) * | 2017-01-10 | 2019-04-26 | 电子科技大学 | A kind of SOI-LIGBT of high reliability |
| CN110010678A (en) * | 2018-01-04 | 2019-07-12 | 中兴通讯股份有限公司 | Lateral insulated gate bipolar transistor and preparation method thereof |
| CN110047920B (en) * | 2019-04-16 | 2021-06-18 | 西安电子科技大学 | Transverse junction type gate bipolar transistor and manufacturing method thereof |
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| CN100474620C (en) * | 2004-04-21 | 2009-04-01 | 三菱电机株式会社 | Dielectric isolation type semiconductor device |
| CN104009089A (en) * | 2014-05-29 | 2014-08-27 | 西安电子科技大学 | PSOI lateral double-diffused metal oxide semiconductor field effect transistor |
| CN104769715A (en) * | 2012-07-31 | 2015-07-08 | 硅联纳半导体(美国)有限公司 | Power device integration on a common substrate |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP5055813B2 (en) * | 2006-04-10 | 2012-10-24 | 富士電機株式会社 | SOI lateral semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100474620C (en) * | 2004-04-21 | 2009-04-01 | 三菱电机株式会社 | Dielectric isolation type semiconductor device |
| CN104769715A (en) * | 2012-07-31 | 2015-07-08 | 硅联纳半导体(美国)有限公司 | Power device integration on a common substrate |
| CN104009089A (en) * | 2014-05-29 | 2014-08-27 | 西安电子科技大学 | PSOI lateral double-diffused metal oxide semiconductor field effect transistor |
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