CN106250340A - A kind of hardware control circuit and control method thereof - Google Patents
A kind of hardware control circuit and control method thereof Download PDFInfo
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- CN106250340A CN106250340A CN201610611589.8A CN201610611589A CN106250340A CN 106250340 A CN106250340 A CN 106250340A CN 201610611589 A CN201610611589 A CN 201610611589A CN 106250340 A CN106250340 A CN 106250340A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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Abstract
The present invention provides a kind of hardware control circuit and control method thereof, and this hardware control circuit includes: processor, CPLD, backboard, multiple veneer；Veneer includes that parallel serial conversion module, CPLD include serioparallel exchange module, coding/decoding module；Parallel serial conversion module, for obtaining the hardware information of veneer, and by the data signal line between veneer and backboard, is sent to backboard by hardware information in a serial fashion；Serioparallel exchange module, for by data signal line between backboard with CPLD, that veneer is corresponding, obtains hardware information in a serial fashion from backboard, and is stored in by hardware information in the data register that veneer is corresponding；Coding/decoding module, for obtaining the hardware information of veneer in the data register that veneer is corresponding, and exports the hardware information of veneer to described processor.By technical scheme, decrease the holding wire quantity between backboard and veneer, decrease the holding wire quantity between backboard and CPLD, save mainboard and the PCB layout space of backboard.
Description
Technical field
The present invention relates to communication technical field, particularly relate to a kind of hardware control circuit and control method thereof.
Background technology
As it is shown in figure 1, be the structural representation of storage system, backboard includes multiple slot, and can be by veneer
It is inserted on backboard.Along with the raising of storage system processing power, the veneer quantity being inserted on backboard gets more and more.In order to make
CPU (Central Processing Unit, central processing unit) can distinguish each veneer, then need to report the hard of veneer to CPU
Part information, this hardware information is indicated by low and high level, i.e. hardware information can be the low and high level of M position, when being 16 such as M,
Low and high level 1111111011001000 represents a hardware information, and low and high level 0111011001000000 represents that another is hard
Part information.
In order to report the hardware information of veneer to CPU, for each veneer, between backboard and veneer, configure M root signal
Line, veneer passes through the low and high level of M root holding wire parallel transmission M position to backboard.This backboard and CPLD (Complex
Programmable Logic Device, CPLD) between configure M root holding wire, backboard is believed by M root
The low and high level of M position is transferred to CPU, the CPU height by M position to CPLD, this CPLD by the low and high level of number line parallel transmission M position
Level conversion becomes hardware information.
For each veneer, need to configure M root holding wire between this veneer and backboard, and join between backboard and CPLD
Put M root holding wire.The quantity assuming veneer is n, then need to configure between n veneer and backboard respectively M root holding wire, and
M*n root holding wire is configured between backboard and CPLD.
If the value of M is 16, the value of n is 10, will configure 16 holding wires between the most each veneer and backboard, 10
Veneer is accomplished by 160 holding wires between veneer and backboard.Furthermore, it would be desirable to configure 160 letters between backboard and CPLD
Number line.Along with the increase of veneer quantity, the value of n can increase, thus causes the further increase of holding wire quantity.These signals
Line will take a large amount of PCB (Printed Circuit Board, the printed circuit board) space of mainboard and backboard, and wastes
The logical resource of CPLD.And, in order to dispose large number of signal lines between mainboard and backboard, need to increase the quantity of adapter,
The use of these adapters, can take PCB space further, increases risk.
Summary of the invention
The present invention provides a kind of hardware control circuit, including: processor, complex programmable logic device (CPLD), backboard, many
Individual veneer；For each veneer, between described veneer and described backboard, include data signal line, at described backboard with described
The data signal line that described veneer is corresponding is included between CPLD；Described veneer includes that parallel serial conversion module, described CPLD include string
And modular converter, coding/decoding module；
Described parallel serial conversion module, for obtaining the hardware information of described veneer, and by described veneer and described backboard
Between data signal line, in a serial fashion described hardware information is sent to described backboard；
Described serioparallel exchange module, for the data corresponding by veneer between described backboard with described CPLD, described
Holding wire, obtains the hardware information of described veneer in a serial fashion from described backboard, and is deposited by the hardware information of described veneer
Storage is in the data register that described veneer is corresponding；
Described coding/decoding module, for obtaining the hardware letter of described veneer in the data register that described veneer is corresponding
Breath, and the hardware information of described veneer is exported to described processor.
Described hardware information is represented by the low and high level data of M position, and M is the positive integer more than 1；
Described parallel serial conversion module, when sending described hardware information in a serial fashion, the most only sends a low and high level
Data, and by M time, the low and high level data of described M position are sent to described backboard；
Described serioparallel exchange module, when obtaining described hardware information in a serial fashion, the most only obtains a low and high level
Data, and by getting the low and high level data of described M position for M time from described backboard.
Between described veneer and backboard, include the first control signal wire, between backboard and CPLD, include all veneers pair
The first control signal wire answered；Described serioparallel exchange module is by the first control signal wire transmission first between backboard and CPLD
Signal, described backboard transmits the first signal by the first each veneer of control signal alignment that each veneer is corresponding；Described and go here and there
Modular converter is when sending described hardware information in a serial fashion, when sending low and high level data every time, according to described
First signal sends low and high level data；Described serioparallel exchange module when obtaining described hardware information in a serial fashion,
When obtaining low and high level data every time, according to described one low and high level data of first signal acquisition.
Between described veneer and backboard, include the second control signal wire, between backboard and CPLD, include all veneers pair
The second control signal wire answered；Described serioparallel exchange module is by the second control signal wire transmission second between backboard and CPLD
Signal, described backboard transmits secondary signal by the second each veneer of control signal alignment that each veneer is corresponding；Described and go here and there
Modular converter, is further used for after receiving secondary signal, judges whether to need to load described list according to described secondary signal
The hardware information of plate；If it is, obtain the hardware information of described veneer, and the hardware information of described veneer is loaded into described
In the shift register of veneer.
Between described veneer and backboard, include the 3rd control signal wire, between backboard and CPLD, include all veneers pair
The 3rd control signal wire answered；Serioparallel exchange module is by the 3rd control signal wire transmission the 3rd letter between backboard and CPLD
Number, backboard transmits the 3rd signal by the 3rd each veneer of control signal alignment that each veneer is corresponding；Described parallel-serial conversion mould
Block, is further used for after receiving the 3rd signal, determines whether to transmit the hard of described veneer according to described 3rd signal
Part information；If it is, read the hardware information of described veneer in described shift register, and in a serial fashion by described hardware
Information is sent to described backboard.
Described hardware control circuit also includes: baseboard management controller BMC；Described coding/decoding module is by described veneer
During hardware information exports to described processor, the hardware information of described veneer is exported to described BMC, by described BMC
The hardware information of described veneer is exported to described processor.
Described coding/decoding module during the hardware information of described veneer is exported to described BMC, described encoding and decoding
Module, for receiving the reading order from described BMC, and utilizes described reading order to determine the list of hardware information to be read
Plate, and in the data register that the veneer of described hardware information to be read is corresponding, obtain the hardware information of this veneer, and should
The hardware information of veneer stores in SDATA depositor；Hardware information in described SDATA depositor is placed on SDATA interface
On, described BMC from described SDATA interface, read this hardware information；Wherein, the most only by SDATA depositor
Hardware information is placed on SDATA interface, until described BMC after reading this hardware information described SDATA interface, and will
Another one hardware information in SDATA depositor is placed on SDATA interface.
Described veneer is host bus adaptor HBA card or quickly Peripheral Component Interconnect standard PCIe card or input
Output IO card；Described hardware information specifically includes one below or combination in any: type identification；Hardware version identifies；Flowing water
Number mark；Port number identifies.
The present invention provides the control method of a kind of hardware control circuit, described hardware control circuit to specifically include: processor,
Complex programmable logic device (CPLD), backboard, multiple veneer；Wherein, for each veneer, described veneer and described backboard it
Between include data signal line, between described backboard with described CPLD, include the data signal line that described veneer is corresponding；Described list
Plate includes that parallel serial conversion module, described CPLD include serioparallel exchange module, coding/decoding module；Said method comprising the steps of:
Described parallel serial conversion module obtains the hardware information of described veneer, and by between described veneer and described backboard
Data signal line, is sent to described backboard by described hardware information in a serial fashion；
Described serioparallel exchange module is by data signal corresponding to veneer between described backboard with described CPLD, described
Line, obtains the hardware information of described veneer in a serial fashion from described backboard, and is stored in by the hardware information of described veneer
In the data register that described veneer is corresponding；
Described coding/decoding module obtains the hardware information of described veneer in the data register that described veneer is corresponding, and will
The hardware information of described veneer exports to described processor.
Described hardware information is represented by the low and high level data of M position, and M is the positive integer more than 1；
Described parallel serial conversion module is by the data signal line between described veneer and described backboard, in a serial fashion by institute
Stating during hardware information is sent to described backboard, described parallel serial conversion module the most only sends low and high level data,
And by M time, the low and high level data of described M position are sent to described backboard；
Described serioparallel exchange module is by data signal corresponding to veneer between described backboard with described CPLD, described
Line, in the journey of the hardware information obtaining described veneer in a serial fashion, the most only obtains low and high level data, and passes through M
The secondary low and high level data getting described M position from described backboard.
Based on technique scheme, in the embodiment of the present invention, the hardware information of serial mode transmitting single plate can be passed through, and
Need not the hardware information by parallel mode transmitting single plate, from without configuring M (i.e. hardware letter between backboard and veneer
Figure place M of breath) root holding wire, it is not required that configure between backboard and CPLD M*n (i.e. quantity n) the root holding wire of veneer, only
Need between backboard and veneer, configure a single data holding wire and 3 control signal wires, totally 4 holding wires, and backboard with
N single data holding wire and 3 control signal wires, altogether n+3 root holding wire is configured, it is possible to transmit the hard of n veneer between CPLD
Part information, thus decrease the holding wire quantity between backboard and veneer, decrease the holding wire quantity between backboard and CPLD,
Save mainboard and the PCB layout space of backboard, be more reasonably utilized the resource of CPLD.It is additionally, since between mainboard and backboard
The holding wire quantity disposed reduces, and therefore can reduce the quantity of adapter, thus save the wiring space of eutergum, reduce
The risk of wiring, improves the safety of use.
Accompanying drawing explanation
In order to the embodiment of the present invention or technical scheme of the prior art are clearly described, below will be to the present invention
In embodiment or description of the prior art, the required accompanying drawing used is briefly described, it should be apparent that, in describing below
Accompanying drawing is only some embodiments described in the present invention, for those of ordinary skill in the art, it is also possible to according to these
Accompanying drawing obtains other accompanying drawing.
Fig. 1 is the structural representation of storage system；
Fig. 2 is the structure chart of the hardware control circuit in one embodiment of the present invention；
Fig. 3 is the schematic diagram of two 74HC165 chip cascades in one embodiment of the present invention；
Fig. 4 is the control time diagram of the parallel serial conversion module in one embodiment of the present invention；
Fig. 5 is the schematic diagram that the BMC in one embodiment of the present invention reads hardware information；
Fig. 6 is the flow chart of the control method of the hardware control circuit in one embodiment of the present invention.
Detailed description of the invention
In terminology used in the present invention merely for the sake of describing the purpose of specific embodiment, and the unrestricted present invention.This
" a kind of ", " described " and " being somebody's turn to do " of singulative used in bright and claims is also intended to include majority form, unless
Context clearly shows that other implication.It is also understood that term "and/or" used herein refers to comprise one or more
Any or all of the project of listing being associated may combination.
Although should be appreciated that in the present invention possible employing term first, second, third, etc. to describe various information, but this
A little information should not necessarily be limited by these terms.These terms are only used for same type of information is distinguished from each other out.Such as, without departing from
In the case of the scope of the invention, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as
One information.Depend on linguistic context, additionally, the word used " if " can be construed to " ... time " or " when ... "
Or " in response to determining ".
For problems of the prior art, the embodiment of the present invention proposes a kind of hardware control circuit, this hardware control
Circuit processed can apply to the network equipment (such as server, the network switch, storage device etc.) or the storage system of high availability
In system, this hardware control circuit can include but not limited to: processor (such as CPU etc.), CPLD, backboard, multiple veneers etc..At the back of the body
Include multiple slot on plate, and veneer can be inserted on backboard.Along with carrying of the network equipment/storage system processing power
Height, the veneer quantity being inserted on backboard gets more and more, with veneer quantity as n as a example by (positive integer more than 1), such as veneer 1, list
Plate 2 etc..
In one example, described veneer specifically can include but not limited to: (Host Bus Adapter, main frame is total for HBA
Line adapter) card or PCIE (Peripheral Component Interconnect Express, quick external components is mutual
Even standard) block or IO (Input Output, input and output) card.
In order to enable a processor to distinguish each veneer, then needing to report the hardware information of veneer to processor, this hardware is believed
Breath can be indicated by low and high level, it is assumed that the figure place of hardware information is M, then hardware information can be the low and high level of M position, i.e.
The binary numeral of M position (such as 0,1 etc.).In one example, this hardware information can include but not limited to one below or
Combination in any: type identification；Hardware version identifies；Serial number identifies；Port number identifies.Certainly, in actual applications, this is hard
Part information can also include out of Memory, and in the embodiment of the present invention, the content to this hardware information does not limits.Say for convenience
Bright, follow-up by hardware information be type identification, hardware version mark, serial number mark, port number mark as a example by.
In one example, type identification can be represented by the low and high level of 4, as low and high level 1111 represents class
Type A, low and high level 0111 represents type B.Hardware version mark can be represented by the low and high level of 4, such as low and high level
1110 represent hardware version A, and low and high level 0110 represents hardware version B.Serial number mark can be come by the low and high level of 4
Represent, as low and high level 1100 represents that serial number A, low and high level 0100 represent serial number B.Port number mark can be by 4
The low and high level of position represents, as low and high level 1000 represents that port number A, low and high level 0000 represent port number B.
Based on this, then hardware information can be the low and high level of 16, and the value of M is 16.Such as, low and high level
1111111011001000 represent a hardware information, and this hardware information can be type A+ hardware version A+ serial number A+ port
Number A.Low and high level 0111011001000000 represents another hardware information, and this hardware information can be type B+hardware version
This B+ serial number B+ port number B.
In conventional manner, as it is shown in figure 1, in order to transmit the hardware information of 16, for each veneer, at backboard and list
Configuring 16 holding wires between plate, veneer passes through the low and high level of 16 holding wire parallel transmissions 16 to backboard.For each
Veneer, configures 16 holding wires between backboard and CPLD, and backboard is by the low and high level of 16 holding wire parallel transmissions 16
To CPLD.Between backboard and CPLD, owing to configuring 16 holding wires for each veneer, therefore for n veneer, need to join
Put 16*n root holding wire.
In contrast to this, in the embodiment of the present invention, as in figure 2 it is shown, in one example, for each veneer, at list
A single data holding wire can be only included, can include between backboard with CPLD that this veneer is corresponding one between plate and backboard
Data signal line.Between backboard and CPLD, owing to configuring a single data holding wire for each veneer, therefore single for n
Plate, needs to configure n single data holding wire.
In one example, the first control signal wire can also be included between veneer and backboard, and at backboard and CPLD
Between can include the first control signal wire that all veneers are corresponding, the i.e. first control signal wire can be only one.At veneer
And can also include the second control signal wire between backboard, and can include between backboard with CPLD that all veneers are corresponding
Two control signal wires, the i.e. second control signal wire can be only one.The 3rd control can also be included between veneer and backboard
Holding wire, can include the 3rd control signal wire that all veneers are corresponding, the i.e. the 3rd control signal wire between backboard with CPLD
Can it be only one.
In sum, as in figure 2 it is shown, for each veneer, configure between backboard and veneer a single data holding wire and
Three control signal wires, i.e. altogether 4 holding wires of configuration.For each veneer, between backboard and CPLD, configure a single data
Holding wire, therefore for n veneer, needs to configure n single data holding wire；And, for n veneer, need to configure three controls
Holding wire processed, i.e. altogether configuration n+3 root holding wire.
In one example, veneer can include but not limited to parallel serial conversion module, and CPLD can include but not limited to string
And modular converter, coding/decoding module.Wherein, this parallel serial conversion module, for obtaining the hardware information of veneer, and by veneer with
Data signal line between backboard, is sent to backboard by this hardware information in a serial fashion.This serioparallel exchange module, is used for passing through
Data signal line between backboard with CPLD, that this veneer is corresponding, obtains the hardware letter of this veneer in a serial fashion from backboard
Breath, and the hardware information of this veneer is stored in the data register that this veneer is corresponding.This coding/decoding module, for single from this
Obtain the hardware information of this veneer in the data register that plate is corresponding, and the hardware information of this veneer is exported to processor.
In one example, hardware information can be represented by the low and high level data of M position, and M is the most whole more than 1
Number, if M is 16.Based on this, parallel serial conversion module, when sending this hardware information in a serial fashion, the most only sends a height
Level data, and by M time, the low and high level data of described M position are sent to backboard.And, serioparallel exchange module is with serial
When mode obtains this hardware information, the most only obtain low and high level data, and obtained by M time described to M from backboard
The low and high level data of position.
Such as, when the hardware information of veneer 1 is type A+ hardware version A+ serial number A+ port number A, then on veneer 1
Parallel serial conversion module can get the hardware information of veneer 1, this hardware information can be low and high level
1111111011001000.Based on this, parallel serial conversion module, by the data signal line between veneer 1 and backboard, is sent out for the first time
Send low and high level data 1, serioparallel exchange module by between backboard with CPLD, data signal line that this veneer 1 is corresponding, first
Secondary acquisition low and high level data 1 from backboard.Similar, parallel serial conversion module second time sends low and high level data 1, string
And modular converter second time obtains low and high level data 1 from backboard.By that analogy, parallel serial conversion module sends height the 15th time
Low-level data 0, serioparallel exchange module obtains low and high level data 0 the 15th time from backboard.Parallel serial conversion module the 16th
Secondary transmission low and high level data 0, serioparallel exchange module obtains low and high level data 0 the 16th time from backboard.
Obviously, in above process, parallel serial conversion module can send low and high level data every time only, and and go here and there turn
After die change block sends low and high level data, serioparallel exchange module just obtains this low and high level data from backboard.So
After, parallel serial conversion module sends low and high level data again, and serioparallel exchange module obtains this again from backboard
Low and high level data, by that analogy.In contrast to this, in conventional manner, not parallel serial conversion module and serioparallel exchange
Module, veneer is the low and high level data directly transmitting all M positions, and directly gets the height electricity of all M positions from backboard
Flat data.
In one example, serioparallel exchange module can be by the first control signal wire transmission the between backboard and CPLD
One signal, backboard transmits the first signal by the first each veneer of control signal alignment that each veneer is corresponding.And/or, string is also
Modular converter can be by the second control signal wire transmission secondary signal between backboard and CPLD, and backboard passes through each veneer pair
The second control signal alignment each veneer transmission secondary signal answered.And/or, serioparallel exchange module can pass through backboard and CPLD
Between the 3rd control signal wire transmission the 3rd signal, backboard is by the 3rd each list of control signal alignment corresponding to each veneer
Plate transmission the 3rd signal.
In one example, parallel serial conversion module, when sending hardware information in a serial fashion, can send one every time
During the low and high level data of position, send low and high level data according to this first signal；And, serioparallel exchange module is with serial
When mode obtains hardware information, can be high according to this first signal acquisition one when obtaining low and high level data every time
Low-level data.And/or, parallel serial conversion module, it is further used for after receiving secondary signal, can be according to this second letter
Number judge whether to need the hardware information of loading monoboard；If it is, obtain the hardware information of this veneer, and hard by this veneer
Part information is loaded in the shift register of this veneer.And/or, parallel serial conversion module, it is further used for receiving the 3rd letter
After number, can determine whether to transmit the hardware information of this veneer according to the 3rd signal；If it is, from shift LD
Read the hardware information of this veneer in device, and in a serial fashion this hardware information is sent to backboard.
In one example, the first signal can be CP signal, secondary signal can be PL (Parallel Load, parallel
Load) signal, the 3rd signal can be CE_N signal.Wherein, PL signal is loaded in parallel signal, when PL signal is low level
Time, represent and need to be loaded in shift register the I/O value (i.e. hardware information) of parallel serial conversion module, when PL signal is high electricity
At ordinary times, enable shift function is represented.CE_N signal is for enabling signal, and when CE_N signal is low level, expression can shift behaviour
Make, when CE_N signal is high level, represents and forbid shifting function.CP signal is data shift clock, each at CP signal
Rising edge pulse, parallel serial conversion module carries out shifting function, i.e. sends the low and high level data of, CP signal each under
Dropping along pulse, serioparallel exchange module receives the low and high level data of.Additionally, for CP signal, PL signal, CE_N signal
Processing procedure, will illustrate in the subsequent process of the embodiment of the present invention.
In one example, the parallel serial conversion module being positioned on veneer can include but not limited to 74HC165 chip, should
74HC165 chip is high-speed cmos (Complementary Metal Oxide Semiconductor, CMOS (Complementary Metal Oxide Semiconductor)
Quasiconductor) device is the shift register of 8 parallel-by-bit incoming serial outputs.
In one example, it is possible to use I/O port represents hardware information, such as the hardware information for M position, it is possible to use M
Individual I/O port represents hardware information, and these I/O ports can be indicated hardware information by the mode of pull-up resistor or pull down resistor.
Wherein, pull-up resistor be by uncertain signal by a resistance clamper at high level, and pull down resistor is by uncertain
Signal passes through a resistance clamper in low level.Such as, for hardware information 1111111011001000, then on first I/O port
Pull-up resistor, second I/O port pull-up resistor, by that analogy, and the 15th I/O port pull down resistor, the 16th I/O port pull down resistor.
In one example, as a example by parallel serial conversion module 74HC165 chip, it is assumed that hardware information includes 4 type marks
Know, 4 hardware version marks, 4 serial number marks, 4 bit port number marks, as it is shown on figure 3, owing to 74HC165 chip leads to
Often support 8 I/O ports, the hardware information of 8 can be represented, accordingly, it would be desirable to configure two 74HC165 chips in veneer, and will
Two 74HC165 chip cascades, each 74HC165 chip is responsible for the hardware information of 8.Such as, in figure 3, U1 is low level,
U2 is high-order.Receive the control signals such as CP signal, PL signal, CE_N signal when 74HC165 chip after, can enter according to clock
Row displacement, exports the hardware information of 16, output information is port number mark successively, serial number identifies, hardware version identifies,
Type identification.And, this hardware information of 16 is admitted to CPLD, forms data register DATA.In subsequent process
The output procedure of this hardware information is discussed in detail.
In actual applications, if the figure place of hardware information is bigger, then more 74HC165 chip can be cascaded, if M is 24
Time, then can cascade 3 74HC165 chips, this is repeated no more by the embodiment of the present invention.
Hereinafter CP signal, PL signal, the function of CE_N signal and handling process are described in detail.
In CPLD, serioparallel exchange module is responsible for the sequential logic of analog-converted, and exports CP signal, PL signal, CE_N
The control signals such as signal, and read the hardware information of veneer.
In one example, as shown in Figure 4, for the control time diagram of parallel serial conversion module, RESET is Global reset
Signal, 0 is Global reset, and 1 resets for release.CLK is sampling clock, and frequency is 1.8Mhz.CLK_CNT is clock counter,
Each trailing edge then counts 1, count down to 20 always, starts again to count from 0 again.PL signal is loaded in parallel signal, when this
When PL signal is low level, then it represents that need the I/O value (i.e. hardware information) of parallel serial conversion module is loaded into shift register
In, when this PL signal is high level, then it represents that enable shift function.CE_N signal is for enabling signal, when this CE_N signal is
During low level, then it represents that can be with shifting function, when this CE_N signal be high level, then it represents that forbid shifting function.CP signal
For data shift clock, at each rising edge pulse of this CP signal, parallel serial conversion module carries out shifting function, i.e. can send
The low and high level data of one, I/O port data are shifted one by low level Q0 to high-order Q7, this CP signal each decline along the pulse
Punching, serioparallel exchange module can receive the low and high level data of.
In one example, CP signal, PL signal, CE_N signal are that n veneer shares, as in figure 2 it is shown, therefore, and string
And the CP signal of modular converter transmission, PL signal, CE_N signal, can be transferred on each veneer by backboard, and each is single
Plate all can carry out relevant treatment based on CP signal, PL signal, CE_N signal, and the processing mode of each veneer is identical, follow-up with one
Illustrate as a example by the process of individual veneer.
After the release that powers on resets, start counting up, at each trailing edge of CLK, CLK_CNT is added one.At CLK_CNT=
When 1, then PL signal is low level.Parallel serial conversion module (such as parallel serial conversion module U1), after receiving PL signal, finds PL signal
It is low level, therefore, judges to need the hardware information of loading monoboard according to PL signal, and obtain the hardware information of veneer, will
The hardware information (i.e. the I/O value of parallel serial conversion module, it is the hardware information of 8) of veneer is loaded in shift register.Another
The hardware information of 8 also can be loaded in shift register by individual parallel serial conversion module (such as parallel serial conversion module U2).
Below in conjunction with the application scenarios shown in Fig. 3, the process being loaded into shift register is described in detail.At Fig. 3
In, the 8 of (D0-D7) hardware information can be loaded in the shift register of U2 by parallel serial conversion module U2.Parallel-serial conversion mould
The 8 of (D0-D7) hardware information can be first loaded in the shift register of parallel serial conversion module U1 by block U1, is carrying out
During shifting function, by parallel serial conversion module U2, these 8 hardware informations can be displaced in the shift register of U2 successively.
When value at CLK_CNT is equal to the arbitrary value (comprising 2 and 18) between 2 to 18, then PL signal is high level, CE_N
Signal is low level.Parallel serial conversion module, after receiving PL signal, finds that PL signal is high level, therefore can shift.At this
On the basis of, parallel serial conversion module, after receiving CE_N signal, finds that CE_N signal is low level, therefore judges according to CE_N signal
Go out and can enable shifting function, it is allowed to the hardware information of CPLD transmission veneer.Now parallel serial conversion module simply can be from shifting
Read the hardware information of veneer in bit register, and in a serial fashion hardware information is sent to backboard.But the most not with
Hardware information is sent to backboard by serial mode, but needs to wait CP signal, at each rising edge pulse of this CP signal, and goes here and there
Modular converter just carries out shifting function, the most just hardware information is sent to backboard.
In shift register, read the hardware information of veneer for parallel serial conversion module, and in a serial fashion hardware is believed
Breath is sent to the process of backboard, when the value at CLK_CNT is equal to the arbitrary value (comprising 2 and 18) between 2 to 18, and serioparallel exchange mould
Block output CP signal.Parallel serial conversion module is after receiving CP signal, at each rising edge pulse of this CP signal, carries out displacement behaviour
Make, i.e. send the low and high level data (hardware information of i.e.) of based on CP signal deciding.Serioparallel exchange module is defeated
When going out CP signal, in each trailing edge pulse of this CP signal, receive low and high level data (the hardware letter of i.e. of
Breath).
Below the process of displacement is described in detail.Each rising edge at CP signal comes interim, parallel serial conversion module
The shift register of U1 and U2 proceeds by shifting function.The data of first D7 put on the data line by Q7, and now one
Individual CP rising edge pulse, the shift register within U1 and U2 starts simultaneously at shifting function, and the shift register of U2 is sent by Q7
Going out a D7, D6 and move to the position of D7, D5 moves to the position of D6, arrives D0 successively and moves to the position of D1.The operation class of U1
Seemingly, when CP rising edge arrives, the D7 in the shift register of U1 is sent by Q7, and D6 moves to the position of D7, and D5 moves
To the position of D6, arrive D0 successively and move to the position of D1.Because U1 and U2 is the relation of cascade, when first CP arrives,
When the D7 of U1 internal shift depositor is removed by Q7, it is placed on the D0 position of the shift register of U2.When second CP pulse comes
When facing, the D6 of U2 moves on to the Q7 output of U2, and D5 moves to the position of D6, arrives D0 successively and moves to the position of D2, now U1
D7 moves to the D1 position of the shift register of U2, and the D6 of U1 moves to the position of the D0 of the shift register of U2, and the D5 of U1 moves
Moving the position of the D7 of U1, the D4 of U1 moves to the position of the D6 of U1, the like, the D0 of U1 moves to the position of the D2 of U1.
After 15 CP rising edge of a pulses, the data in the shift register of U1 and U2 are the most all moved out of.Certainly, above-mentioned is one
Individual embodiment, can also use other implementation in actual application, repeat this most in detail.
In one example, serioparallel exchange module (receives only one in the low and high level data receiving veneer every time
Low and high level data) after, these low and high level data are stored in the data register that this veneer is corresponding.Such as, for veneer 1
The low and high level data being shifted out, then in serioparallel exchange module stores it in the data register 1 of veneer 1 correspondence.For list
The low and high level data that plate 2 is shifted out, then in serioparallel exchange module stores it in the data register 2 of veneer 2 correspondence.With this
Analogize, the low and high level data being shifted out for veneer n, then serioparallel exchange module stores it in data corresponding for veneer n and posts
In storage n.
In one example, owing to hardware information includes the low and high level data of 16, first low and high level data is
Through being positioned on data signal line, therefore, parallel serial conversion module need 15 rising edge pulse of CP signal to carry out shifting function,
Thus altogether the low and high level data of 16 are transferred to serioparallel exchange module, by serioparallel exchange module by this low and high level of 16
Data store in the data register of corresponding veneer.
In sum, parallel serial conversion module need 15 rising edge pulse of CP signal to carry out shifting function, and go here and there also
Modular converter needs 16 trailing edges of CP signal to read low and high level data.It is additionally, since the value at CLK_CNT and is equal to 2
During arbitrary value (comprising 2 and 18) between 18, serioparallel exchange module output CP signal, and need 15 rising edges of CP signal
Pulse, therefore, it can when the value of CLK_CNT is 4 to 18, the output trailing edge pulse of CP signal.Based on this, CLK_CNT's
When value is 1, then PL signal can be exported, when the value of CLK_CNT is 2, then CE_N signal can be exported, in the value of CLK_CNT
From the beginning of 3, then can export pulse, and first export trailing edge.Due to had one on the data line, therefore go here and there and turn
Die change block needs first to take this position away.In subsequent process, parallel serial conversion module needs each rising edge pulse at CP signal
Carry out shifting function, and serioparallel exchange module need each trailing edge of CP signal to read low and high level data, at this not
Repeat again.
In one example, this hardware control circuit can also include: BMC (Baseboard Management
Controller, baseboard management controller), this BMC may be located on mainboard.Based on this, hard by veneer of coding/decoding module
During part information exports to processor, it is also possible to the hardware information of veneer is exported to BMC, and by BMC by this veneer
Hardware information exports to processor.
In one example, coding/decoding module directly can communicate with processor, it is possible to directly hard by veneer
Part information exports to processor.In another example, coding/decoding module directly can communicate with BMC, it is possible to directly
The hardware information of veneer is exported to BMC, and by BMC, the hardware information of this veneer is exported to processor.Coding/decoding module with
The process of processor communication, similar with the process that coding/decoding module communicates with BMC, can select according to actual needs to locate accordingly
Reason mode.Describe for convenience, in subsequent process, as a example by the process that coding/decoding module and BMC communicate, to above-mentioned mistake
Journey illustrates.
In one example, can be communicated by the hardware interface of standard between coding/decoding module and BMC, this standard
Hardware interface can be such as IIC (Inter-Integrated Circuit, IC bus).Certainly, coding/decoding module with
Can also be communicated by other interface between BMC, such as LPC (Low Pin Count, low pin count) interface, SPI
The process side of (Serial Peripheral Interface, Serial Peripheral Interface (SPI)) interface etc., its processing mode and IIC interface
Formula is similar to, and follow-up repeats no more, and illustrates as a example by IIC interface.Wherein, IIC interface has 2 holding wires, a holding wire
For clock line SCLK, BMC exporting clock signal to CPLD, another root holding wire is data wire SDATA, is used for carrying out two-way number
According to communication, S therein represents that serial, SDATA represent serial data, i.e. IIC interface is a serial protocol.
In one example, coding/decoding module during the hardware information of veneer is exported to BMC, encoding and decoding mould
Block, for receiving the reading order from BMC, it is possible to utilize this reading order to determine the veneer of hardware information to be read, and
The hardware information of this veneer is obtained in the data register that the veneer of this hardware information to be read is corresponding, and hard by this veneer
Part information stores in SDATA depositor.Further, the hardware information in this SDATA depositor is placed on SDATA interface
On, BMC from this SDATA interface, read this hardware information.Wherein, coding/decoding module is the most only by SDATA depositor
One hardware information is placed on SDATA interface, until BMC after reading this hardware information this SDATA interface, by SDATA
Another one hardware information in depositor is placed on SDATA interface, by that analogy.
Wherein, when the hardware information in SDATA depositor is placed on SDATA interface, can be from this SDATA depositor
In highest order start, successively a hardware information is placed on SDATA interface；Or the lowest order from SDATA depositor
Start, successively a hardware information is placed on SDATA interface.
In one example, as it is shown in figure 5, read the schematic diagram of hardware information for BMC.BMC is as IIC main frame, CPLD
Carry out data communication between machine, BMC and CPLD by IIC interface as IIC, CPLD simulates the volume solution of IIC agreement
Code module, is carried out data communication by coding/decoding module with BMC.
In one example, can use the clock rate of mode standard, the clock rate of this mode standard can be
100kbps.Under the clock rate of mode standard, for start bit, when SDATA trailing edge, then SCLK is high level；For
Stop bits, when SDATA is rising edge, then SCLK is high level.
Shown in Figure 5, coding/decoding module first detects start bit, then according to BMC clock receives 8 bit data of coming in,
Using front 7 address bits as IIC, using the 8th the read-write position as IIC (as 0 expression is write, 1 represents reading).Ground based on IIC
Position, location carries out address check, and after address check is correct, coding/decoding module provides response bits.BMC after receiving response bits,
Read operation or write operation can be carried out.
For write operation, BMC sends reading order, and this reading order can be the data of 8bit, the tables of data of this 8bit
Show the identification information of a veneer.Coding/decoding module receives this reading order according to clock, and this reading order is stored in CMD
Depositor, coding/decoding module provides response bits afterwards.BMC, after receiving response bits, i.e. sends stop bits.So, stream is write
Journey terminates, and returns RESET (start bit) state.
For read operation, coding/decoding module can obtain reading order from CMD depositor, and utilize this reading order true
The veneer of fixed hardware information to be read.In one example, owing to SDATA depositor can only store 8 bit data, therefore for one
The hardware information (i.e. 16) of individual veneer, coding/decoding module needs can complete hardware information for 2 times to report process.Based on
This, is when the 8bit data (i.e. reading order) in CMD depositor are 0, then can at SDATA register memory storage veneer 1 (i.e.
The veneer of hardware information to be read) least-significant byte data, and report this least-significant byte data；When the 8bit data in CMD depositor are 1
Time, then in the most-significant byte data of SDATA register memory storage veneer 1, and report this most-significant byte data.When in CMD depositor
When 8bit data are 2, then in the least-significant byte data of SDATA register memory storage veneer 2, and this least-significant byte data can be reported；When
When 8bit data in CMD depositor are 3, then in the most-significant byte data of SDATA register memory storage veneer 2, and can be reported this
Most-significant byte data.By that analogy, when the 8bit data in CMD depositor are 2k-2, then can store up at SDATA register memory
The least-significant byte data of veneer k, and report this least-significant byte data；When the 8bit data in CMD depositor are 2k-1, then can be
The most-significant byte data of SDATA register memory storage veneer k, and report this most-significant byte data.
In one example, it is assumed that the 8bit data in CMD depositor are 0, then coding/decoding module is from the number of veneer 1 correspondence
According to the least-significant byte data of acquisition veneer 1 in depositor, and the least-significant byte data of veneer 1 are stored in SDATA depositor, then will
A hardware information in SDATA depositor is placed on SDATA interface, treats that BMC reads this hardware from this SDATA interface
After information, the another one hardware information in SDATA depositor is placed on SDATA interface, by that analogy, this 8 bit data successively
It is placed on SDATA interface, BMC from SDATA depositor, is successively read this 8 bit data according to clock, and BMC can only read every time
Take a data.After the reading of this 8 bit data is complete, BMC sends response bits, sends stop bits the most again.So, flow process is read
Terminate, return RESET (start bit) state.And, the 8bit data in storage next time to CMD depositor are 1, coding/decoding module
In the data register of veneer 1 correspondence, obtain the most-significant byte data of veneer 1, and the most-significant byte data of veneer 1 are stored SDATA
In depositor, then a hardware information in SDATA depositor is placed on SDATA interface, treats that BMC is from this SDATA interface
After this hardware information of upper reading, the another one hardware information in SDATA depositor is placed on SDATA interface, with this type of
Pushing away, this 8 bit data is placed on SDATA interface successively, BMC be successively read this 8 figure place from SDATA depositor according to clock
According to, and BMC can only read a data every time.After the reading of this 8 bit data is complete, BMC sends response bits, sends the most again
Stop bits.So, read flow process and terminate, return RESET (start bit) state.So far, the biography of the hardware information of veneer 1 it is complete
Defeated, BMC the hardware information of veneer 1 is sent to processor and carries out subsequent treatment.For the processing procedure of other veneer, with list
The processing procedure of plate 1 is similar to, and does not repeats them here.
Based on technique scheme, in the embodiment of the present invention, the hardware information of serial mode transmitting single plate can be passed through, and
Need not the hardware information by parallel mode transmitting single plate, from without configuring M (i.e. hardware letter between backboard and veneer
Figure place M of breath) root holding wire, it is not required that configure between backboard and CPLD M*n (i.e. quantity n) the root holding wire of veneer, only
Need between backboard and veneer, configure a single data holding wire and 3 control signal wires, totally 4 holding wires, and backboard with
N single data holding wire and 3 control signal wires, altogether n+3 root holding wire is configured, it is possible to transmit the hard of n veneer between CPLD
Part information, thus decrease the holding wire quantity between backboard and veneer, decrease the holding wire quantity between backboard and CPLD,
Save mainboard and the PCB layout space of backboard, be more reasonably utilized the resource of CPLD.It is additionally, since between mainboard and backboard
The holding wire quantity disposed reduces, and therefore can reduce the quantity of adapter, thus save the wiring space of eutergum, reduce
The risk of wiring, improves the safety of use.
Based on the inventive concept similar with above-mentioned hardware control circuit, the embodiment of the present invention also proposes a kind of hardware controls
The control method of circuit, this hardware control circuit may include that processor, CPLD, backboard, multiple veneer.Wherein, for each
Veneer, includes data signal line between veneer and backboard, includes the data signal line that veneer is corresponding between backboard with CPLD；
This veneer includes parallel serial conversion module, and this CPLD can include serioparallel exchange module, coding/decoding module.Shown in Figure 6, the party
Method may comprise steps of:
Step 601, described parallel serial conversion module obtains the hardware information of described veneer, and by described veneer and the described back of the body
Data signal line between plate, is sent to described backboard by described hardware information in a serial fashion.
Step 602, described serioparallel exchange module is by the number between described backboard with described CPLD, described veneer is corresponding
According to holding wire, from described backboard, obtain the hardware information of described veneer in a serial fashion, and by the hardware information of described veneer
It is stored in the data register that described veneer is corresponding.
Step 603, described coding/decoding module obtains the hardware of described veneer in the data register that described veneer is corresponding
Information, and the hardware information of described veneer is exported to described processor.
In one example, described hardware information is represented by the low and high level data of M position, and M is the most whole more than 1
Number；Described parallel serial conversion module by data signal line between described veneer and described backboard, in a serial fashion by described firmly
During part information is sent to described backboard, described parallel serial conversion module the most only sends low and high level data, and leads to
Cross M time and the low and high level data of described M position are sent to described backboard；Described serioparallel exchange module passes through described backboard with described
The data signal line that veneer between CPLD, described is corresponding, in the journey of the hardware information obtaining described veneer in a serial fashion, often
Secondary obtains low and high level data, and by getting the low and high level data of described M position for M time from described backboard.
The several specific embodiments being only the present invention disclosed above, but, the present invention is not limited to this, any ability
What the technical staff in territory can think change all should fall into protection scope of the present invention.
Claims (10)
1. a hardware control circuit, it is characterised in that including: processor, complex programmable logic device (CPLD), backboard, many
Individual veneer；For each veneer, between described veneer and described backboard, include data signal line, at described backboard with described
The data signal line that described veneer is corresponding is included between CPLD；Described veneer includes that parallel serial conversion module, described CPLD include string
And modular converter, coding/decoding module；
Described parallel serial conversion module, for obtaining the hardware information of described veneer, and by between described veneer and described backboard
Data signal line, in a serial fashion described hardware information is sent to described backboard；
Described serioparallel exchange module, for the data signal corresponding by veneer between described backboard with described CPLD, described
Line, obtains the hardware information of described veneer in a serial fashion from described backboard, and is stored in by the hardware information of described veneer
In the data register that described veneer is corresponding；
Described coding/decoding module, for obtaining the hardware information of described veneer in the data register that described veneer is corresponding, and
The hardware information of described veneer is exported to described processor.
Hardware control circuit the most according to claim 1, it is characterised in that
Described hardware information is represented by the low and high level data of M position, and M is the positive integer more than 1；
Described parallel serial conversion module, when sending described hardware information in a serial fashion, the most only sends a low and high level number
According to, and by M time, the low and high level data of described M position are sent to described backboard；
Described serioparallel exchange module, when obtaining described hardware information in a serial fashion, the most only obtains a low and high level number
According to, and by getting the low and high level data of described M position for M time from described backboard.
Hardware control circuit the most according to claim 2, it is characterised in that include first between described veneer and backboard
Control signal wire, includes the first control signal wire that all veneers are corresponding between backboard with CPLD；Described serioparallel exchange module
Transmitting the first signal by the first control signal wire between backboard and CPLD, described backboard passes through first that each veneer is corresponding
The each veneer of control signal alignment transmits the first signal；
Described parallel serial conversion module, when sending described hardware information in a serial fashion, is sending low and high level data every time
Time, send low and high level data according to described first signal；
Described serioparallel exchange module, when obtaining described hardware information in a serial fashion, is obtaining low and high level data every time
Time, according to described one low and high level data of first signal acquisition.
Hardware control circuit the most according to claim 1, it is characterised in that include second between described veneer and backboard
Control signal wire, includes the second control signal wire that all veneers are corresponding between backboard with CPLD；Described serioparallel exchange module
By the second control signal wire transmission secondary signal between backboard and CPLD, described backboard passes through second that each veneer is corresponding
Control signal alignment each veneer transmission secondary signal；
Described parallel serial conversion module, is further used for after receiving described secondary signal, according to the judgement of described secondary signal is
The no hardware information needing to load described veneer；If it is, obtain the hardware information of described veneer, and hard by described veneer
Part information is loaded in the shift register of described veneer.
Hardware control circuit the most according to claim 4, it is characterised in that include the 3rd between described veneer and backboard
Control signal wire, includes the 3rd control signal wire that all veneers are corresponding between backboard with CPLD；Described serioparallel exchange module
By the 3rd control signal wire transmission the 3rd signal between backboard and CPLD, described backboard passes through the 3rd that each veneer is corresponding
Control signal alignment each veneer transmission the 3rd signal；
Described parallel serial conversion module, is further used for after receiving described 3rd signal, according to described 3rd signal judgement is
The no hardware information allowing to transmit described veneer；If it is, read the hardware letter of described veneer in described shift register
Breath, and in a serial fashion described hardware information is sent to described backboard.
Hardware control circuit the most according to claim 1, it is characterised in that
Described hardware control circuit also includes: baseboard management controller BMC；Described coding/decoding module is at the hardware by described veneer
During information exports to described processor, the hardware information of described veneer is exported to described BMC, by described BMC by institute
The hardware information stating veneer exports to described processor.
Hardware control circuit the most according to claim 6, it is characterised in that
Described coding/decoding module during the hardware information of described veneer is exported to described BMC, described coding/decoding module,
For receiving from the reading order of described BMC, and described reading order is utilized to determine the veneer of hardware information to be read, and from
The hardware information of this veneer is obtained in the data register that the veneer of described hardware information to be read is corresponding, and hard by this veneer
Part information stores in SDATA depositor；Hardware information in described SDATA depositor is placed on SDATA interface, by described
BMC reads this hardware information from described SDATA interface；Wherein, the most only a hardware information in SDATA depositor is put
On SDATA interface, until described BMC after reading this hardware information described SDATA interface, by SDATA depositor
Another one hardware information be placed on SDATA interface.
Hardware control circuit the most according to claim 1, it is characterised in that described veneer is host bus adaptor HBA
Card or quickly Peripheral Component Interconnect standard PCIe card or input and output IO card；
Described hardware information specifically includes one below or combination in any:
Type identification；Hardware version identifies；Serial number identifies；Port number identifies.
9. the control method of a hardware control circuit, it is characterised in that described hardware control circuit specifically includes: processor,
Complex programmable logic device (CPLD), backboard, multiple veneer；Wherein, for each veneer, described veneer and described backboard it
Between include data signal line, between described backboard with described CPLD, include the data signal line that described veneer is corresponding；Described list
Plate includes that parallel serial conversion module, described CPLD include serioparallel exchange module, coding/decoding module；Said method comprising the steps of:
Described parallel serial conversion module obtains the hardware information of described veneer, and by the data between described veneer and described backboard
Holding wire, is sent to described backboard by described hardware information in a serial fashion；
Described serioparallel exchange module passes through the data signal line between described backboard with described CPLD, described veneer is corresponding, with
Serial mode obtains the hardware information of described veneer from described backboard, and the hardware information of described veneer is stored in described list
In the data register that plate is corresponding；
Described coding/decoding module obtains the hardware information of described veneer in the data register that described veneer is corresponding, and by described
The hardware information of veneer exports to described processor.
Method the most according to claim 9, it is characterised in that
Described hardware information is represented by the low and high level data of M position, and M is the positive integer more than 1；
Described parallel serial conversion module by data signal line between described veneer and described backboard, in a serial fashion by described firmly
During part information is sent to described backboard, described parallel serial conversion module the most only sends low and high level data, and leads to
Cross M time and the low and high level data of described M position are sent to described backboard；
Described serioparallel exchange module passes through the data signal line between described backboard with described CPLD, described veneer is corresponding, with
In the journey of the hardware information that serial mode obtains described veneer, the most only obtain low and high level data, and by M time from institute
State the low and high level data getting described M position on backboard.
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| CN110764585A (en) * | 2019-09-12 | 2020-02-07 | 苏州浪潮智能科技有限公司 | Universal independent BMC board card |
| CN113051204A (en) * | 2019-12-27 | 2021-06-29 | 中车大连电力牵引研发中心有限公司 | Serial backplane bus communication method and system |
| CN111628944A (en) * | 2020-05-25 | 2020-09-04 | 深圳市信锐网科技术有限公司 | Switch and switch system |
| CN111628944B (en) * | 2020-05-25 | 2022-03-25 | 深圳市信锐网科技术有限公司 | Switch and switch system |
| CN113868159A (en) * | 2020-06-30 | 2021-12-31 | 中车株洲电力机车研究所有限公司 | IO module, in-module master control device and in-module interface device identification method |
| CN112328054A (en) * | 2020-11-02 | 2021-02-05 | 联想(北京)有限公司 | Control device and control method |
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Address after: Hangzhou City, Zhejiang Province, Binjiang District West Street 310053 Qianmo Road No. 482 building eleventh layer to the twelfth layer A Applicant after: Hangzhou Sequoia Polytron Technologies Inc Address before: Hangzhou City, Zhejiang Province, Binjiang District West Street 310053 Qianmo Road No. 482 building eleventh layer to the twelfth layer A Applicant before: Hangzhou MacroSAN Technologies Co., Ltd. |
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Application publication date: 20161221 |